1Device tree configuration for i2c-ocores 2 3Required properties: 4- compatible : "opencores,i2c-ocores" 5 "aeroflexgaisler,i2cmst" 6 "sifive,fu540-c000-i2c", "sifive,i2c0" 7 For Opencore based I2C IP block reimplemented in 8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt 9 for additional details. 10- reg : bus address start and address range size of device 11- clocks : handle to the controller clock; see the note below. 12 Mutually exclusive with opencores,ip-clock-frequency 13- opencores,ip-clock-frequency: frequency of the controller clock in Hz; 14 see the note below. Mutually exclusive with clocks 15- #address-cells : should be <1> 16- #size-cells : should be <0> 17 18Optional properties: 19- interrupts : interrupt number. 20- clock-frequency : frequency of bus clock in Hz; see the note below. 21 Defaults to 100 KHz when the property is not specified 22- reg-shift : device register offsets are shifted by this value 23- reg-io-width : io register width in bytes (1, 2 or 4) 24- regstep : deprecated, use reg-shift above 25 26Note 27clock-frequency property is meant to control the bus frequency for i2c bus 28drivers, but it was incorrectly used to specify i2c controller input clock 29frequency. So the following rules are set to fix this situation: 30- if clock-frequency is present and neither opencores,ip-clock-frequency nor 31 clocks are, then clock-frequency specifies i2c controller clock frequency. 32 This is to keep backwards compatibility with setups using old DTB. i2c bus 33 frequency is fixed at 100 KHz. 34- if clocks is present it specifies i2c controller clock. clock-frequency 35 property specifies i2c bus frequency. 36- if opencores,ip-clock-frequency is present it specifies i2c controller 37 clock frequency. clock-frequency property specifies i2c bus frequency. 38 39Examples: 40 41 i2c0: ocores@a0000000 { 42 #address-cells = <1>; 43 #size-cells = <0>; 44 compatible = "opencores,i2c-ocores"; 45 reg = <0xa0000000 0x8>; 46 interrupts = <10>; 47 opencores,ip-clock-frequency = <20000000>; 48 49 reg-shift = <0>; /* 8 bit registers */ 50 reg-io-width = <1>; /* 8 bit read/write */ 51 52 dummy@60 { 53 compatible = "dummy"; 54 reg = <0x60>; 55 }; 56 }; 57or 58 i2c0: ocores@a0000000 { 59 #address-cells = <1>; 60 #size-cells = <0>; 61 compatible = "opencores,i2c-ocores"; 62 reg = <0xa0000000 0x8>; 63 interrupts = <10>; 64 clocks = <&osc>; 65 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ 66 67 reg-shift = <0>; /* 8 bit registers */ 68 reg-io-width = <1>; /* 8 bit read/write */ 69 70 dummy@60 { 71 compatible = "dummy"; 72 reg = <0x60>; 73 }; 74 }; 75