1Xilinx XADC device driver 2 3This binding document describes the bindings for both of them since the 4bindings are very similar. The Xilinx XADC is a ADC that can be found in the 5series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. 6Currently two different frontends for the DRP interface exist. One that is only 7available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The 8other one is available on all series 7 platforms and is a softmacro with a AXI 9interface. This binding document describes the bindings for both of them since 10the bindings are very similar. 11 12Required properties: 13 - compatible: Should be one of 14 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device 15 configuration interface to interface to the XADC hardmacro. 16 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to 17 interface to the XADC hardmacro. 18 - reg: Address and length of the register set for the device 19 - interrupts: Interrupt for the XADC control interface. 20 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock, 21 when using the AXI-XADC pcore this must be the clock that provides the 22 clock to the AXI bus interface of the core. 23 24Optional properties: 25 - xlnx,external-mux: 26 * "none": No external multiplexer is used, this is the default 27 if the property is omitted. 28 * "single": External multiplexer mode is used with one 29 multiplexer. 30 * "dual": External multiplexer mode is used with two 31 multiplexers for simultaneous sampling. 32 - xlnx,external-mux-channel: Configures which pair of pins is used to 33 sample data in external mux mode. 34 Valid values for single external multiplexer mode are: 35 0: VP/VN 36 1: VAUXP[0]/VAUXN[0] 37 2: VAUXP[1]/VAUXN[1] 38 ... 39 16: VAUXP[15]/VAUXN[15] 40 Valid values for dual external multiplexer mode are: 41 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8] 42 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9] 43 ... 44 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15] 45 46 This property needs to be present if the device is configured for 47 external multiplexer mode (either single or dual). If the device is 48 not using external multiplexer mode the property is ignored. 49 - xnlx,channels: List of external channels that are connected to the ADC 50 Required properties: 51 * #address-cells: Should be 1. 52 * #size-cells: Should be 0. 53 54 The child nodes of this node represent the external channels which are 55 connected to the ADC. If the property is no present no external 56 channels will be assumed to be connected. 57 58 Each child node represents one channel and has the following 59 properties: 60 Required properties: 61 * reg: Pair of pins the channel is connected to. 62 0: VP/VN 63 1: VAUXP[0]/VAUXN[0] 64 2: VAUXP[1]/VAUXN[1] 65 ... 66 16: VAUXP[15]/VAUXN[15] 67 Note each channel number should only be used at most 68 once. 69 Optional properties: 70 * xlnx,bipolar: If set the channel is used in bipolar 71 mode. 72 73 74Examples: 75 xadc@f8007100 { 76 compatible = "xlnx,zynq-xadc-1.00.a"; 77 reg = <0xf8007100 0x20>; 78 interrupts = <0 7 4>; 79 interrupt-parent = <&gic>; 80 clocks = <&pcap_clk>; 81 82 xlnx,channels { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 channel@0 { 86 reg = <0>; 87 }; 88 channel@1 { 89 reg = <1>; 90 }; 91 channel@8 { 92 reg = <8>; 93 }; 94 }; 95 }; 96 97 xadc@43200000 { 98 compatible = "xlnx,axi-xadc-1.00.a"; 99 reg = <0x43200000 0x1000>; 100 interrupts = <0 53 4>; 101 interrupt-parent = <&gic>; 102 clocks = <&fpga1_clk>; 103 104 xlnx,channels { 105 #address-cells = <1>; 106 #size-cells = <0>; 107 channel@0 { 108 reg = <0>; 109 xlnx,bipolar; 110 }; 111 }; 112 }; 113