1Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY 2------------------------------------------------- 3 4Required properties: 5- compatible : should be one of the listed compatibles: 6 - "samsung,s5pv210-mipi-video-phy" 7 - "samsung,exynos5420-mipi-video-phy" 8 - "samsung,exynos5433-mipi-video-phy" 9- #phy-cells : from the generic phy bindings, must be 1; 10 11In case of s5pv210 and exynos5420 compatible PHYs: 12- syscon - phandle to the PMU system controller 13 14In case of exynos5433 compatible PHY: 15 - samsung,pmu-syscon - phandle to the PMU system controller 16 - samsung,disp-sysreg - phandle to the DISP system registers controller 17 - samsung,cam0-sysreg - phandle to the CAM0 system registers controller 18 - samsung,cam1-sysreg - phandle to the CAM1 system registers controller 19 20For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in 21the PHY specifier identifies the PHY and its meaning is as follows: 22 0 - MIPI CSIS 0, 23 1 - MIPI DSIM 0, 24 2 - MIPI CSIS 1, 25 3 - MIPI DSIM 1. 26"samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy" 27supports additional fifth PHY: 28 4 - MIPI CSIS 2. 29 30Samsung Exynos SoC series Display Port PHY 31------------------------------------------------- 32 33Required properties: 34- compatible : should be one of the following supported values: 35 - "samsung,exynos5250-dp-video-phy" 36 - "samsung,exynos5420-dp-video-phy" 37- samsung,pmu-syscon: phandle for PMU system controller interface, used to 38 control pmu registers for power isolation. 39- #phy-cells : from the generic PHY bindings, must be 0; 40 41Samsung S5P/Exynos SoC series USB PHY 42------------------------------------------------- 43 44Required properties: 45- compatible : should be one of the listed compatibles: 46 - "samsung,exynos3250-usb2-phy" 47 - "samsung,exynos4210-usb2-phy" 48 - "samsung,exynos4x12-usb2-phy" 49 - "samsung,exynos5250-usb2-phy" 50 - "samsung,s5pv210-usb2-phy" 51- reg : a list of registers used by phy driver 52 - first and obligatory is the location of phy modules registers 53- samsung,sysreg-phandle - handle to syscon used to control the system registers 54- samsung,pmureg-phandle - handle to syscon used to control PMU registers 55- #phy-cells : from the generic phy bindings, must be 1; 56- clocks and clock-names: 57 - the "phy" clock is required by the phy module, used as a gate 58 - the "ref" clock is used to get the rate of the clock provided to the 59 PHY module 60 61Optional properties: 62- vbus-supply: power-supply phandle for vbus power source 63 64The first phandle argument in the PHY specifier identifies the PHY, its 65meaning is compatible dependent. For the currently supported SoCs (Exynos 4210 66and Exynos 4212) it is as follows: 67 0 - USB device ("device"), 68 1 - USB host ("host"), 69 2 - HSIC0 ("hsic0"), 70 3 - HSIC1 ("hsic1"), 71Exynos3250 has only USB device phy available as phy 0. 72 73Exynos 4210 and Exynos 4212 use mode switching and require that mode switch 74register is supplied. 75 76Example: 77 78For Exynos 4412 (compatible with Exynos 4212): 79 80usbphy: phy@125b0000 { 81 compatible = "samsung,exynos4x12-usb2-phy"; 82 reg = <0x125b0000 0x100>; 83 clocks = <&clock 305>, <&clock 2>; 84 clock-names = "phy", "ref"; 85 #phy-cells = <1>; 86 samsung,sysreg-phandle = <&sys_reg>; 87 samsung,pmureg-phandle = <&pmu_reg>; 88}; 89 90Then the PHY can be used in other nodes such as: 91 92phy-consumer@12340000 { 93 phys = <&usbphy 2>; 94 phy-names = "phy"; 95}; 96 97Refer to DT bindings documentation of particular PHY consumer devices for more 98information about required PHYs and the way of specification. 99 100Samsung SATA PHY Controller 101--------------------------- 102 103SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. 104Each SATA PHY controller should have its own node. 105 106Required properties: 107- compatible : compatible list, contains "samsung,exynos5250-sata-phy" 108- reg : offset and length of the SATA PHY register set; 109- #phy-cells : must be zero 110- clocks : must be exactly one entry 111- clock-names : must be "sata_phyctrl" 112- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments 113- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments 114 115Example: 116 sata_phy: sata-phy@12170000 { 117 compatible = "samsung,exynos5250-sata-phy"; 118 reg = <0x12170000 0x1ff>; 119 clocks = <&clock 287>; 120 clock-names = "sata_phyctrl"; 121 #phy-cells = <0>; 122 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; 123 samsung,syscon-phandle = <&pmu_syscon>; 124 }; 125 126Device-Tree bindings for sataphy i2c client driver 127-------------------------------------------------- 128 129Required properties: 130compatible: Should be "samsung,exynos-sataphy-i2c" 131- reg: I2C address of the sataphy i2c device. 132 133Example: 134 135 sata_phy_i2c:sata-phy@38 { 136 compatible = "samsung,exynos-sataphy-i2c"; 137 reg = <0x38>; 138 }; 139 140Samsung Exynos5 SoC series USB DRD PHY controller 141-------------------------------------------------- 142 143Required properties: 144- compatible : Should be set to one of the following supported values: 145 - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC, 146 - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC. 147 - "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC. 148 - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC. 149- reg : Register offset and length of USB DRD PHY register set; 150- clocks: Clock IDs array as required by the controller 151- clock-names: names of clocks correseponding to IDs in the clock property; 152 Required clocks: 153 - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), 154 used for register access. 155 - ref: PHY's reference clock (usually crystal clock), used for 156 PHY operations, associated by phy name. It is used to 157 determine bit values for clock settings register. 158 For Exynos5420 this is given as 'sclk_usbphy30' in CMU. 159 - optional clocks: Exynos5433 & Exynos7 SoC has now following additional 160 gate clocks available: 161 - phy_pipe: for PIPE3 phy 162 - phy_utmi: for UTMI+ phy 163 - itp: for ITP generation 164- samsung,pmu-syscon: phandle for PMU system controller interface, used to 165 control pmu registers for power isolation. 166- #phy-cells : from the generic PHY bindings, must be 1; 167 168For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy" 169compatible PHYs, the second cell in the PHY specifier identifies the 170PHY id, which is interpreted as follows: 171 0 - UTMI+ type phy, 172 1 - PIPE3 type phy, 173 174Example: 175 usbdrd_phy: usbphy@12100000 { 176 compatible = "samsung,exynos5250-usbdrd-phy"; 177 reg = <0x12100000 0x100>; 178 clocks = <&clock 286>, <&clock 1>; 179 clock-names = "phy", "ref"; 180 samsung,pmu-syscon = <&pmu_system_controller>; 181 #phy-cells = <1>; 182 }; 183 184- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers, 185 'usbdrd_phy' nodes should have numbered alias in the aliases node, 186 in the form of usbdrdphyN, N = 0, 1... (depending on number of 187 controllers). 188Example: 189 aliases { 190 usbdrdphy0 = &usb3_phy0; 191 usbdrdphy1 = &usb3_phy1; 192 }; 193 194Samsung Exynos SoC series PCIe PHY controller 195-------------------------------------------------- 196Required properties: 197- compatible : Should be set to "samsung,exynos5440-pcie-phy" 198- #phy-cells : Must be zero 199- reg : a register used by phy driver. 200 - First is for phy register, second is for block register. 201- reg-names : Must be set to "phy" and "block". 202 203Example: 204 pcie_phy0: pcie-phy@270000 { 205 #phy-cells = <0>; 206 compatible = "samsung,exynos5440-pcie-phy"; 207 reg = <0x270000 0x1000>, <0x271000 0x40>; 208 reg-names = "phy", "block"; 209 }; 210