1-------------------------------------------------------------------------- 2 = Zynq UltraScale+ MPSoC and Versal reset driver binding = 3-------------------------------------------------------------------------- 4The Zynq UltraScale+ MPSoC and Versal has several different resets. 5 6See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information 7about zynqmp resets. 8 9Please also refer to reset.txt in this directory for common reset 10controller binding usage. 11 12Required Properties: 13- compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform 14 "xlnx,versal-reset" for Versal platform 15- #reset-cells: Specifies the number of cells needed to encode reset 16 line, should be 1 17 18------- 19Example 20------- 21 22firmware { 23 zynqmp_firmware: zynqmp-firmware { 24 compatible = "xlnx,zynqmp-firmware"; 25 method = "smc"; 26 27 zynqmp_reset: reset-controller { 28 compatible = "xlnx,zynqmp-reset"; 29 #reset-cells = <1>; 30 }; 31 }; 32}; 33 34Specifying reset lines connected to IP modules 35============================================== 36 37Device nodes that need access to reset lines should 38specify them as a reset phandle in their corresponding node as 39specified in reset.txt. 40 41For list of all valid reset indices for Zynq UltraScale+ MPSoC see 42<dt-bindings/reset/xlnx-zynqmp-resets.h> 43For list of all valid reset indices for Versal see 44<dt-bindings/reset/xlnx-versal-resets.h> 45 46Example: 47 48serdes: zynqmp_phy@fd400000 { 49 ... 50 51 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; 52 reset-names = "sata_rst"; 53 54 ... 55}; 56