1/* 2 * Device Tree Source for AM33XX SoC 3 * 4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/bus/ti-sysc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/pinctrl/am33xx.h> 14#include <dt-bindings/clock/am3.h> 15 16/ { 17 compatible = "ti,am33xx"; 18 interrupt-parent = <&intc>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 chosen { }; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 serial3 = &uart3; 31 serial4 = &uart4; 32 serial5 = &uart5; 33 d-can0 = &dcan0; 34 d-can1 = &dcan1; 35 usb0 = &usb0; 36 usb1 = &usb1; 37 phy0 = &usb0_phy; 38 phy1 = &usb1_phy; 39 ethernet0 = &cpsw_emac0; 40 ethernet1 = &cpsw_emac1; 41 spi0 = &spi0; 42 spi1 = &spi1; 43 mmc0 = &mmc1; 44 mmc1 = &mmc2; 45 mmc2 = &mmc3; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 cpu@0 { 52 compatible = "arm,cortex-a8"; 53 enable-method = "ti,am3352"; 54 device_type = "cpu"; 55 reg = <0>; 56 57 operating-points-v2 = <&cpu0_opp_table>; 58 59 clocks = <&dpll_mpu_ck>; 60 clock-names = "cpu"; 61 62 clock-latency = <300000>; /* From omap-cpufreq driver */ 63 cpu-idle-states = <&mpu_gate>; 64 }; 65 66 idle-states { 67 mpu_gate: mpu_gate { 68 compatible = "arm,idle-state"; 69 entry-latency-us = <40>; 70 exit-latency-us = <90>; 71 min-residency-us = <300>; 72 ti,idle-wkup-m3; 73 }; 74 }; 75 }; 76 77 cpu0_opp_table: opp-table { 78 compatible = "operating-points-v2-ti-cpu"; 79 syscon = <&scm_conf>; 80 81 /* 82 * The three following nodes are marked with opp-suspend 83 * because the can not be enabled simultaneously on a 84 * single SoC. 85 */ 86 opp50-300000000 { 87 opp-hz = /bits/ 64 <300000000>; 88 opp-microvolt = <950000 931000 969000>; 89 opp-supported-hw = <0x06 0x0010>; 90 opp-suspend; 91 }; 92 93 opp100-275000000 { 94 opp-hz = /bits/ 64 <275000000>; 95 opp-microvolt = <1100000 1078000 1122000>; 96 opp-supported-hw = <0x01 0x00FF>; 97 opp-suspend; 98 }; 99 100 opp100-300000000 { 101 opp-hz = /bits/ 64 <300000000>; 102 opp-microvolt = <1100000 1078000 1122000>; 103 opp-supported-hw = <0x06 0x0020>; 104 opp-suspend; 105 }; 106 107 opp100-500000000 { 108 opp-hz = /bits/ 64 <500000000>; 109 opp-microvolt = <1100000 1078000 1122000>; 110 opp-supported-hw = <0x01 0xFFFF>; 111 }; 112 113 opp100-600000000 { 114 opp-hz = /bits/ 64 <600000000>; 115 opp-microvolt = <1100000 1078000 1122000>; 116 opp-supported-hw = <0x06 0x0040>; 117 }; 118 119 opp120-600000000 { 120 opp-hz = /bits/ 64 <600000000>; 121 opp-microvolt = <1200000 1176000 1224000>; 122 opp-supported-hw = <0x01 0xFFFF>; 123 }; 124 125 opp120-720000000 { 126 opp-hz = /bits/ 64 <720000000>; 127 opp-microvolt = <1200000 1176000 1224000>; 128 opp-supported-hw = <0x06 0x0080>; 129 }; 130 131 oppturbo-720000000 { 132 opp-hz = /bits/ 64 <720000000>; 133 opp-microvolt = <1260000 1234800 1285200>; 134 opp-supported-hw = <0x01 0xFFFF>; 135 }; 136 137 oppturbo-800000000 { 138 opp-hz = /bits/ 64 <800000000>; 139 opp-microvolt = <1260000 1234800 1285200>; 140 opp-supported-hw = <0x06 0x0100>; 141 }; 142 143 oppnitro-1000000000 { 144 opp-hz = /bits/ 64 <1000000000>; 145 opp-microvolt = <1325000 1298500 1351500>; 146 opp-supported-hw = <0x04 0x0200>; 147 }; 148 }; 149 150 pmu@4b000000 { 151 compatible = "arm,cortex-a8-pmu"; 152 interrupts = <3>; 153 reg = <0x4b000000 0x1000000>; 154 ti,hwmods = "debugss"; 155 }; 156 157 /* 158 * The soc node represents the soc top level view. It is used for IPs 159 * that are not memory mapped in the MPU view or for the MPU itself. 160 */ 161 soc { 162 compatible = "ti,omap-infra"; 163 mpu { 164 compatible = "ti,omap3-mpu"; 165 ti,hwmods = "mpu"; 166 pm-sram = <&pm_sram_code 167 &pm_sram_data>; 168 }; 169 }; 170 171 /* 172 * XXX: Use a flat representation of the AM33XX interconnect. 173 * The real AM33XX interconnect network is quite complex. Since 174 * it will not bring real advantage to represent that in DT 175 * for the moment, just use a fake OCP bus entry to represent 176 * the whole bus hierarchy. 177 */ 178 ocp: ocp { 179 compatible = "simple-bus"; 180 #address-cells = <1>; 181 #size-cells = <1>; 182 ranges; 183 ti,hwmods = "l3_main"; 184 185 l4_wkup: interconnect@44c00000 { 186 wkup_m3: wkup_m3@100000 { 187 compatible = "ti,am3352-wkup-m3"; 188 reg = <0x100000 0x4000>, 189 <0x180000 0x2000>; 190 reg-names = "umem", "dmem"; 191 ti,hwmods = "wkup_m3"; 192 ti,pm-firmware = "am335x-pm-firmware.elf"; 193 }; 194 }; 195 l4_per: interconnect@48000000 { 196 }; 197 l4_fw: interconnect@47c00000 { 198 }; 199 l4_fast: interconnect@4a000000 { 200 }; 201 l4_mpuss: interconnect@4b140000 { 202 }; 203 204 intc: interrupt-controller@48200000 { 205 compatible = "ti,am33xx-intc"; 206 interrupt-controller; 207 #interrupt-cells = <1>; 208 reg = <0x48200000 0x1000>; 209 }; 210 211 target-module@49000000 { 212 compatible = "ti,sysc-omap4", "ti,sysc"; 213 reg = <0x49000000 0x4>; 214 reg-names = "rev"; 215 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>; 216 clock-names = "fck"; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 ranges = <0x0 0x49000000 0x10000>; 220 221 edma: dma@0 { 222 compatible = "ti,edma3-tpcc"; 223 reg = <0 0x10000>; 224 reg-names = "edma3_cc"; 225 interrupts = <12 13 14>; 226 interrupt-names = "edma3_ccint", "edma3_mperr", 227 "edma3_ccerrint"; 228 dma-requests = <64>; 229 #dma-cells = <2>; 230 231 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, 232 <&edma_tptc2 0>; 233 234 ti,edma-memcpy-channels = <20 21>; 235 }; 236 }; 237 238 target-module@49800000 { 239 compatible = "ti,sysc-omap4", "ti,sysc"; 240 reg = <0x49800000 0x4>, 241 <0x49800010 0x4>; 242 reg-names = "rev", "sysc"; 243 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 244 ti,sysc-midle = <SYSC_IDLE_FORCE>; 245 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 246 <SYSC_IDLE_SMART>; 247 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>; 248 clock-names = "fck"; 249 #address-cells = <1>; 250 #size-cells = <1>; 251 ranges = <0x0 0x49800000 0x100000>; 252 253 edma_tptc0: dma@0 { 254 compatible = "ti,edma3-tptc"; 255 reg = <0 0x100000>; 256 interrupts = <112>; 257 interrupt-names = "edma3_tcerrint"; 258 }; 259 }; 260 261 target-module@49900000 { 262 compatible = "ti,sysc-omap4", "ti,sysc"; 263 reg = <0x49900000 0x4>, 264 <0x49900010 0x4>; 265 reg-names = "rev", "sysc"; 266 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 267 ti,sysc-midle = <SYSC_IDLE_FORCE>; 268 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 269 <SYSC_IDLE_SMART>; 270 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>; 271 clock-names = "fck"; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 ranges = <0x0 0x49900000 0x100000>; 275 276 edma_tptc1: dma@0 { 277 compatible = "ti,edma3-tptc"; 278 reg = <0 0x100000>; 279 interrupts = <113>; 280 interrupt-names = "edma3_tcerrint"; 281 }; 282 }; 283 284 target-module@49a00000 { 285 compatible = "ti,sysc-omap4", "ti,sysc"; 286 reg = <0x49a00000 0x4>, 287 <0x49a00010 0x4>; 288 reg-names = "rev", "sysc"; 289 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 290 ti,sysc-midle = <SYSC_IDLE_FORCE>; 291 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 292 <SYSC_IDLE_SMART>; 293 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>; 294 clock-names = "fck"; 295 #address-cells = <1>; 296 #size-cells = <1>; 297 ranges = <0x0 0x49a00000 0x100000>; 298 299 edma_tptc2: dma@0 { 300 compatible = "ti,edma3-tptc"; 301 reg = <0 0x100000>; 302 interrupts = <114>; 303 interrupt-names = "edma3_tcerrint"; 304 }; 305 }; 306 307 target-module@47810000 { 308 compatible = "ti,sysc-omap2", "ti,sysc"; 309 reg = <0x478102fc 0x4>, 310 <0x47810110 0x4>, 311 <0x47810114 0x4>; 312 reg-names = "rev", "sysc", "syss"; 313 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 314 SYSC_OMAP2_ENAWAKEUP | 315 SYSC_OMAP2_SOFTRESET | 316 SYSC_OMAP2_AUTOIDLE)>; 317 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 318 <SYSC_IDLE_NO>, 319 <SYSC_IDLE_SMART>; 320 ti,syss-mask = <1>; 321 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>; 322 clock-names = "fck"; 323 #address-cells = <1>; 324 #size-cells = <1>; 325 ranges = <0x0 0x47810000 0x1000>; 326 327 mmc3: mmc@0 { 328 compatible = "ti,am335-sdhci"; 329 ti,needs-special-reset; 330 interrupts = <29>; 331 reg = <0x0 0x1000>; 332 status = "disabled"; 333 }; 334 }; 335 336 usb: target-module@47400000 { 337 compatible = "ti,sysc-omap4", "ti,sysc"; 338 reg = <0x47400000 0x4>, 339 <0x47400010 0x4>; 340 reg-names = "rev", "sysc"; 341 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 342 SYSC_OMAP4_SOFTRESET)>; 343 ti,sysc-midle = <SYSC_IDLE_FORCE>, 344 <SYSC_IDLE_NO>, 345 <SYSC_IDLE_SMART>; 346 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 347 <SYSC_IDLE_NO>, 348 <SYSC_IDLE_SMART>, 349 <SYSC_IDLE_SMART_WKUP>; 350 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>; 351 clock-names = "fck"; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges = <0x0 0x47400000 0x8000>; 355 356 usb0_phy: usb-phy@1300 { 357 compatible = "ti,am335x-usb-phy"; 358 reg = <0x1300 0x100>; 359 reg-names = "phy"; 360 ti,ctrl_mod = <&usb_ctrl_mod>; 361 #phy-cells = <0>; 362 }; 363 364 usb0: usb@1400 { 365 compatible = "ti,musb-am33xx"; 366 reg = <0x1400 0x400>, 367 <0x1000 0x200>; 368 reg-names = "mc", "control"; 369 370 interrupts = <18>; 371 interrupt-names = "mc"; 372 dr_mode = "otg"; 373 mentor,multipoint = <1>; 374 mentor,num-eps = <16>; 375 mentor,ram-bits = <12>; 376 mentor,power = <500>; 377 phys = <&usb0_phy>; 378 379 dmas = <&cppi41dma 0 0 &cppi41dma 1 0 380 &cppi41dma 2 0 &cppi41dma 3 0 381 &cppi41dma 4 0 &cppi41dma 5 0 382 &cppi41dma 6 0 &cppi41dma 7 0 383 &cppi41dma 8 0 &cppi41dma 9 0 384 &cppi41dma 10 0 &cppi41dma 11 0 385 &cppi41dma 12 0 &cppi41dma 13 0 386 &cppi41dma 14 0 &cppi41dma 0 1 387 &cppi41dma 1 1 &cppi41dma 2 1 388 &cppi41dma 3 1 &cppi41dma 4 1 389 &cppi41dma 5 1 &cppi41dma 6 1 390 &cppi41dma 7 1 &cppi41dma 8 1 391 &cppi41dma 9 1 &cppi41dma 10 1 392 &cppi41dma 11 1 &cppi41dma 12 1 393 &cppi41dma 13 1 &cppi41dma 14 1>; 394 dma-names = 395 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", 396 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", 397 "rx14", "rx15", 398 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 399 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", 400 "tx14", "tx15"; 401 }; 402 403 usb1_phy: usb-phy@1b00 { 404 compatible = "ti,am335x-usb-phy"; 405 reg = <0x1b00 0x100>; 406 reg-names = "phy"; 407 ti,ctrl_mod = <&usb_ctrl_mod>; 408 #phy-cells = <0>; 409 }; 410 411 usb1: usb@1800 { 412 compatible = "ti,musb-am33xx"; 413 reg = <0x1c00 0x400>, 414 <0x1800 0x200>; 415 reg-names = "mc", "control"; 416 interrupts = <19>; 417 interrupt-names = "mc"; 418 dr_mode = "otg"; 419 mentor,multipoint = <1>; 420 mentor,num-eps = <16>; 421 mentor,ram-bits = <12>; 422 mentor,power = <500>; 423 phys = <&usb1_phy>; 424 425 dmas = <&cppi41dma 15 0 &cppi41dma 16 0 426 &cppi41dma 17 0 &cppi41dma 18 0 427 &cppi41dma 19 0 &cppi41dma 20 0 428 &cppi41dma 21 0 &cppi41dma 22 0 429 &cppi41dma 23 0 &cppi41dma 24 0 430 &cppi41dma 25 0 &cppi41dma 26 0 431 &cppi41dma 27 0 &cppi41dma 28 0 432 &cppi41dma 29 0 &cppi41dma 15 1 433 &cppi41dma 16 1 &cppi41dma 17 1 434 &cppi41dma 18 1 &cppi41dma 19 1 435 &cppi41dma 20 1 &cppi41dma 21 1 436 &cppi41dma 22 1 &cppi41dma 23 1 437 &cppi41dma 24 1 &cppi41dma 25 1 438 &cppi41dma 26 1 &cppi41dma 27 1 439 &cppi41dma 28 1 &cppi41dma 29 1>; 440 dma-names = 441 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", 442 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", 443 "rx14", "rx15", 444 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 445 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", 446 "tx14", "tx15"; 447 }; 448 449 cppi41dma: dma-controller@2000 { 450 compatible = "ti,am3359-cppi41"; 451 reg = <0x0000 0x1000>, 452 <0x2000 0x1000>, 453 <0x3000 0x1000>, 454 <0x4000 0x4000>; 455 reg-names = "glue", "controller", "scheduler", "queuemgr"; 456 interrupts = <17>; 457 interrupt-names = "glue"; 458 #dma-cells = <2>; 459 #dma-channels = <30>; 460 #dma-requests = <256>; 461 }; 462 }; 463 464 ocmcram: sram@40300000 { 465 compatible = "mmio-sram"; 466 reg = <0x40300000 0x10000>; /* 64k */ 467 ranges = <0x0 0x40300000 0x10000>; 468 #address-cells = <1>; 469 #size-cells = <1>; 470 471 pm_sram_code: pm-code-sram@0 { 472 compatible = "ti,sram"; 473 reg = <0x0 0x1000>; 474 protect-exec; 475 }; 476 477 pm_sram_data: pm-data-sram@1000 { 478 compatible = "ti,sram"; 479 reg = <0x1000 0x1000>; 480 pool; 481 }; 482 }; 483 484 emif: emif@4c000000 { 485 compatible = "ti,emif-am3352"; 486 reg = <0x4c000000 0x1000000>; 487 ti,hwmods = "emif"; 488 interrupts = <101>; 489 sram = <&pm_sram_code 490 &pm_sram_data>; 491 ti,no-idle; 492 }; 493 494 gpmc: gpmc@50000000 { 495 compatible = "ti,am3352-gpmc"; 496 ti,hwmods = "gpmc"; 497 ti,no-idle-on-init; 498 reg = <0x50000000 0x2000>; 499 interrupts = <100>; 500 dmas = <&edma 52 0>; 501 dma-names = "rxtx"; 502 gpmc,num-cs = <7>; 503 gpmc,num-waitpins = <2>; 504 #address-cells = <2>; 505 #size-cells = <1>; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 gpio-controller; 509 #gpio-cells = <2>; 510 status = "disabled"; 511 }; 512 513 sham_target: target-module@53100000 { 514 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 515 reg = <0x53100100 0x4>, 516 <0x53100110 0x4>, 517 <0x53100114 0x4>; 518 reg-names = "rev", "sysc", "syss"; 519 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 520 SYSC_OMAP2_AUTOIDLE)>; 521 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 522 <SYSC_IDLE_NO>, 523 <SYSC_IDLE_SMART>; 524 ti,syss-mask = <1>; 525 /* Domains (P, C): per_pwrdm, l3_clkdm */ 526 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>; 527 clock-names = "fck"; 528 #address-cells = <1>; 529 #size-cells = <1>; 530 ranges = <0x0 0x53100000 0x1000>; 531 532 sham: sham@0 { 533 compatible = "ti,omap4-sham"; 534 reg = <0 0x200>; 535 interrupts = <109>; 536 dmas = <&edma 36 0>; 537 dma-names = "rx"; 538 }; 539 }; 540 541 aes_target: target-module@53500000 { 542 compatible = "ti,sysc-omap2", "ti,sysc"; 543 reg = <0x53500080 0x4>, 544 <0x53500084 0x4>, 545 <0x53500088 0x4>; 546 reg-names = "rev", "sysc", "syss"; 547 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 548 SYSC_OMAP2_AUTOIDLE)>; 549 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 550 <SYSC_IDLE_NO>, 551 <SYSC_IDLE_SMART>, 552 <SYSC_IDLE_SMART_WKUP>; 553 ti,syss-mask = <1>; 554 /* Domains (P, C): per_pwrdm, l3_clkdm */ 555 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>; 556 clock-names = "fck"; 557 #address-cells = <1>; 558 #size-cells = <1>; 559 ranges = <0x0 0x53500000 0x1000>; 560 561 aes: aes@0 { 562 compatible = "ti,omap4-aes"; 563 reg = <0 0xa0>; 564 interrupts = <103>; 565 dmas = <&edma 6 0>, 566 <&edma 5 0>; 567 dma-names = "tx", "rx"; 568 }; 569 }; 570 571 target-module@56000000 { 572 compatible = "ti,sysc-omap4", "ti,sysc"; 573 reg = <0x5600fe00 0x4>, 574 <0x5600fe10 0x4>; 575 reg-names = "rev", "sysc"; 576 ti,sysc-midle = <SYSC_IDLE_FORCE>, 577 <SYSC_IDLE_NO>, 578 <SYSC_IDLE_SMART>; 579 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 580 <SYSC_IDLE_NO>, 581 <SYSC_IDLE_SMART>; 582 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>; 583 clock-names = "fck"; 584 power-domains = <&prm_gfx>; 585 resets = <&prm_gfx 0>; 586 reset-names = "rstctrl"; 587 #address-cells = <1>; 588 #size-cells = <1>; 589 ranges = <0 0x56000000 0x1000000>; 590 591 /* 592 * Closed source PowerVR driver, no child device 593 * binding or driver in mainline 594 */ 595 }; 596 }; 597}; 598 599#include "am33xx-l4.dtsi" 600#include "am33xx-clocks.dtsi" 601 602&prcm { 603 prm_per: prm@c00 { 604 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 605 reg = <0xc00 0x100>; 606 #reset-cells = <1>; 607 }; 608 609 prm_wkup: prm@d00 { 610 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 611 reg = <0xd00 0x100>; 612 #reset-cells = <1>; 613 }; 614 615 prm_device: prm@f00 { 616 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 617 reg = <0xf00 0x100>; 618 #reset-cells = <1>; 619 }; 620 621 prm_gfx: prm@1100 { 622 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 623 reg = <0x1100 0x100>; 624 #power-domain-cells = <0>; 625 #reset-cells = <1>; 626 }; 627}; 628 629/* Preferred always-on timer for clocksource */ 630&timer1_target { 631 ti,no-reset-on-init; 632 ti,no-idle; 633 timer@0 { 634 assigned-clocks = <&timer1_fck>; 635 assigned-clock-parents = <&sys_clkin_ck>; 636 }; 637}; 638 639/* Preferred timer for clockevent */ 640&timer2_target { 641 ti,no-reset-on-init; 642 ti,no-idle; 643 timer@0 { 644 assigned-clocks = <&timer2_fck>; 645 assigned-clock-parents = <&sys_clkin_ck>; 646 }; 647}; 648