1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2013 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 led0 = &led0; 14 led1 = &led1; 15 led2 = &led2; 16 nand = &gpmi; 17 ssi0 = &ssi1; 18 usb0 = &usbh1; 19 usb1 = &usbotg; 20 }; 21 22 chosen { 23 bootargs = "console=ttymxc1,115200"; 24 }; 25 26 backlight { 27 compatible = "pwm-backlight"; 28 pwms = <&pwm4 0 5000000>; 29 brightness-levels = <0 4 8 16 32 64 128 255>; 30 default-brightness-level = <7>; 31 }; 32 33 gpio-keys { 34 compatible = "gpio-keys"; 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 user-pb { 39 label = "user_pb"; 40 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 41 linux,code = <BTN_0>; 42 }; 43 44 user-pb1x { 45 label = "user_pb1x"; 46 linux,code = <BTN_1>; 47 interrupt-parent = <&gsc>; 48 interrupts = <0>; 49 }; 50 51 key-erased { 52 label = "key-erased"; 53 linux,code = <BTN_2>; 54 interrupt-parent = <&gsc>; 55 interrupts = <1>; 56 }; 57 58 eeprom-wp { 59 label = "eeprom_wp"; 60 linux,code = <BTN_3>; 61 interrupt-parent = <&gsc>; 62 interrupts = <2>; 63 }; 64 65 tamper { 66 label = "tamper"; 67 linux,code = <BTN_4>; 68 interrupt-parent = <&gsc>; 69 interrupts = <5>; 70 }; 71 72 switch-hold { 73 label = "switch_hold"; 74 linux,code = <BTN_5>; 75 interrupt-parent = <&gsc>; 76 interrupts = <7>; 77 }; 78 }; 79 80 leds { 81 compatible = "gpio-leds"; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_gpio_leds>; 84 85 led0: user1 { 86 label = "user1"; 87 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 88 default-state = "on"; 89 linux,default-trigger = "heartbeat"; 90 }; 91 92 led1: user2 { 93 label = "user2"; 94 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 95 default-state = "off"; 96 }; 97 98 led2: user3 { 99 label = "user3"; 100 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 101 default-state = "off"; 102 }; 103 }; 104 105 memory@10000000 { 106 device_type = "memory"; 107 reg = <0x10000000 0x20000000>; 108 }; 109 110 pps { 111 compatible = "pps-gpio"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_pps>; 114 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 115 status = "okay"; 116 }; 117 118 reg_1p0v: regulator-1p0v { 119 compatible = "regulator-fixed"; 120 regulator-name = "1P0V"; 121 regulator-min-microvolt = <1000000>; 122 regulator-max-microvolt = <1000000>; 123 regulator-always-on; 124 }; 125 126 reg_3p3v: regulator-3p3v { 127 compatible = "regulator-fixed"; 128 regulator-name = "3P3V"; 129 regulator-min-microvolt = <3300000>; 130 regulator-max-microvolt = <3300000>; 131 regulator-always-on; 132 }; 133 134 reg_5p0v: regulator-5p0v { 135 compatible = "regulator-fixed"; 136 regulator-name = "5P0V"; 137 regulator-min-microvolt = <5000000>; 138 regulator-max-microvolt = <5000000>; 139 regulator-always-on; 140 }; 141 142 reg_usb_otg_vbus: regulator-usb-otg-vbus { 143 compatible = "regulator-fixed"; 144 regulator-name = "usb_otg_vbus"; 145 regulator-min-microvolt = <5000000>; 146 regulator-max-microvolt = <5000000>; 147 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 148 enable-active-high; 149 }; 150 151 sound { 152 compatible = "fsl,imx6q-ventana-sgtl5000", 153 "fsl,imx-audio-sgtl5000"; 154 model = "sgtl5000-audio"; 155 ssi-controller = <&ssi1>; 156 audio-codec = <&codec>; 157 audio-routing = 158 "MIC_IN", "Mic Jack", 159 "Mic Jack", "Mic Bias", 160 "Headphone Jack", "HP_OUT"; 161 mux-int-port = <1>; 162 mux-ext-port = <4>; 163 }; 164}; 165 166&audmux { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_audmux>; 169 status = "okay"; 170}; 171 172&can1 { 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_flexcan1>; 175 status = "okay"; 176}; 177 178&clks { 179 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 180 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 181 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 182 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 183}; 184 185&ecspi3 { 186 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_ecspi3>; 189 status = "okay"; 190}; 191 192&fec { 193 pinctrl-names = "default"; 194 pinctrl-0 = <&pinctrl_enet>; 195 phy-mode = "rgmii-id"; 196 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 197 status = "okay"; 198}; 199 200&gpmi { 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_gpmi_nand>; 203 status = "okay"; 204}; 205 206&hdmi { 207 ddc-i2c-bus = <&i2c3>; 208 status = "okay"; 209}; 210 211&i2c1 { 212 clock-frequency = <100000>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_i2c1>; 215 status = "okay"; 216 217 gsc: gsc@20 { 218 compatible = "gw,gsc"; 219 reg = <0x20>; 220 interrupt-parent = <&gpio1>; 221 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 222 interrupt-controller; 223 #interrupt-cells = <1>; 224 #size-cells = <0>; 225 226 adc { 227 compatible = "gw,gsc-adc"; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 231 channel@0 { 232 gw,mode = <0>; 233 reg = <0x00>; 234 label = "temp"; 235 }; 236 237 channel@2 { 238 gw,mode = <1>; 239 reg = <0x02>; 240 label = "vdd_vin"; 241 }; 242 243 channel@5 { 244 gw,mode = <1>; 245 reg = <0x05>; 246 label = "vdd_3p3"; 247 }; 248 249 channel@8 { 250 gw,mode = <1>; 251 reg = <0x08>; 252 label = "vdd_bat"; 253 }; 254 255 channel@b { 256 gw,mode = <1>; 257 reg = <0x0b>; 258 label = "vdd_5p0"; 259 }; 260 261 channel@e { 262 gw,mode = <1>; 263 reg = <0xe>; 264 label = "vdd_arm"; 265 }; 266 267 channel@11 { 268 gw,mode = <1>; 269 reg = <0x11>; 270 label = "vdd_soc"; 271 }; 272 273 channel@14 { 274 gw,mode = <1>; 275 reg = <0x14>; 276 label = "vdd_3p0"; 277 }; 278 279 channel@17 { 280 gw,mode = <1>; 281 reg = <0x17>; 282 label = "vdd_1p5"; 283 }; 284 285 channel@1d { 286 gw,mode = <1>; 287 reg = <0x1d>; 288 label = "vdd_1p8"; 289 }; 290 291 channel@20 { 292 gw,mode = <1>; 293 reg = <0x20>; 294 label = "vdd_1p0"; 295 }; 296 297 channel@23 { 298 gw,mode = <1>; 299 reg = <0x23>; 300 label = "vdd_2p5"; 301 }; 302 303 channel@29 { 304 gw,mode = <1>; 305 reg = <0x29>; 306 label = "vdd_an1"; 307 }; 308 }; 309 }; 310 311 gsc_gpio: gpio@23 { 312 compatible = "nxp,pca9555"; 313 reg = <0x23>; 314 gpio-controller; 315 #gpio-cells = <2>; 316 interrupt-parent = <&gsc>; 317 interrupts = <4>; 318 }; 319 320 eeprom1: eeprom@50 { 321 compatible = "atmel,24c02"; 322 reg = <0x50>; 323 pagesize = <16>; 324 }; 325 326 eeprom2: eeprom@51 { 327 compatible = "atmel,24c02"; 328 reg = <0x51>; 329 pagesize = <16>; 330 }; 331 332 eeprom3: eeprom@52 { 333 compatible = "atmel,24c02"; 334 reg = <0x52>; 335 pagesize = <16>; 336 }; 337 338 eeprom4: eeprom@53 { 339 compatible = "atmel,24c02"; 340 reg = <0x53>; 341 pagesize = <16>; 342 }; 343 344 rtc: ds1672@68 { 345 compatible = "dallas,ds1672"; 346 reg = <0x68>; 347 }; 348}; 349 350&i2c2 { 351 clock-frequency = <100000>; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pinctrl_i2c2>; 354 status = "okay"; 355 356 ltc3676: pmic@3c { 357 compatible = "lltc,ltc3676"; 358 reg = <0x3c>; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&pinctrl_pmic>; 361 interrupt-parent = <&gpio1>; 362 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 363 364 regulators { 365 /* VDD_SOC (1+R1/R2 = 1.635) */ 366 reg_vdd_soc: sw1 { 367 regulator-name = "vddsoc"; 368 regulator-min-microvolt = <674400>; 369 regulator-max-microvolt = <1308000>; 370 lltc,fb-voltage-divider = <127000 200000>; 371 regulator-ramp-delay = <7000>; 372 regulator-boot-on; 373 regulator-always-on; 374 }; 375 376 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ 377 reg_1p8v: sw2 { 378 regulator-name = "vdd1p8"; 379 regulator-min-microvolt = <1033310>; 380 regulator-max-microvolt = <2004000>; 381 lltc,fb-voltage-divider = <301000 200000>; 382 regulator-ramp-delay = <7000>; 383 regulator-boot-on; 384 regulator-always-on; 385 }; 386 387 /* VDD_ARM (1+R1/R2 = 1.635) */ 388 reg_vdd_arm: sw3 { 389 regulator-name = "vddarm"; 390 regulator-min-microvolt = <674400>; 391 regulator-max-microvolt = <1308000>; 392 lltc,fb-voltage-divider = <127000 200000>; 393 regulator-ramp-delay = <7000>; 394 regulator-boot-on; 395 regulator-always-on; 396 }; 397 398 /* VDD_DDR (1+R1/R2 = 2.105) */ 399 reg_vdd_ddr: sw4 { 400 regulator-name = "vddddr"; 401 regulator-min-microvolt = <868310>; 402 regulator-max-microvolt = <1684000>; 403 lltc,fb-voltage-divider = <221000 200000>; 404 regulator-ramp-delay = <7000>; 405 regulator-boot-on; 406 regulator-always-on; 407 }; 408 409 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 410 reg_2p5v: ldo2 { 411 regulator-name = "vdd2p5"; 412 regulator-min-microvolt = <2490375>; 413 regulator-max-microvolt = <2490375>; 414 lltc,fb-voltage-divider = <487000 200000>; 415 regulator-boot-on; 416 regulator-always-on; 417 }; 418 419 /* VDD_AUD_1P8: Audio codec */ 420 reg_aud_1p8v: ldo3 { 421 regulator-name = "vdd1p8a"; 422 regulator-min-microvolt = <1800000>; 423 regulator-max-microvolt = <1800000>; 424 regulator-boot-on; 425 }; 426 427 /* VDD_HIGH (1+R1/R2 = 4.17) */ 428 reg_3p0v: ldo4 { 429 regulator-name = "vdd3p0"; 430 regulator-min-microvolt = <3023250>; 431 regulator-max-microvolt = <3023250>; 432 lltc,fb-voltage-divider = <634000 200000>; 433 regulator-boot-on; 434 regulator-always-on; 435 }; 436 }; 437 }; 438}; 439 440&i2c3 { 441 clock-frequency = <100000>; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&pinctrl_i2c3>; 444 status = "okay"; 445 446 codec: sgtl5000@a { 447 compatible = "fsl,sgtl5000"; 448 reg = <0x0a>; 449 clocks = <&clks IMX6QDL_CLK_CKO>; 450 VDDA-supply = <®_1p8v>; 451 VDDIO-supply = <®_3p3v>; 452 }; 453 454 touchscreen: egalax_ts@4 { 455 compatible = "eeti,egalax_ts"; 456 reg = <0x04>; 457 interrupt-parent = <&gpio7>; 458 interrupts = <12 2>; 459 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; 460 }; 461 462 accel@1e { 463 compatible = "nxp,fxos8700"; 464 reg = <0x1e>; 465 }; 466}; 467 468&ldb { 469 status = "okay"; 470 471 lvds-channel@0 { 472 fsl,data-mapping = "spwg"; 473 fsl,data-width = <18>; 474 status = "okay"; 475 476 display-timings { 477 native-mode = <&timing0>; 478 timing0: hsd100pxn1 { 479 clock-frequency = <65000000>; 480 hactive = <1024>; 481 vactive = <768>; 482 hback-porch = <220>; 483 hfront-porch = <40>; 484 vback-porch = <21>; 485 vfront-porch = <7>; 486 hsync-len = <60>; 487 vsync-len = <10>; 488 }; 489 }; 490 }; 491}; 492 493&pcie { 494 pinctrl-names = "default"; 495 pinctrl-0 = <&pinctrl_pcie>; 496 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; 497 status = "okay"; 498}; 499 500&pwm2 { 501 pinctrl-names = "default"; 502 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 503 status = "disabled"; 504}; 505 506&pwm3 { 507 pinctrl-names = "default"; 508 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 509 status = "disabled"; 510}; 511 512&pwm4 { 513 #pwm-cells = <2>; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&pinctrl_pwm4>; 516 status = "okay"; 517}; 518 519&ssi1 { 520 status = "okay"; 521}; 522 523&uart1 { 524 pinctrl-names = "default"; 525 pinctrl-0 = <&pinctrl_uart1>; 526 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 527 status = "okay"; 528}; 529 530&uart2 { 531 pinctrl-names = "default"; 532 pinctrl-0 = <&pinctrl_uart2>; 533 status = "okay"; 534}; 535 536&uart5 { 537 pinctrl-names = "default"; 538 pinctrl-0 = <&pinctrl_uart5>; 539 status = "okay"; 540}; 541 542&usbotg { 543 vbus-supply = <®_usb_otg_vbus>; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&pinctrl_usbotg>; 546 disable-over-current; 547 status = "okay"; 548}; 549 550&usbh1 { 551 status = "okay"; 552}; 553 554&usdhc3 { 555 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 556 pinctrl-0 = <&pinctrl_usdhc3>; 557 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 558 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 559 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 560 vmmc-supply = <®_3p3v>; 561 no-1-8-v; /* firmware will remove if board revision supports */ 562 status = "okay"; 563}; 564 565&wdog1 { 566 pinctrl-names = "default"; 567 pinctrl-0 = <&pinctrl_wdog>; 568 fsl,ext-reset-output; 569}; 570 571&iomuxc { 572 pinctrl_audmux: audmuxgrp { 573 fsl,pins = < 574 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 575 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 576 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 577 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 578 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 579 >; 580 }; 581 582 pinctrl_ecspi3: escpi3grp { 583 fsl,pins = < 584 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 585 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 586 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 587 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 588 >; 589 }; 590 591 pinctrl_enet: enetgrp { 592 fsl,pins = < 593 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 594 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 595 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 596 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 597 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 598 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 599 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 600 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 601 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 602 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 603 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 604 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 605 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 606 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 607 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 608 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 609 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ 610 >; 611 }; 612 613 pinctrl_flexcan1: flexcan1grp { 614 fsl,pins = < 615 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 616 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 617 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ 618 >; 619 }; 620 621 pinctrl_gpio_leds: gpioledsgrp { 622 fsl,pins = < 623 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 624 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 625 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 626 >; 627 }; 628 629 pinctrl_gpmi_nand: gpminandgrp { 630 fsl,pins = < 631 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 632 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 633 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 634 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 635 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 636 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 637 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 638 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 639 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 640 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 641 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 642 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 643 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 644 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 645 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 646 >; 647 }; 648 649 pinctrl_i2c1: i2c1grp { 650 fsl,pins = < 651 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 652 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 653 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 654 >; 655 }; 656 657 pinctrl_i2c2: i2c2grp { 658 fsl,pins = < 659 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 660 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 661 >; 662 }; 663 664 pinctrl_i2c3: i2c3grp { 665 fsl,pins = < 666 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 667 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 668 >; 669 }; 670 671 pinctrl_pcie: pciegrp { 672 fsl,pins = < 673 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ 674 >; 675 }; 676 677 pinctrl_pmic: pmicgrp { 678 fsl,pins = < 679 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 680 >; 681 }; 682 683 pinctrl_pps: ppsgrp { 684 fsl,pins = < 685 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 686 >; 687 }; 688 689 pinctrl_pwm2: pwm2grp { 690 fsl,pins = < 691 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 692 >; 693 }; 694 695 pinctrl_pwm3: pwm3grp { 696 fsl,pins = < 697 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 698 >; 699 }; 700 701 pinctrl_pwm4: pwm4grp { 702 fsl,pins = < 703 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 704 >; 705 }; 706 707 pinctrl_uart1: uart1grp { 708 fsl,pins = < 709 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 710 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 711 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 712 >; 713 }; 714 715 pinctrl_uart2: uart2grp { 716 fsl,pins = < 717 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 718 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 719 >; 720 }; 721 722 pinctrl_uart5: uart5grp { 723 fsl,pins = < 724 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 725 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 726 >; 727 }; 728 729 pinctrl_usbotg: usbotggrp { 730 fsl,pins = < 731 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 732 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 733 >; 734 }; 735 736 pinctrl_usdhc3: usdhc3grp { 737 fsl,pins = < 738 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 739 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 740 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 741 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 742 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 743 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 744 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 745 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 746 >; 747 }; 748 749 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 750 fsl,pins = < 751 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 752 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 753 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 754 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 755 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 756 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 757 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 758 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 759 >; 760 }; 761 762 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 763 fsl,pins = < 764 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 765 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 766 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 767 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 768 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 769 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 770 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 771 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 772 >; 773 }; 774 775 pinctrl_wdog: wdoggrp { 776 fsl,pins = < 777 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 778 >; 779 }; 780}; 781