1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2011 Picochip, Jamie Iles 4 */ 5/ { 6 model = "Picochip picoXcell PC3X2"; 7 compatible = "picochip,pc3x2"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 11 cpus { 12 #address-cells = <0>; 13 #size-cells = <0>; 14 15 cpu { 16 compatible = "arm,arm1176jz-s"; 17 device_type = "cpu"; 18 clock-frequency = <400000000>; 19 d-cache-line-size = <32>; 20 d-cache-size = <32768>; 21 i-cache-line-size = <32>; 22 i-cache-size = <32768>; 23 }; 24 }; 25 26 clocks { 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges; 30 31 pclk: clock@0 { 32 compatible = "fixed-clock"; 33 clock-outputs = "bus", "pclk"; 34 clock-frequency = <200000000>; 35 ref-clock = <&ref_clk>, "ref"; 36 }; 37 }; 38 39 paxi { 40 compatible = "simple-bus"; 41 #address-cells = <1>; 42 #size-cells = <1>; 43 ranges = <0 0x80000000 0x400000>; 44 45 emac: gem@30000 { 46 compatible = "cadence,gem"; 47 reg = <0x30000 0x10000>; 48 interrupt-parent = <&vic0>; 49 interrupts = <31>; 50 }; 51 52 dmac1: dmac@40000 { 53 compatible = "snps,dw-dmac"; 54 reg = <0x40000 0x10000>; 55 interrupt-parent = <&vic0>; 56 interrupts = <25>; 57 }; 58 59 dmac2: dmac@50000 { 60 compatible = "snps,dw-dmac"; 61 reg = <0x50000 0x10000>; 62 interrupt-parent = <&vic0>; 63 interrupts = <26>; 64 }; 65 66 vic0: interrupt-controller@60000 { 67 compatible = "arm,pl192-vic"; 68 interrupt-controller; 69 reg = <0x60000 0x1000>; 70 #interrupt-cells = <1>; 71 }; 72 73 vic1: interrupt-controller@64000 { 74 compatible = "arm,pl192-vic"; 75 interrupt-controller; 76 reg = <0x64000 0x1000>; 77 #interrupt-cells = <1>; 78 }; 79 80 fuse: picoxcell-fuse@80000 { 81 compatible = "picoxcell,fuse-pc3x2"; 82 reg = <0x80000 0x10000>; 83 }; 84 85 ssi: picoxcell-spi@90000 { 86 compatible = "picoxcell,spi"; 87 reg = <0x90000 0x10000>; 88 interrupt-parent = <&vic0>; 89 interrupts = <10>; 90 }; 91 92 ipsec: spacc@100000 { 93 compatible = "picochip,spacc-ipsec"; 94 reg = <0x100000 0x10000>; 95 interrupt-parent = <&vic0>; 96 interrupts = <24>; 97 ref-clock = <&pclk>, "ref"; 98 }; 99 100 srtp: spacc@140000 { 101 compatible = "picochip,spacc-srtp"; 102 reg = <0x140000 0x10000>; 103 interrupt-parent = <&vic0>; 104 interrupts = <23>; 105 }; 106 107 l2_engine: spacc@180000 { 108 compatible = "picochip,spacc-l2"; 109 reg = <0x180000 0x10000>; 110 interrupt-parent = <&vic0>; 111 interrupts = <22>; 112 ref-clock = <&pclk>, "ref"; 113 }; 114 115 apb { 116 compatible = "simple-bus"; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges = <0 0x200000 0x80000>; 120 121 rtc0: rtc@0 { 122 compatible = "picochip,pc3x2-rtc"; 123 clock-freq = <200000000>; 124 reg = <0x00000 0xf>; 125 interrupt-parent = <&vic1>; 126 interrupts = <8>; 127 }; 128 129 timer0: timer@10000 { 130 compatible = "picochip,pc3x2-timer"; 131 interrupt-parent = <&vic0>; 132 interrupts = <4>; 133 clock-freq = <200000000>; 134 reg = <0x10000 0x14>; 135 }; 136 137 timer1: timer@10014 { 138 compatible = "picochip,pc3x2-timer"; 139 interrupt-parent = <&vic0>; 140 interrupts = <5>; 141 clock-freq = <200000000>; 142 reg = <0x10014 0x14>; 143 }; 144 145 timer2: timer@10028 { 146 compatible = "picochip,pc3x2-timer"; 147 interrupt-parent = <&vic0>; 148 interrupts = <6>; 149 clock-freq = <200000000>; 150 reg = <0x10028 0x14>; 151 }; 152 153 timer3: timer@1003c { 154 compatible = "picochip,pc3x2-timer"; 155 interrupt-parent = <&vic0>; 156 interrupts = <7>; 157 clock-freq = <200000000>; 158 reg = <0x1003c 0x14>; 159 }; 160 161 gpio: gpio@20000 { 162 compatible = "snps,dw-apb-gpio"; 163 reg = <0x20000 0x1000>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 167 banka: gpio-controller@0 { 168 compatible = "snps,dw-apb-gpio-bank"; 169 gpio-controller; 170 #gpio-cells = <2>; 171 gpio-generic,nr-gpio = <8>; 172 173 regoffset-dat = <0x50>; 174 regoffset-set = <0x00>; 175 regoffset-dirout = <0x04>; 176 }; 177 178 bankb: gpio-controller@1 { 179 compatible = "snps,dw-apb-gpio-bank"; 180 gpio-controller; 181 #gpio-cells = <2>; 182 gpio-generic,nr-gpio = <8>; 183 184 regoffset-dat = <0x54>; 185 regoffset-set = <0x0c>; 186 regoffset-dirout = <0x10>; 187 }; 188 }; 189 190 uart0: uart@30000 { 191 compatible = "snps,dw-apb-uart"; 192 reg = <0x30000 0x1000>; 193 interrupt-parent = <&vic1>; 194 interrupts = <10>; 195 clock-frequency = <3686400>; 196 reg-shift = <2>; 197 reg-io-width = <4>; 198 }; 199 200 uart1: uart@40000 { 201 compatible = "snps,dw-apb-uart"; 202 reg = <0x40000 0x1000>; 203 interrupt-parent = <&vic1>; 204 interrupts = <9>; 205 clock-frequency = <3686400>; 206 reg-shift = <2>; 207 reg-io-width = <4>; 208 }; 209 210 wdog: watchdog@50000 { 211 compatible = "snps,dw-apb-wdg"; 212 reg = <0x50000 0x10000>; 213 interrupt-parent = <&vic0>; 214 interrupts = <11>; 215 bus-clock = <&pclk>, "bus"; 216 }; 217 }; 218 }; 219 220 rwid-axi { 221 #address-cells = <1>; 222 #size-cells = <1>; 223 compatible = "simple-bus"; 224 ranges; 225 226 ebi@50000000 { 227 compatible = "simple-bus"; 228 #address-cells = <2>; 229 #size-cells = <1>; 230 ranges = <0 0 0x40000000 0x08000000 231 1 0 0x48000000 0x08000000 232 2 0 0x50000000 0x08000000 233 3 0 0x58000000 0x08000000>; 234 }; 235 236 axi2pico@c0000000 { 237 compatible = "picochip,axi2pico-pc3x2"; 238 reg = <0xc0000000 0x10000>; 239 interrupt-parent = <&vic0>; 240 interrupts = <13 14 15 16 17 18 19 20 21>; 241 }; 242 }; 243}; 244