1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2014 STMicroelectronics R&D Limited 4 */ 5#include <dt-bindings/clock/stih410-clks.h> 6/ { 7 /* 8 * Fixed 30MHz oscillator inputs to SoC 9 */ 10 clk_sysin: clk-sysin { 11 #clock-cells = <0>; 12 compatible = "fixed-clock"; 13 clock-frequency = <30000000>; 14 clock-output-names = "CLK_SYSIN"; 15 }; 16 17 clk_tmdsout_hdmi: clk-tmdsout-hdmi { 18 #clock-cells = <0>; 19 compatible = "fixed-clock"; 20 clock-frequency = <0>; 21 }; 22 23 clocks { 24 #address-cells = <1>; 25 #size-cells = <1>; 26 ranges; 27 28 compatible = "st,stih410-clk", "simple-bus"; 29 30 /* 31 * A9 PLL. 32 */ 33 clockgen-a9@92b0000 { 34 compatible = "st,clkgen-c32"; 35 reg = <0x92b0000 0xffff>; 36 37 clockgen_a9_pll: clockgen-a9-pll { 38 #clock-cells = <1>; 39 compatible = "st,stih407-clkgen-plla9"; 40 41 clocks = <&clk_sysin>; 42 43 clock-output-names = "clockgen-a9-pll-odf"; 44 }; 45 }; 46 47 /* 48 * ARM CPU related clocks. 49 */ 50 clk_m_a9: clk-m-a9@92b0000 { 51 #clock-cells = <0>; 52 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; 53 reg = <0x92b0000 0x10000>; 54 55 clocks = <&clockgen_a9_pll 0>, 56 <&clockgen_a9_pll 0>, 57 <&clk_s_c0_flexgen 13>, 58 <&clk_m_a9_ext2f_div2>; 59 /* 60 * ARM Peripheral clock for timers 61 */ 62 arm_periph_clk: clk-m-a9-periphs { 63 #clock-cells = <0>; 64 compatible = "fixed-factor-clock"; 65 clocks = <&clk_m_a9>; 66 clock-div = <2>; 67 clock-mult = <1>; 68 }; 69 }; 70 71 clockgen-a@90ff000 { 72 compatible = "st,clkgen-c32"; 73 reg = <0x90ff000 0x1000>; 74 75 clk_s_a0_pll: clk-s-a0-pll { 76 #clock-cells = <1>; 77 compatible = "st,clkgen-pll0"; 78 79 clocks = <&clk_sysin>; 80 81 clock-output-names = "clk-s-a0-pll-ofd-0"; 82 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ 83 }; 84 85 clk_s_a0_flexgen: clk-s-a0-flexgen { 86 compatible = "st,flexgen"; 87 88 #clock-cells = <1>; 89 90 clocks = <&clk_s_a0_pll 0>, 91 <&clk_sysin>; 92 93 clock-output-names = "clk-ic-lmi0", 94 "clk-ic-lmi1"; 95 clock-critical = <CLK_IC_LMI0>; 96 }; 97 }; 98 99 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { 100 #clock-cells = <1>; 101 compatible = "st,quadfs-pll"; 102 reg = <0x9103000 0x1000>; 103 104 clocks = <&clk_sysin>; 105 106 clock-output-names = "clk-s-c0-fs0-ch0", 107 "clk-s-c0-fs0-ch1", 108 "clk-s-c0-fs0-ch2", 109 "clk-s-c0-fs0-ch3"; 110 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ 111 }; 112 113 clk_s_c0: clockgen-c@9103000 { 114 compatible = "st,clkgen-c32"; 115 reg = <0x9103000 0x1000>; 116 117 clk_s_c0_pll0: clk-s-c0-pll0 { 118 #clock-cells = <1>; 119 compatible = "st,clkgen-pll0"; 120 121 clocks = <&clk_sysin>; 122 123 clock-output-names = "clk-s-c0-pll0-odf-0"; 124 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ 125 }; 126 127 clk_s_c0_pll1: clk-s-c0-pll1 { 128 #clock-cells = <1>; 129 compatible = "st,clkgen-pll1"; 130 131 clocks = <&clk_sysin>; 132 133 clock-output-names = "clk-s-c0-pll1-odf-0"; 134 }; 135 136 clk_s_c0_flexgen: clk-s-c0-flexgen { 137 #clock-cells = <1>; 138 compatible = "st,flexgen"; 139 140 clocks = <&clk_s_c0_pll0 0>, 141 <&clk_s_c0_pll1 0>, 142 <&clk_s_c0_quadfs 0>, 143 <&clk_s_c0_quadfs 1>, 144 <&clk_s_c0_quadfs 2>, 145 <&clk_s_c0_quadfs 3>, 146 <&clk_sysin>; 147 148 clock-output-names = "clk-icn-gpu", 149 "clk-fdma", 150 "clk-nand", 151 "clk-hva", 152 "clk-proc-stfe", 153 "clk-proc-tp", 154 "clk-rx-icn-dmu", 155 "clk-rx-icn-hva", 156 "clk-icn-cpu", 157 "clk-tx-icn-dmu", 158 "clk-mmc-0", 159 "clk-mmc-1", 160 "clk-jpegdec", 161 "clk-ext2fa9", 162 "clk-ic-bdisp-0", 163 "clk-ic-bdisp-1", 164 "clk-pp-dmu", 165 "clk-vid-dmu", 166 "clk-dss-lpc", 167 "clk-st231-aud-0", 168 "clk-st231-gp-1", 169 "clk-st231-dmu", 170 "clk-icn-lmi", 171 "clk-tx-icn-disp-1", 172 "clk-icn-sbc", 173 "clk-stfe-frc2", 174 "clk-eth-phy", 175 "clk-eth-ref-phyclk", 176 "clk-flash-promip", 177 "clk-main-disp", 178 "clk-aux-disp", 179 "clk-compo-dvp", 180 "clk-tx-icn-hades", 181 "clk-rx-icn-hades", 182 "clk-icn-reg-16", 183 "clk-pp-hades", 184 "clk-clust-hades", 185 "clk-hwpe-hades", 186 "clk-fc-hades"; 187 clock-critical = <CLK_PROC_STFE>, 188 <CLK_ICN_CPU>, 189 <CLK_TX_ICN_DMU>, 190 <CLK_EXT2F_A9>, 191 <CLK_ICN_LMI>, 192 <CLK_ICN_SBC>; 193 194 /* 195 * ARM Peripheral clock for timers 196 */ 197 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { 198 #clock-cells = <0>; 199 compatible = "fixed-factor-clock"; 200 201 clocks = <&clk_s_c0_flexgen 13>; 202 203 clock-output-names = "clk-m-a9-ext2f-div2"; 204 205 clock-div = <2>; 206 clock-mult = <1>; 207 }; 208 }; 209 }; 210 211 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { 212 #clock-cells = <1>; 213 compatible = "st,quadfs"; 214 reg = <0x9104000 0x1000>; 215 216 clocks = <&clk_sysin>; 217 218 clock-output-names = "clk-s-d0-fs0-ch0", 219 "clk-s-d0-fs0-ch1", 220 "clk-s-d0-fs0-ch2", 221 "clk-s-d0-fs0-ch3"; 222 }; 223 224 clockgen-d0@9104000 { 225 compatible = "st,clkgen-c32"; 226 reg = <0x9104000 0x1000>; 227 228 clk_s_d0_flexgen: clk-s-d0-flexgen { 229 #clock-cells = <1>; 230 compatible = "st,flexgen-audio", "st,flexgen"; 231 232 clocks = <&clk_s_d0_quadfs 0>, 233 <&clk_s_d0_quadfs 1>, 234 <&clk_s_d0_quadfs 2>, 235 <&clk_s_d0_quadfs 3>, 236 <&clk_sysin>; 237 238 clock-output-names = "clk-pcm-0", 239 "clk-pcm-1", 240 "clk-pcm-2", 241 "clk-spdiff", 242 "clk-pcmr10-master", 243 "clk-usb2-phy"; 244 }; 245 }; 246 247 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { 248 #clock-cells = <1>; 249 compatible = "st,quadfs"; 250 reg = <0x9106000 0x1000>; 251 252 clocks = <&clk_sysin>; 253 254 clock-output-names = "clk-s-d2-fs0-ch0", 255 "clk-s-d2-fs0-ch1", 256 "clk-s-d2-fs0-ch2", 257 "clk-s-d2-fs0-ch3"; 258 }; 259 260 clockgen-d2@9106000 { 261 compatible = "st,clkgen-c32"; 262 reg = <0x9106000 0x1000>; 263 264 clk_s_d2_flexgen: clk-s-d2-flexgen { 265 #clock-cells = <1>; 266 compatible = "st,flexgen-video", "st,flexgen"; 267 268 clocks = <&clk_s_d2_quadfs 0>, 269 <&clk_s_d2_quadfs 1>, 270 <&clk_s_d2_quadfs 2>, 271 <&clk_s_d2_quadfs 3>, 272 <&clk_sysin>, 273 <&clk_sysin>, 274 <&clk_tmdsout_hdmi>; 275 276 clock-output-names = "clk-pix-main-disp", 277 "clk-pix-pip", 278 "clk-pix-gdp1", 279 "clk-pix-gdp2", 280 "clk-pix-gdp3", 281 "clk-pix-gdp4", 282 "clk-pix-aux-disp", 283 "clk-denc", 284 "clk-pix-hddac", 285 "clk-hddac", 286 "clk-sddac", 287 "clk-pix-dvo", 288 "clk-dvo", 289 "clk-pix-hdmi", 290 "clk-tmds-hdmi", 291 "clk-ref-hdmiphy"; 292 }; 293 }; 294 295 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { 296 #clock-cells = <1>; 297 compatible = "st,quadfs"; 298 reg = <0x9107000 0x1000>; 299 300 clocks = <&clk_sysin>; 301 302 clock-output-names = "clk-s-d3-fs0-ch0", 303 "clk-s-d3-fs0-ch1", 304 "clk-s-d3-fs0-ch2", 305 "clk-s-d3-fs0-ch3"; 306 }; 307 308 clockgen-d3@9107000 { 309 compatible = "st,clkgen-c32"; 310 reg = <0x9107000 0x1000>; 311 312 clk_s_d3_flexgen: clk-s-d3-flexgen { 313 #clock-cells = <1>; 314 compatible = "st,flexgen"; 315 316 clocks = <&clk_s_d3_quadfs 0>, 317 <&clk_s_d3_quadfs 1>, 318 <&clk_s_d3_quadfs 2>, 319 <&clk_s_d3_quadfs 3>, 320 <&clk_sysin>; 321 322 clock-output-names = "clk-stfe-frc1", 323 "clk-tsout-0", 324 "clk-tsout-1", 325 "clk-mchi", 326 "clk-vsens-compo", 327 "clk-frc1-remote", 328 "clk-lpc-0", 329 "clk-lpc-1"; 330 }; 331 }; 332 }; 333}; 334