1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 clock-frequency = <650000000>; 21 device_type = "cpu"; 22 reg = <0>; 23 }; 24 }; 25 26 arm-pmu { 27 compatible = "arm,cortex-a7-pmu"; 28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 29 interrupt-affinity = <&cpu0>; 30 interrupt-parent = <&intc>; 31 }; 32 33 psci { 34 compatible = "arm,psci-1.0"; 35 method = "smc"; 36 }; 37 38 intc: interrupt-controller@a0021000 { 39 compatible = "arm,cortex-a7-gic"; 40 #interrupt-cells = <3>; 41 interrupt-controller; 42 reg = <0xa0021000 0x1000>, 43 <0xa0022000 0x2000>; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 52 interrupt-parent = <&intc>; 53 }; 54 55 clocks { 56 clk_hse: clk-hse { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <24000000>; 60 }; 61 62 clk_hsi: clk-hsi { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <64000000>; 66 }; 67 68 clk_lse: clk-lse { 69 #clock-cells = <0>; 70 compatible = "fixed-clock"; 71 clock-frequency = <32768>; 72 }; 73 74 clk_lsi: clk-lsi { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <32000>; 78 }; 79 80 clk_csi: clk-csi { 81 #clock-cells = <0>; 82 compatible = "fixed-clock"; 83 clock-frequency = <4000000>; 84 }; 85 }; 86 87 thermal-zones { 88 cpu_thermal: cpu-thermal { 89 polling-delay-passive = <0>; 90 polling-delay = <0>; 91 thermal-sensors = <&dts>; 92 93 trips { 94 cpu_alert1: cpu-alert1 { 95 temperature = <85000>; 96 hysteresis = <0>; 97 type = "passive"; 98 }; 99 100 cpu-crit { 101 temperature = <120000>; 102 hysteresis = <0>; 103 type = "critical"; 104 }; 105 }; 106 107 cooling-maps { 108 }; 109 }; 110 }; 111 112 booster: regulator-booster { 113 compatible = "st,stm32mp1-booster"; 114 st,syscfg = <&syscfg>; 115 status = "disabled"; 116 }; 117 118 soc { 119 compatible = "simple-bus"; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 interrupt-parent = <&intc>; 123 ranges; 124 125 timers2: timer@40000000 { 126 #address-cells = <1>; 127 #size-cells = <0>; 128 compatible = "st,stm32-timers"; 129 reg = <0x40000000 0x400>; 130 clocks = <&rcc TIM2_K>; 131 clock-names = "int"; 132 dmas = <&dmamux1 18 0x400 0x1>, 133 <&dmamux1 19 0x400 0x1>, 134 <&dmamux1 20 0x400 0x1>, 135 <&dmamux1 21 0x400 0x1>, 136 <&dmamux1 22 0x400 0x1>; 137 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 138 status = "disabled"; 139 140 pwm { 141 compatible = "st,stm32-pwm"; 142 #pwm-cells = <3>; 143 status = "disabled"; 144 }; 145 146 timer@1 { 147 compatible = "st,stm32h7-timer-trigger"; 148 reg = <1>; 149 status = "disabled"; 150 }; 151 152 counter { 153 compatible = "st,stm32-timer-counter"; 154 status = "disabled"; 155 }; 156 }; 157 158 timers3: timer@40001000 { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 compatible = "st,stm32-timers"; 162 reg = <0x40001000 0x400>; 163 clocks = <&rcc TIM3_K>; 164 clock-names = "int"; 165 dmas = <&dmamux1 23 0x400 0x1>, 166 <&dmamux1 24 0x400 0x1>, 167 <&dmamux1 25 0x400 0x1>, 168 <&dmamux1 26 0x400 0x1>, 169 <&dmamux1 27 0x400 0x1>, 170 <&dmamux1 28 0x400 0x1>; 171 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 172 status = "disabled"; 173 174 pwm { 175 compatible = "st,stm32-pwm"; 176 #pwm-cells = <3>; 177 status = "disabled"; 178 }; 179 180 timer@2 { 181 compatible = "st,stm32h7-timer-trigger"; 182 reg = <2>; 183 status = "disabled"; 184 }; 185 186 counter { 187 compatible = "st,stm32-timer-counter"; 188 status = "disabled"; 189 }; 190 }; 191 192 timers4: timer@40002000 { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 compatible = "st,stm32-timers"; 196 reg = <0x40002000 0x400>; 197 clocks = <&rcc TIM4_K>; 198 clock-names = "int"; 199 dmas = <&dmamux1 29 0x400 0x1>, 200 <&dmamux1 30 0x400 0x1>, 201 <&dmamux1 31 0x400 0x1>, 202 <&dmamux1 32 0x400 0x1>; 203 dma-names = "ch1", "ch2", "ch3", "ch4"; 204 status = "disabled"; 205 206 pwm { 207 compatible = "st,stm32-pwm"; 208 #pwm-cells = <3>; 209 status = "disabled"; 210 }; 211 212 timer@3 { 213 compatible = "st,stm32h7-timer-trigger"; 214 reg = <3>; 215 status = "disabled"; 216 }; 217 218 counter { 219 compatible = "st,stm32-timer-counter"; 220 status = "disabled"; 221 }; 222 }; 223 224 timers5: timer@40003000 { 225 #address-cells = <1>; 226 #size-cells = <0>; 227 compatible = "st,stm32-timers"; 228 reg = <0x40003000 0x400>; 229 clocks = <&rcc TIM5_K>; 230 clock-names = "int"; 231 dmas = <&dmamux1 55 0x400 0x1>, 232 <&dmamux1 56 0x400 0x1>, 233 <&dmamux1 57 0x400 0x1>, 234 <&dmamux1 58 0x400 0x1>, 235 <&dmamux1 59 0x400 0x1>, 236 <&dmamux1 60 0x400 0x1>; 237 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 238 status = "disabled"; 239 240 pwm { 241 compatible = "st,stm32-pwm"; 242 #pwm-cells = <3>; 243 status = "disabled"; 244 }; 245 246 timer@4 { 247 compatible = "st,stm32h7-timer-trigger"; 248 reg = <4>; 249 status = "disabled"; 250 }; 251 252 counter { 253 compatible = "st,stm32-timer-counter"; 254 status = "disabled"; 255 }; 256 }; 257 258 timers6: timer@40004000 { 259 #address-cells = <1>; 260 #size-cells = <0>; 261 compatible = "st,stm32-timers"; 262 reg = <0x40004000 0x400>; 263 clocks = <&rcc TIM6_K>; 264 clock-names = "int"; 265 dmas = <&dmamux1 69 0x400 0x1>; 266 dma-names = "up"; 267 status = "disabled"; 268 269 timer@5 { 270 compatible = "st,stm32h7-timer-trigger"; 271 reg = <5>; 272 status = "disabled"; 273 }; 274 }; 275 276 timers7: timer@40005000 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "st,stm32-timers"; 280 reg = <0x40005000 0x400>; 281 clocks = <&rcc TIM7_K>; 282 clock-names = "int"; 283 dmas = <&dmamux1 70 0x400 0x1>; 284 dma-names = "up"; 285 status = "disabled"; 286 287 timer@6 { 288 compatible = "st,stm32h7-timer-trigger"; 289 reg = <6>; 290 status = "disabled"; 291 }; 292 }; 293 294 timers12: timer@40006000 { 295 #address-cells = <1>; 296 #size-cells = <0>; 297 compatible = "st,stm32-timers"; 298 reg = <0x40006000 0x400>; 299 clocks = <&rcc TIM12_K>; 300 clock-names = "int"; 301 status = "disabled"; 302 303 pwm { 304 compatible = "st,stm32-pwm"; 305 #pwm-cells = <3>; 306 status = "disabled"; 307 }; 308 309 timer@11 { 310 compatible = "st,stm32h7-timer-trigger"; 311 reg = <11>; 312 status = "disabled"; 313 }; 314 }; 315 316 timers13: timer@40007000 { 317 #address-cells = <1>; 318 #size-cells = <0>; 319 compatible = "st,stm32-timers"; 320 reg = <0x40007000 0x400>; 321 clocks = <&rcc TIM13_K>; 322 clock-names = "int"; 323 status = "disabled"; 324 325 pwm { 326 compatible = "st,stm32-pwm"; 327 #pwm-cells = <3>; 328 status = "disabled"; 329 }; 330 331 timer@12 { 332 compatible = "st,stm32h7-timer-trigger"; 333 reg = <12>; 334 status = "disabled"; 335 }; 336 }; 337 338 timers14: timer@40008000 { 339 #address-cells = <1>; 340 #size-cells = <0>; 341 compatible = "st,stm32-timers"; 342 reg = <0x40008000 0x400>; 343 clocks = <&rcc TIM14_K>; 344 clock-names = "int"; 345 status = "disabled"; 346 347 pwm { 348 compatible = "st,stm32-pwm"; 349 #pwm-cells = <3>; 350 status = "disabled"; 351 }; 352 353 timer@13 { 354 compatible = "st,stm32h7-timer-trigger"; 355 reg = <13>; 356 status = "disabled"; 357 }; 358 }; 359 360 lptimer1: timer@40009000 { 361 #address-cells = <1>; 362 #size-cells = <0>; 363 compatible = "st,stm32-lptimer"; 364 reg = <0x40009000 0x400>; 365 clocks = <&rcc LPTIM1_K>; 366 clock-names = "mux"; 367 status = "disabled"; 368 369 pwm { 370 compatible = "st,stm32-pwm-lp"; 371 #pwm-cells = <3>; 372 status = "disabled"; 373 }; 374 375 trigger@0 { 376 compatible = "st,stm32-lptimer-trigger"; 377 reg = <0>; 378 status = "disabled"; 379 }; 380 381 counter { 382 compatible = "st,stm32-lptimer-counter"; 383 status = "disabled"; 384 }; 385 }; 386 387 spi2: spi@4000b000 { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 compatible = "st,stm32h7-spi"; 391 reg = <0x4000b000 0x400>; 392 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&rcc SPI2_K>; 394 resets = <&rcc SPI2_R>; 395 dmas = <&dmamux1 39 0x400 0x05>, 396 <&dmamux1 40 0x400 0x05>; 397 dma-names = "rx", "tx"; 398 status = "disabled"; 399 }; 400 401 i2s2: audio-controller@4000b000 { 402 compatible = "st,stm32h7-i2s"; 403 #sound-dai-cells = <0>; 404 reg = <0x4000b000 0x400>; 405 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 406 dmas = <&dmamux1 39 0x400 0x01>, 407 <&dmamux1 40 0x400 0x01>; 408 dma-names = "rx", "tx"; 409 status = "disabled"; 410 }; 411 412 spi3: spi@4000c000 { 413 #address-cells = <1>; 414 #size-cells = <0>; 415 compatible = "st,stm32h7-spi"; 416 reg = <0x4000c000 0x400>; 417 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&rcc SPI3_K>; 419 resets = <&rcc SPI3_R>; 420 dmas = <&dmamux1 61 0x400 0x05>, 421 <&dmamux1 62 0x400 0x05>; 422 dma-names = "rx", "tx"; 423 status = "disabled"; 424 }; 425 426 i2s3: audio-controller@4000c000 { 427 compatible = "st,stm32h7-i2s"; 428 #sound-dai-cells = <0>; 429 reg = <0x4000c000 0x400>; 430 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 431 dmas = <&dmamux1 61 0x400 0x01>, 432 <&dmamux1 62 0x400 0x01>; 433 dma-names = "rx", "tx"; 434 status = "disabled"; 435 }; 436 437 spdifrx: audio-controller@4000d000 { 438 compatible = "st,stm32h7-spdifrx"; 439 #sound-dai-cells = <0>; 440 reg = <0x4000d000 0x400>; 441 clocks = <&rcc SPDIF_K>; 442 clock-names = "kclk"; 443 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 444 dmas = <&dmamux1 93 0x400 0x01>, 445 <&dmamux1 94 0x400 0x01>; 446 dma-names = "rx", "rx-ctrl"; 447 status = "disabled"; 448 }; 449 450 usart2: serial@4000e000 { 451 compatible = "st,stm32h7-uart"; 452 reg = <0x4000e000 0x400>; 453 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&rcc USART2_K>; 455 status = "disabled"; 456 }; 457 458 usart3: serial@4000f000 { 459 compatible = "st,stm32h7-uart"; 460 reg = <0x4000f000 0x400>; 461 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&rcc USART3_K>; 463 status = "disabled"; 464 }; 465 466 uart4: serial@40010000 { 467 compatible = "st,stm32h7-uart"; 468 reg = <0x40010000 0x400>; 469 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&rcc UART4_K>; 471 status = "disabled"; 472 }; 473 474 uart5: serial@40011000 { 475 compatible = "st,stm32h7-uart"; 476 reg = <0x40011000 0x400>; 477 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&rcc UART5_K>; 479 status = "disabled"; 480 }; 481 482 i2c1: i2c@40012000 { 483 compatible = "st,stm32mp15-i2c"; 484 reg = <0x40012000 0x400>; 485 interrupt-names = "event", "error"; 486 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&rcc I2C1_K>; 489 resets = <&rcc I2C1_R>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 st,syscfg-fmp = <&syscfg 0x4 0x1>; 493 wakeup-source; 494 status = "disabled"; 495 }; 496 497 i2c2: i2c@40013000 { 498 compatible = "st,stm32mp15-i2c"; 499 reg = <0x40013000 0x400>; 500 interrupt-names = "event", "error"; 501 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&rcc I2C2_K>; 504 resets = <&rcc I2C2_R>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 st,syscfg-fmp = <&syscfg 0x4 0x2>; 508 wakeup-source; 509 status = "disabled"; 510 }; 511 512 i2c3: i2c@40014000 { 513 compatible = "st,stm32mp15-i2c"; 514 reg = <0x40014000 0x400>; 515 interrupt-names = "event", "error"; 516 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&rcc I2C3_K>; 519 resets = <&rcc I2C3_R>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 st,syscfg-fmp = <&syscfg 0x4 0x4>; 523 wakeup-source; 524 status = "disabled"; 525 }; 526 527 i2c5: i2c@40015000 { 528 compatible = "st,stm32mp15-i2c"; 529 reg = <0x40015000 0x400>; 530 interrupt-names = "event", "error"; 531 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&rcc I2C5_K>; 534 resets = <&rcc I2C5_R>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 st,syscfg-fmp = <&syscfg 0x4 0x10>; 538 wakeup-source; 539 status = "disabled"; 540 }; 541 542 cec: cec@40016000 { 543 compatible = "st,stm32-cec"; 544 reg = <0x40016000 0x400>; 545 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&rcc CEC_K>, <&clk_lse>; 547 clock-names = "cec", "hdmi-cec"; 548 status = "disabled"; 549 }; 550 551 dac: dac@40017000 { 552 compatible = "st,stm32h7-dac-core"; 553 reg = <0x40017000 0x400>; 554 clocks = <&rcc DAC12>; 555 clock-names = "pclk"; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 status = "disabled"; 559 560 dac1: dac@1 { 561 compatible = "st,stm32-dac"; 562 #io-channel-cells = <1>; 563 reg = <1>; 564 status = "disabled"; 565 }; 566 567 dac2: dac@2 { 568 compatible = "st,stm32-dac"; 569 #io-channel-cells = <1>; 570 reg = <2>; 571 status = "disabled"; 572 }; 573 }; 574 575 uart7: serial@40018000 { 576 compatible = "st,stm32h7-uart"; 577 reg = <0x40018000 0x400>; 578 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&rcc UART7_K>; 580 status = "disabled"; 581 }; 582 583 uart8: serial@40019000 { 584 compatible = "st,stm32h7-uart"; 585 reg = <0x40019000 0x400>; 586 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&rcc UART8_K>; 588 status = "disabled"; 589 }; 590 591 timers1: timer@44000000 { 592 #address-cells = <1>; 593 #size-cells = <0>; 594 compatible = "st,stm32-timers"; 595 reg = <0x44000000 0x400>; 596 clocks = <&rcc TIM1_K>; 597 clock-names = "int"; 598 dmas = <&dmamux1 11 0x400 0x1>, 599 <&dmamux1 12 0x400 0x1>, 600 <&dmamux1 13 0x400 0x1>, 601 <&dmamux1 14 0x400 0x1>, 602 <&dmamux1 15 0x400 0x1>, 603 <&dmamux1 16 0x400 0x1>, 604 <&dmamux1 17 0x400 0x1>; 605 dma-names = "ch1", "ch2", "ch3", "ch4", 606 "up", "trig", "com"; 607 status = "disabled"; 608 609 pwm { 610 compatible = "st,stm32-pwm"; 611 #pwm-cells = <3>; 612 status = "disabled"; 613 }; 614 615 timer@0 { 616 compatible = "st,stm32h7-timer-trigger"; 617 reg = <0>; 618 status = "disabled"; 619 }; 620 621 counter { 622 compatible = "st,stm32-timer-counter"; 623 status = "disabled"; 624 }; 625 }; 626 627 timers8: timer@44001000 { 628 #address-cells = <1>; 629 #size-cells = <0>; 630 compatible = "st,stm32-timers"; 631 reg = <0x44001000 0x400>; 632 clocks = <&rcc TIM8_K>; 633 clock-names = "int"; 634 dmas = <&dmamux1 47 0x400 0x1>, 635 <&dmamux1 48 0x400 0x1>, 636 <&dmamux1 49 0x400 0x1>, 637 <&dmamux1 50 0x400 0x1>, 638 <&dmamux1 51 0x400 0x1>, 639 <&dmamux1 52 0x400 0x1>, 640 <&dmamux1 53 0x400 0x1>; 641 dma-names = "ch1", "ch2", "ch3", "ch4", 642 "up", "trig", "com"; 643 status = "disabled"; 644 645 pwm { 646 compatible = "st,stm32-pwm"; 647 #pwm-cells = <3>; 648 status = "disabled"; 649 }; 650 651 timer@7 { 652 compatible = "st,stm32h7-timer-trigger"; 653 reg = <7>; 654 status = "disabled"; 655 }; 656 657 counter { 658 compatible = "st,stm32-timer-counter"; 659 status = "disabled"; 660 }; 661 }; 662 663 usart6: serial@44003000 { 664 compatible = "st,stm32h7-uart"; 665 reg = <0x44003000 0x400>; 666 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&rcc USART6_K>; 668 status = "disabled"; 669 }; 670 671 spi1: spi@44004000 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 compatible = "st,stm32h7-spi"; 675 reg = <0x44004000 0x400>; 676 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&rcc SPI1_K>; 678 resets = <&rcc SPI1_R>; 679 dmas = <&dmamux1 37 0x400 0x05>, 680 <&dmamux1 38 0x400 0x05>; 681 dma-names = "rx", "tx"; 682 status = "disabled"; 683 }; 684 685 i2s1: audio-controller@44004000 { 686 compatible = "st,stm32h7-i2s"; 687 #sound-dai-cells = <0>; 688 reg = <0x44004000 0x400>; 689 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 690 dmas = <&dmamux1 37 0x400 0x01>, 691 <&dmamux1 38 0x400 0x01>; 692 dma-names = "rx", "tx"; 693 status = "disabled"; 694 }; 695 696 spi4: spi@44005000 { 697 #address-cells = <1>; 698 #size-cells = <0>; 699 compatible = "st,stm32h7-spi"; 700 reg = <0x44005000 0x400>; 701 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&rcc SPI4_K>; 703 resets = <&rcc SPI4_R>; 704 dmas = <&dmamux1 83 0x400 0x05>, 705 <&dmamux1 84 0x400 0x05>; 706 dma-names = "rx", "tx"; 707 status = "disabled"; 708 }; 709 710 timers15: timer@44006000 { 711 #address-cells = <1>; 712 #size-cells = <0>; 713 compatible = "st,stm32-timers"; 714 reg = <0x44006000 0x400>; 715 clocks = <&rcc TIM15_K>; 716 clock-names = "int"; 717 dmas = <&dmamux1 105 0x400 0x1>, 718 <&dmamux1 106 0x400 0x1>, 719 <&dmamux1 107 0x400 0x1>, 720 <&dmamux1 108 0x400 0x1>; 721 dma-names = "ch1", "up", "trig", "com"; 722 status = "disabled"; 723 724 pwm { 725 compatible = "st,stm32-pwm"; 726 #pwm-cells = <3>; 727 status = "disabled"; 728 }; 729 730 timer@14 { 731 compatible = "st,stm32h7-timer-trigger"; 732 reg = <14>; 733 status = "disabled"; 734 }; 735 }; 736 737 timers16: timer@44007000 { 738 #address-cells = <1>; 739 #size-cells = <0>; 740 compatible = "st,stm32-timers"; 741 reg = <0x44007000 0x400>; 742 clocks = <&rcc TIM16_K>; 743 clock-names = "int"; 744 dmas = <&dmamux1 109 0x400 0x1>, 745 <&dmamux1 110 0x400 0x1>; 746 dma-names = "ch1", "up"; 747 status = "disabled"; 748 749 pwm { 750 compatible = "st,stm32-pwm"; 751 #pwm-cells = <3>; 752 status = "disabled"; 753 }; 754 timer@15 { 755 compatible = "st,stm32h7-timer-trigger"; 756 reg = <15>; 757 status = "disabled"; 758 }; 759 }; 760 761 timers17: timer@44008000 { 762 #address-cells = <1>; 763 #size-cells = <0>; 764 compatible = "st,stm32-timers"; 765 reg = <0x44008000 0x400>; 766 clocks = <&rcc TIM17_K>; 767 clock-names = "int"; 768 dmas = <&dmamux1 111 0x400 0x1>, 769 <&dmamux1 112 0x400 0x1>; 770 dma-names = "ch1", "up"; 771 status = "disabled"; 772 773 pwm { 774 compatible = "st,stm32-pwm"; 775 #pwm-cells = <3>; 776 status = "disabled"; 777 }; 778 779 timer@16 { 780 compatible = "st,stm32h7-timer-trigger"; 781 reg = <16>; 782 status = "disabled"; 783 }; 784 }; 785 786 spi5: spi@44009000 { 787 #address-cells = <1>; 788 #size-cells = <0>; 789 compatible = "st,stm32h7-spi"; 790 reg = <0x44009000 0x400>; 791 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&rcc SPI5_K>; 793 resets = <&rcc SPI5_R>; 794 dmas = <&dmamux1 85 0x400 0x05>, 795 <&dmamux1 86 0x400 0x05>; 796 dma-names = "rx", "tx"; 797 status = "disabled"; 798 }; 799 800 sai1: sai@4400a000 { 801 compatible = "st,stm32h7-sai"; 802 #address-cells = <1>; 803 #size-cells = <1>; 804 ranges = <0 0x4400a000 0x400>; 805 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 806 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 807 resets = <&rcc SAI1_R>; 808 status = "disabled"; 809 810 sai1a: audio-controller@4400a004 { 811 #sound-dai-cells = <0>; 812 813 compatible = "st,stm32-sai-sub-a"; 814 reg = <0x4 0x20>; 815 clocks = <&rcc SAI1_K>; 816 clock-names = "sai_ck"; 817 dmas = <&dmamux1 87 0x400 0x01>; 818 status = "disabled"; 819 }; 820 821 sai1b: audio-controller@4400a024 { 822 #sound-dai-cells = <0>; 823 compatible = "st,stm32-sai-sub-b"; 824 reg = <0x24 0x20>; 825 clocks = <&rcc SAI1_K>; 826 clock-names = "sai_ck"; 827 dmas = <&dmamux1 88 0x400 0x01>; 828 status = "disabled"; 829 }; 830 }; 831 832 sai2: sai@4400b000 { 833 compatible = "st,stm32h7-sai"; 834 #address-cells = <1>; 835 #size-cells = <1>; 836 ranges = <0 0x4400b000 0x400>; 837 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 838 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 839 resets = <&rcc SAI2_R>; 840 status = "disabled"; 841 842 sai2a: audio-controller@4400b004 { 843 #sound-dai-cells = <0>; 844 compatible = "st,stm32-sai-sub-a"; 845 reg = <0x4 0x20>; 846 clocks = <&rcc SAI2_K>; 847 clock-names = "sai_ck"; 848 dmas = <&dmamux1 89 0x400 0x01>; 849 status = "disabled"; 850 }; 851 852 sai2b: audio-controller@4400b024 { 853 #sound-dai-cells = <0>; 854 compatible = "st,stm32-sai-sub-b"; 855 reg = <0x24 0x20>; 856 clocks = <&rcc SAI2_K>; 857 clock-names = "sai_ck"; 858 dmas = <&dmamux1 90 0x400 0x01>; 859 status = "disabled"; 860 }; 861 }; 862 863 sai3: sai@4400c000 { 864 compatible = "st,stm32h7-sai"; 865 #address-cells = <1>; 866 #size-cells = <1>; 867 ranges = <0 0x4400c000 0x400>; 868 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 869 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 870 resets = <&rcc SAI3_R>; 871 status = "disabled"; 872 873 sai3a: audio-controller@4400c004 { 874 #sound-dai-cells = <0>; 875 compatible = "st,stm32-sai-sub-a"; 876 reg = <0x04 0x20>; 877 clocks = <&rcc SAI3_K>; 878 clock-names = "sai_ck"; 879 dmas = <&dmamux1 113 0x400 0x01>; 880 status = "disabled"; 881 }; 882 883 sai3b: audio-controller@4400c024 { 884 #sound-dai-cells = <0>; 885 compatible = "st,stm32-sai-sub-b"; 886 reg = <0x24 0x20>; 887 clocks = <&rcc SAI3_K>; 888 clock-names = "sai_ck"; 889 dmas = <&dmamux1 114 0x400 0x01>; 890 status = "disabled"; 891 }; 892 }; 893 894 dfsdm: dfsdm@4400d000 { 895 compatible = "st,stm32mp1-dfsdm"; 896 reg = <0x4400d000 0x800>; 897 clocks = <&rcc DFSDM_K>; 898 clock-names = "dfsdm"; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 status = "disabled"; 902 903 dfsdm0: filter@0 { 904 compatible = "st,stm32-dfsdm-adc"; 905 #io-channel-cells = <1>; 906 reg = <0>; 907 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 908 dmas = <&dmamux1 101 0x400 0x01>; 909 dma-names = "rx"; 910 status = "disabled"; 911 }; 912 913 dfsdm1: filter@1 { 914 compatible = "st,stm32-dfsdm-adc"; 915 #io-channel-cells = <1>; 916 reg = <1>; 917 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 918 dmas = <&dmamux1 102 0x400 0x01>; 919 dma-names = "rx"; 920 status = "disabled"; 921 }; 922 923 dfsdm2: filter@2 { 924 compatible = "st,stm32-dfsdm-adc"; 925 #io-channel-cells = <1>; 926 reg = <2>; 927 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 928 dmas = <&dmamux1 103 0x400 0x01>; 929 dma-names = "rx"; 930 status = "disabled"; 931 }; 932 933 dfsdm3: filter@3 { 934 compatible = "st,stm32-dfsdm-adc"; 935 #io-channel-cells = <1>; 936 reg = <3>; 937 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 938 dmas = <&dmamux1 104 0x400 0x01>; 939 dma-names = "rx"; 940 status = "disabled"; 941 }; 942 943 dfsdm4: filter@4 { 944 compatible = "st,stm32-dfsdm-adc"; 945 #io-channel-cells = <1>; 946 reg = <4>; 947 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 948 dmas = <&dmamux1 91 0x400 0x01>; 949 dma-names = "rx"; 950 status = "disabled"; 951 }; 952 953 dfsdm5: filter@5 { 954 compatible = "st,stm32-dfsdm-adc"; 955 #io-channel-cells = <1>; 956 reg = <5>; 957 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 958 dmas = <&dmamux1 92 0x400 0x01>; 959 dma-names = "rx"; 960 status = "disabled"; 961 }; 962 }; 963 964 dma1: dma-controller@48000000 { 965 compatible = "st,stm32-dma"; 966 reg = <0x48000000 0x400>; 967 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&rcc DMA1>; 976 resets = <&rcc DMA1_R>; 977 #dma-cells = <4>; 978 st,mem2mem; 979 dma-requests = <8>; 980 }; 981 982 dma2: dma-controller@48001000 { 983 compatible = "st,stm32-dma"; 984 reg = <0x48001000 0x400>; 985 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&rcc DMA2>; 994 resets = <&rcc DMA2_R>; 995 #dma-cells = <4>; 996 st,mem2mem; 997 dma-requests = <8>; 998 }; 999 1000 dmamux1: dma-router@48002000 { 1001 compatible = "st,stm32h7-dmamux"; 1002 reg = <0x48002000 0x1c>; 1003 #dma-cells = <3>; 1004 dma-requests = <128>; 1005 dma-masters = <&dma1 &dma2>; 1006 dma-channels = <16>; 1007 clocks = <&rcc DMAMUX>; 1008 resets = <&rcc DMAMUX_R>; 1009 }; 1010 1011 adc: adc@48003000 { 1012 compatible = "st,stm32mp1-adc-core"; 1013 reg = <0x48003000 0x400>; 1014 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1017 clock-names = "bus", "adc"; 1018 interrupt-controller; 1019 st,syscfg = <&syscfg>; 1020 #interrupt-cells = <1>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 status = "disabled"; 1024 1025 adc1: adc@0 { 1026 compatible = "st,stm32mp1-adc"; 1027 #io-channel-cells = <1>; 1028 reg = <0x0>; 1029 interrupt-parent = <&adc>; 1030 interrupts = <0>; 1031 dmas = <&dmamux1 9 0x400 0x01>; 1032 dma-names = "rx"; 1033 status = "disabled"; 1034 }; 1035 1036 adc2: adc@100 { 1037 compatible = "st,stm32mp1-adc"; 1038 #io-channel-cells = <1>; 1039 reg = <0x100>; 1040 interrupt-parent = <&adc>; 1041 interrupts = <1>; 1042 dmas = <&dmamux1 10 0x400 0x01>; 1043 dma-names = "rx"; 1044 status = "disabled"; 1045 }; 1046 }; 1047 1048 sdmmc3: sdmmc@48004000 { 1049 compatible = "arm,pl18x", "arm,primecell"; 1050 arm,primecell-periphid = <0x10153180>; 1051 reg = <0x48004000 0x400>; 1052 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1053 interrupt-names = "cmd_irq"; 1054 clocks = <&rcc SDMMC3_K>; 1055 clock-names = "apb_pclk"; 1056 resets = <&rcc SDMMC3_R>; 1057 cap-sd-highspeed; 1058 cap-mmc-highspeed; 1059 max-frequency = <120000000>; 1060 status = "disabled"; 1061 }; 1062 1063 usbotg_hs: usb-otg@49000000 { 1064 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1065 reg = <0x49000000 0x10000>; 1066 clocks = <&rcc USBO_K>; 1067 clock-names = "otg"; 1068 resets = <&rcc USBO_R>; 1069 reset-names = "dwc2"; 1070 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1071 g-rx-fifo-size = <256>; 1072 g-np-tx-fifo-size = <32>; 1073 g-tx-fifo-size = <128 128 64 64 64 64 32 32>; 1074 dr_mode = "otg"; 1075 usb33d-supply = <&usb33>; 1076 status = "disabled"; 1077 }; 1078 1079 ipcc: mailbox@4c001000 { 1080 compatible = "st,stm32mp1-ipcc"; 1081 #mbox-cells = <1>; 1082 reg = <0x4c001000 0x400>; 1083 st,proc-id = <0>; 1084 interrupts-extended = 1085 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1086 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1087 <&exti 61 1>; 1088 interrupt-names = "rx", "tx", "wakeup"; 1089 clocks = <&rcc IPCC>; 1090 wakeup-source; 1091 status = "disabled"; 1092 }; 1093 1094 dcmi: dcmi@4c006000 { 1095 compatible = "st,stm32-dcmi"; 1096 reg = <0x4c006000 0x400>; 1097 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1098 resets = <&rcc CAMITF_R>; 1099 clocks = <&rcc DCMI>; 1100 clock-names = "mclk"; 1101 dmas = <&dmamux1 75 0x400 0x0d>; 1102 dma-names = "tx"; 1103 status = "disabled"; 1104 }; 1105 1106 rcc: rcc@50000000 { 1107 compatible = "st,stm32mp1-rcc", "syscon"; 1108 reg = <0x50000000 0x1000>; 1109 #clock-cells = <1>; 1110 #reset-cells = <1>; 1111 }; 1112 1113 pwr_regulators: pwr@50001000 { 1114 compatible = "st,stm32mp1,pwr-reg"; 1115 reg = <0x50001000 0x10>; 1116 1117 reg11: reg11 { 1118 regulator-name = "reg11"; 1119 regulator-min-microvolt = <1100000>; 1120 regulator-max-microvolt = <1100000>; 1121 }; 1122 1123 reg18: reg18 { 1124 regulator-name = "reg18"; 1125 regulator-min-microvolt = <1800000>; 1126 regulator-max-microvolt = <1800000>; 1127 }; 1128 1129 usb33: usb33 { 1130 regulator-name = "usb33"; 1131 regulator-min-microvolt = <3300000>; 1132 regulator-max-microvolt = <3300000>; 1133 }; 1134 }; 1135 1136 pwr_mcu: pwr_mcu@50001014 { 1137 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 1138 reg = <0x50001014 0x4>; 1139 }; 1140 1141 exti: interrupt-controller@5000d000 { 1142 compatible = "st,stm32mp1-exti", "syscon"; 1143 interrupt-controller; 1144 #interrupt-cells = <2>; 1145 reg = <0x5000d000 0x400>; 1146 }; 1147 1148 syscfg: syscon@50020000 { 1149 compatible = "st,stm32mp157-syscfg", "syscon"; 1150 reg = <0x50020000 0x400>; 1151 clocks = <&rcc SYSCFG>; 1152 }; 1153 1154 lptimer2: timer@50021000 { 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 compatible = "st,stm32-lptimer"; 1158 reg = <0x50021000 0x400>; 1159 clocks = <&rcc LPTIM2_K>; 1160 clock-names = "mux"; 1161 status = "disabled"; 1162 1163 pwm { 1164 compatible = "st,stm32-pwm-lp"; 1165 #pwm-cells = <3>; 1166 status = "disabled"; 1167 }; 1168 1169 trigger@1 { 1170 compatible = "st,stm32-lptimer-trigger"; 1171 reg = <1>; 1172 status = "disabled"; 1173 }; 1174 1175 counter { 1176 compatible = "st,stm32-lptimer-counter"; 1177 status = "disabled"; 1178 }; 1179 }; 1180 1181 lptimer3: timer@50022000 { 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 compatible = "st,stm32-lptimer"; 1185 reg = <0x50022000 0x400>; 1186 clocks = <&rcc LPTIM3_K>; 1187 clock-names = "mux"; 1188 status = "disabled"; 1189 1190 pwm { 1191 compatible = "st,stm32-pwm-lp"; 1192 #pwm-cells = <3>; 1193 status = "disabled"; 1194 }; 1195 1196 trigger@2 { 1197 compatible = "st,stm32-lptimer-trigger"; 1198 reg = <2>; 1199 status = "disabled"; 1200 }; 1201 }; 1202 1203 lptimer4: timer@50023000 { 1204 compatible = "st,stm32-lptimer"; 1205 reg = <0x50023000 0x400>; 1206 clocks = <&rcc LPTIM4_K>; 1207 clock-names = "mux"; 1208 status = "disabled"; 1209 1210 pwm { 1211 compatible = "st,stm32-pwm-lp"; 1212 #pwm-cells = <3>; 1213 status = "disabled"; 1214 }; 1215 }; 1216 1217 lptimer5: timer@50024000 { 1218 compatible = "st,stm32-lptimer"; 1219 reg = <0x50024000 0x400>; 1220 clocks = <&rcc LPTIM5_K>; 1221 clock-names = "mux"; 1222 status = "disabled"; 1223 1224 pwm { 1225 compatible = "st,stm32-pwm-lp"; 1226 #pwm-cells = <3>; 1227 status = "disabled"; 1228 }; 1229 }; 1230 1231 vrefbuf: vrefbuf@50025000 { 1232 compatible = "st,stm32-vrefbuf"; 1233 reg = <0x50025000 0x8>; 1234 regulator-min-microvolt = <1500000>; 1235 regulator-max-microvolt = <2500000>; 1236 clocks = <&rcc VREF>; 1237 status = "disabled"; 1238 }; 1239 1240 sai4: sai@50027000 { 1241 compatible = "st,stm32h7-sai"; 1242 #address-cells = <1>; 1243 #size-cells = <1>; 1244 ranges = <0 0x50027000 0x400>; 1245 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1246 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1247 resets = <&rcc SAI4_R>; 1248 status = "disabled"; 1249 1250 sai4a: audio-controller@50027004 { 1251 #sound-dai-cells = <0>; 1252 compatible = "st,stm32-sai-sub-a"; 1253 reg = <0x04 0x20>; 1254 clocks = <&rcc SAI4_K>; 1255 clock-names = "sai_ck"; 1256 dmas = <&dmamux1 99 0x400 0x01>; 1257 status = "disabled"; 1258 }; 1259 1260 sai4b: audio-controller@50027024 { 1261 #sound-dai-cells = <0>; 1262 compatible = "st,stm32-sai-sub-b"; 1263 reg = <0x24 0x20>; 1264 clocks = <&rcc SAI4_K>; 1265 clock-names = "sai_ck"; 1266 dmas = <&dmamux1 100 0x400 0x01>; 1267 status = "disabled"; 1268 }; 1269 }; 1270 1271 dts: thermal@50028000 { 1272 compatible = "st,stm32-thermal"; 1273 reg = <0x50028000 0x100>; 1274 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1275 clocks = <&rcc TMPSENS>; 1276 clock-names = "pclk"; 1277 #thermal-sensor-cells = <0>; 1278 status = "disabled"; 1279 }; 1280 1281 hash1: hash@54002000 { 1282 compatible = "st,stm32f756-hash"; 1283 reg = <0x54002000 0x400>; 1284 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1285 clocks = <&rcc HASH1>; 1286 resets = <&rcc HASH1_R>; 1287 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>; 1288 dma-names = "in"; 1289 dma-maxburst = <2>; 1290 status = "disabled"; 1291 }; 1292 1293 rng1: rng@54003000 { 1294 compatible = "st,stm32-rng"; 1295 reg = <0x54003000 0x400>; 1296 clocks = <&rcc RNG1_K>; 1297 resets = <&rcc RNG1_R>; 1298 status = "disabled"; 1299 }; 1300 1301 mdma1: dma-controller@58000000 { 1302 compatible = "st,stm32h7-mdma"; 1303 reg = <0x58000000 0x1000>; 1304 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1305 clocks = <&rcc MDMA>; 1306 resets = <&rcc MDMA_R>; 1307 #dma-cells = <5>; 1308 dma-channels = <32>; 1309 dma-requests = <48>; 1310 }; 1311 1312 fmc: memory-controller@58002000 { 1313 #address-cells = <2>; 1314 #size-cells = <1>; 1315 compatible = "st,stm32mp1-fmc2-ebi"; 1316 reg = <0x58002000 0x1000>; 1317 clocks = <&rcc FMC_K>; 1318 resets = <&rcc FMC_R>; 1319 status = "disabled"; 1320 1321 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1322 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1323 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1324 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1325 <4 0 0x80000000 0x10000000>; /* NAND */ 1326 1327 nand-controller@4,0 { 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 compatible = "st,stm32mp1-fmc2-nfc"; 1331 reg = <4 0x00000000 0x1000>, 1332 <4 0x08010000 0x1000>, 1333 <4 0x08020000 0x1000>, 1334 <4 0x01000000 0x1000>, 1335 <4 0x09010000 0x1000>, 1336 <4 0x09020000 0x1000>; 1337 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1338 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1339 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1340 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1341 dma-names = "tx", "rx", "ecc"; 1342 status = "disabled"; 1343 }; 1344 }; 1345 1346 qspi: spi@58003000 { 1347 compatible = "st,stm32f469-qspi"; 1348 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1349 reg-names = "qspi", "qspi_mm"; 1350 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1351 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, 1352 <&mdma1 22 0x10 0x100008 0x0 0x0>; 1353 dma-names = "tx", "rx"; 1354 clocks = <&rcc QSPI_K>; 1355 resets = <&rcc QSPI_R>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 status = "disabled"; 1359 }; 1360 1361 sdmmc1: sdmmc@58005000 { 1362 compatible = "arm,pl18x", "arm,primecell"; 1363 arm,primecell-periphid = <0x10153180>; 1364 reg = <0x58005000 0x1000>; 1365 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1366 interrupt-names = "cmd_irq"; 1367 clocks = <&rcc SDMMC1_K>; 1368 clock-names = "apb_pclk"; 1369 resets = <&rcc SDMMC1_R>; 1370 cap-sd-highspeed; 1371 cap-mmc-highspeed; 1372 max-frequency = <120000000>; 1373 status = "disabled"; 1374 }; 1375 1376 sdmmc2: sdmmc@58007000 { 1377 compatible = "arm,pl18x", "arm,primecell"; 1378 arm,primecell-periphid = <0x10153180>; 1379 reg = <0x58007000 0x1000>; 1380 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1381 interrupt-names = "cmd_irq"; 1382 clocks = <&rcc SDMMC2_K>; 1383 clock-names = "apb_pclk"; 1384 resets = <&rcc SDMMC2_R>; 1385 cap-sd-highspeed; 1386 cap-mmc-highspeed; 1387 max-frequency = <120000000>; 1388 status = "disabled"; 1389 }; 1390 1391 crc1: crc@58009000 { 1392 compatible = "st,stm32f7-crc"; 1393 reg = <0x58009000 0x400>; 1394 clocks = <&rcc CRC1>; 1395 status = "disabled"; 1396 }; 1397 1398 ethernet0: ethernet@5800a000 { 1399 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1400 reg = <0x5800a000 0x2000>; 1401 reg-names = "stmmaceth"; 1402 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1403 interrupt-names = "macirq"; 1404 clock-names = "stmmaceth", 1405 "mac-clk-tx", 1406 "mac-clk-rx", 1407 "eth-ck", 1408 "ethstp"; 1409 clocks = <&rcc ETHMAC>, 1410 <&rcc ETHTX>, 1411 <&rcc ETHRX>, 1412 <&rcc ETHCK_K>, 1413 <&rcc ETHSTP>; 1414 st,syscon = <&syscfg 0x4>; 1415 snps,mixed-burst; 1416 snps,pbl = <2>; 1417 snps,en-tx-lpi-clockgating; 1418 snps,axi-config = <&stmmac_axi_config_0>; 1419 snps,tso; 1420 status = "disabled"; 1421 1422 stmmac_axi_config_0: stmmac-axi-config { 1423 snps,wr_osr_lmt = <0x7>; 1424 snps,rd_osr_lmt = <0x7>; 1425 snps,blen = <0 0 0 0 16 8 4>; 1426 }; 1427 }; 1428 1429 usbh_ohci: usbh-ohci@5800c000 { 1430 compatible = "generic-ohci"; 1431 reg = <0x5800c000 0x1000>; 1432 clocks = <&rcc USBH>; 1433 resets = <&rcc USBH_R>; 1434 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1435 status = "disabled"; 1436 }; 1437 1438 usbh_ehci: usbh-ehci@5800d000 { 1439 compatible = "generic-ehci"; 1440 reg = <0x5800d000 0x1000>; 1441 clocks = <&rcc USBH>; 1442 resets = <&rcc USBH_R>; 1443 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1444 companion = <&usbh_ohci>; 1445 status = "disabled"; 1446 }; 1447 1448 ltdc: display-controller@5a001000 { 1449 compatible = "st,stm32-ltdc"; 1450 reg = <0x5a001000 0x400>; 1451 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1453 clocks = <&rcc LTDC_PX>; 1454 clock-names = "lcd"; 1455 resets = <&rcc LTDC_R>; 1456 status = "disabled"; 1457 1458 port { 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 }; 1462 }; 1463 1464 iwdg2: watchdog@5a002000 { 1465 compatible = "st,stm32mp1-iwdg"; 1466 reg = <0x5a002000 0x400>; 1467 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 1468 clock-names = "pclk", "lsi"; 1469 status = "disabled"; 1470 }; 1471 1472 usbphyc: usbphyc@5a006000 { 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 compatible = "st,stm32mp1-usbphyc"; 1476 reg = <0x5a006000 0x1000>; 1477 clocks = <&rcc USBPHY_K>; 1478 resets = <&rcc USBPHY_R>; 1479 status = "disabled"; 1480 1481 usbphyc_port0: usb-phy@0 { 1482 #phy-cells = <0>; 1483 reg = <0>; 1484 }; 1485 1486 usbphyc_port1: usb-phy@1 { 1487 #phy-cells = <1>; 1488 reg = <1>; 1489 }; 1490 }; 1491 1492 usart1: serial@5c000000 { 1493 compatible = "st,stm32h7-uart"; 1494 reg = <0x5c000000 0x400>; 1495 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1496 clocks = <&rcc USART1_K>; 1497 status = "disabled"; 1498 }; 1499 1500 spi6: spi@5c001000 { 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 compatible = "st,stm32h7-spi"; 1504 reg = <0x5c001000 0x400>; 1505 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1506 clocks = <&rcc SPI6_K>; 1507 resets = <&rcc SPI6_R>; 1508 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1509 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1510 dma-names = "rx", "tx"; 1511 status = "disabled"; 1512 }; 1513 1514 i2c4: i2c@5c002000 { 1515 compatible = "st,stm32mp15-i2c"; 1516 reg = <0x5c002000 0x400>; 1517 interrupt-names = "event", "error"; 1518 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1520 clocks = <&rcc I2C4_K>; 1521 resets = <&rcc I2C4_R>; 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1525 wakeup-source; 1526 status = "disabled"; 1527 }; 1528 1529 rtc: rtc@5c004000 { 1530 compatible = "st,stm32mp1-rtc"; 1531 reg = <0x5c004000 0x400>; 1532 clocks = <&rcc RTCAPB>, <&rcc RTC>; 1533 clock-names = "pclk", "rtc_ck"; 1534 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1535 status = "disabled"; 1536 }; 1537 1538 bsec: efuse@5c005000 { 1539 compatible = "st,stm32mp15-bsec"; 1540 reg = <0x5c005000 0x400>; 1541 #address-cells = <1>; 1542 #size-cells = <1>; 1543 ts_cal1: calib@5c { 1544 reg = <0x5c 0x2>; 1545 }; 1546 ts_cal2: calib@5e { 1547 reg = <0x5e 0x2>; 1548 }; 1549 }; 1550 1551 i2c6: i2c@5c009000 { 1552 compatible = "st,stm32mp15-i2c"; 1553 reg = <0x5c009000 0x400>; 1554 interrupt-names = "event", "error"; 1555 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1557 clocks = <&rcc I2C6_K>; 1558 resets = <&rcc I2C6_R>; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1562 wakeup-source; 1563 status = "disabled"; 1564 }; 1565 1566 /* 1567 * Break node order to solve dependency probe issue between 1568 * pinctrl and exti. 1569 */ 1570 pinctrl: pin-controller@50002000 { 1571 #address-cells = <1>; 1572 #size-cells = <1>; 1573 compatible = "st,stm32mp157-pinctrl"; 1574 ranges = <0 0x50002000 0xa400>; 1575 interrupt-parent = <&exti>; 1576 st,syscfg = <&exti 0x60 0xff>; 1577 pins-are-numbered; 1578 1579 gpioa: gpio@50002000 { 1580 gpio-controller; 1581 #gpio-cells = <2>; 1582 interrupt-controller; 1583 #interrupt-cells = <2>; 1584 reg = <0x0 0x400>; 1585 clocks = <&rcc GPIOA>; 1586 st,bank-name = "GPIOA"; 1587 status = "disabled"; 1588 }; 1589 1590 gpiob: gpio@50003000 { 1591 gpio-controller; 1592 #gpio-cells = <2>; 1593 interrupt-controller; 1594 #interrupt-cells = <2>; 1595 reg = <0x1000 0x400>; 1596 clocks = <&rcc GPIOB>; 1597 st,bank-name = "GPIOB"; 1598 status = "disabled"; 1599 }; 1600 1601 gpioc: gpio@50004000 { 1602 gpio-controller; 1603 #gpio-cells = <2>; 1604 interrupt-controller; 1605 #interrupt-cells = <2>; 1606 reg = <0x2000 0x400>; 1607 clocks = <&rcc GPIOC>; 1608 st,bank-name = "GPIOC"; 1609 status = "disabled"; 1610 }; 1611 1612 gpiod: gpio@50005000 { 1613 gpio-controller; 1614 #gpio-cells = <2>; 1615 interrupt-controller; 1616 #interrupt-cells = <2>; 1617 reg = <0x3000 0x400>; 1618 clocks = <&rcc GPIOD>; 1619 st,bank-name = "GPIOD"; 1620 status = "disabled"; 1621 }; 1622 1623 gpioe: gpio@50006000 { 1624 gpio-controller; 1625 #gpio-cells = <2>; 1626 interrupt-controller; 1627 #interrupt-cells = <2>; 1628 reg = <0x4000 0x400>; 1629 clocks = <&rcc GPIOE>; 1630 st,bank-name = "GPIOE"; 1631 status = "disabled"; 1632 }; 1633 1634 gpiof: gpio@50007000 { 1635 gpio-controller; 1636 #gpio-cells = <2>; 1637 interrupt-controller; 1638 #interrupt-cells = <2>; 1639 reg = <0x5000 0x400>; 1640 clocks = <&rcc GPIOF>; 1641 st,bank-name = "GPIOF"; 1642 status = "disabled"; 1643 }; 1644 1645 gpiog: gpio@50008000 { 1646 gpio-controller; 1647 #gpio-cells = <2>; 1648 interrupt-controller; 1649 #interrupt-cells = <2>; 1650 reg = <0x6000 0x400>; 1651 clocks = <&rcc GPIOG>; 1652 st,bank-name = "GPIOG"; 1653 status = "disabled"; 1654 }; 1655 1656 gpioh: gpio@50009000 { 1657 gpio-controller; 1658 #gpio-cells = <2>; 1659 interrupt-controller; 1660 #interrupt-cells = <2>; 1661 reg = <0x7000 0x400>; 1662 clocks = <&rcc GPIOH>; 1663 st,bank-name = "GPIOH"; 1664 status = "disabled"; 1665 }; 1666 1667 gpioi: gpio@5000a000 { 1668 gpio-controller; 1669 #gpio-cells = <2>; 1670 interrupt-controller; 1671 #interrupt-cells = <2>; 1672 reg = <0x8000 0x400>; 1673 clocks = <&rcc GPIOI>; 1674 st,bank-name = "GPIOI"; 1675 status = "disabled"; 1676 }; 1677 1678 gpioj: gpio@5000b000 { 1679 gpio-controller; 1680 #gpio-cells = <2>; 1681 interrupt-controller; 1682 #interrupt-cells = <2>; 1683 reg = <0x9000 0x400>; 1684 clocks = <&rcc GPIOJ>; 1685 st,bank-name = "GPIOJ"; 1686 status = "disabled"; 1687 }; 1688 1689 gpiok: gpio@5000c000 { 1690 gpio-controller; 1691 #gpio-cells = <2>; 1692 interrupt-controller; 1693 #interrupt-cells = <2>; 1694 reg = <0xa000 0x400>; 1695 clocks = <&rcc GPIOK>; 1696 st,bank-name = "GPIOK"; 1697 status = "disabled"; 1698 }; 1699 }; 1700 1701 pinctrl_z: pin-controller-z@54004000 { 1702 #address-cells = <1>; 1703 #size-cells = <1>; 1704 compatible = "st,stm32mp157-z-pinctrl"; 1705 ranges = <0 0x54004000 0x400>; 1706 pins-are-numbered; 1707 interrupt-parent = <&exti>; 1708 st,syscfg = <&exti 0x60 0xff>; 1709 1710 gpioz: gpio@54004000 { 1711 gpio-controller; 1712 #gpio-cells = <2>; 1713 interrupt-controller; 1714 #interrupt-cells = <2>; 1715 reg = <0 0x400>; 1716 clocks = <&rcc GPIOZ>; 1717 st,bank-name = "GPIOZ"; 1718 st,bank-ioport = <11>; 1719 status = "disabled"; 1720 }; 1721 }; 1722 }; 1723 1724 mlahb: ahb { 1725 compatible = "st,mlahb", "simple-bus"; 1726 #address-cells = <1>; 1727 #size-cells = <1>; 1728 ranges; 1729 dma-ranges = <0x00000000 0x38000000 0x10000>, 1730 <0x10000000 0x10000000 0x60000>, 1731 <0x30000000 0x30000000 0x60000>; 1732 1733 m4_rproc: m4@10000000 { 1734 compatible = "st,stm32mp1-m4"; 1735 reg = <0x10000000 0x40000>, 1736 <0x30000000 0x40000>, 1737 <0x38000000 0x10000>; 1738 resets = <&rcc MCU_R>; 1739 st,syscfg-holdboot = <&rcc 0x10C 0x1>; 1740 st,syscfg-tz = <&rcc 0x000 0x1>; 1741 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1742 status = "disabled"; 1743 }; 1744 }; 1745}; 1746