1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4/ { 5 model = "ARM Versatile AB"; 6 compatible = "arm,versatile-ab"; 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&vic>; 10 11 aliases { 12 serial0 = &uart0; 13 serial1 = &uart1; 14 serial2 = &uart2; 15 i2c0 = &i2c0; 16 }; 17 18 chosen { 19 stdout-path = &uart0; 20 }; 21 22 memory { 23 device_type = "memory"; 24 reg = <0x0 0x08000000>; 25 }; 26 27 xtal24mhz: xtal24mhz@24M { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <24000000>; 31 }; 32 33 bridge { 34 compatible = "ti,ths8134b", "ti,ths8134"; 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 ports { 39 #address-cells = <1>; 40 #size-cells = <0>; 41 42 port@0 { 43 reg = <0>; 44 45 vga_bridge_in: endpoint { 46 remote-endpoint = <&clcd_pads_vga_dac>; 47 }; 48 }; 49 50 port@1 { 51 reg = <1>; 52 53 vga_bridge_out: endpoint { 54 remote-endpoint = <&vga_con_in>; 55 }; 56 }; 57 }; 58 }; 59 60 vga { 61 compatible = "vga-connector"; 62 63 port { 64 vga_con_in: endpoint { 65 remote-endpoint = <&vga_bridge_out>; 66 }; 67 }; 68 }; 69 70 core-module@10000000 { 71 compatible = "arm,core-module-versatile", "syscon", "simple-mfd"; 72 reg = <0x10000000 0x200>; 73 74 led@08.0 { 75 compatible = "register-bit-led"; 76 offset = <0x08>; 77 mask = <0x01>; 78 label = "versatile:0"; 79 linux,default-trigger = "heartbeat"; 80 default-state = "on"; 81 }; 82 led@08.1 { 83 compatible = "register-bit-led"; 84 offset = <0x08>; 85 mask = <0x02>; 86 label = "versatile:1"; 87 linux,default-trigger = "mmc0"; 88 default-state = "off"; 89 }; 90 led@08.2 { 91 compatible = "register-bit-led"; 92 offset = <0x08>; 93 mask = <0x04>; 94 label = "versatile:2"; 95 linux,default-trigger = "cpu0"; 96 default-state = "off"; 97 }; 98 led@08.3 { 99 compatible = "register-bit-led"; 100 offset = <0x08>; 101 mask = <0x08>; 102 label = "versatile:3"; 103 default-state = "off"; 104 }; 105 led@08.4 { 106 compatible = "register-bit-led"; 107 offset = <0x08>; 108 mask = <0x10>; 109 label = "versatile:4"; 110 default-state = "off"; 111 }; 112 led@08.5 { 113 compatible = "register-bit-led"; 114 offset = <0x08>; 115 mask = <0x20>; 116 label = "versatile:5"; 117 default-state = "off"; 118 }; 119 led@08.6 { 120 compatible = "register-bit-led"; 121 offset = <0x08>; 122 mask = <0x40>; 123 label = "versatile:6"; 124 default-state = "off"; 125 }; 126 led@08.7 { 127 compatible = "register-bit-led"; 128 offset = <0x08>; 129 mask = <0x80>; 130 label = "versatile:7"; 131 default-state = "off"; 132 }; 133 134 /* OSC1 on AB, OSC4 on PB */ 135 osc1: cm_aux_osc@24M { 136 #clock-cells = <0>; 137 compatible = "arm,versatile-cm-auxosc"; 138 clocks = <&xtal24mhz>; 139 }; 140 141 /* The timer clock is the 24 MHz oscillator divided to 1MHz */ 142 timclk: timclk@1M { 143 #clock-cells = <0>; 144 compatible = "fixed-factor-clock"; 145 clock-div = <24>; 146 clock-mult = <1>; 147 clocks = <&xtal24mhz>; 148 }; 149 150 pclk: pclk@24M { 151 #clock-cells = <0>; 152 compatible = "fixed-factor-clock"; 153 clock-div = <1>; 154 clock-mult = <1>; 155 clocks = <&xtal24mhz>; 156 }; 157 }; 158 159 flash@34000000 { 160 /* 64 MiB NOR flash in non-interleaved chips */ 161 compatible = "arm,versatile-flash", "cfi-flash"; 162 reg = <0x34000000 0x04000000>; 163 bank-width = <4>; 164 partitions { 165 compatible = "arm,arm-firmware-suite"; 166 }; 167 }; 168 169 i2c0: i2c@10002000 { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 compatible = "arm,versatile-i2c"; 173 reg = <0x10002000 0x1000>; 174 175 rtc@68 { 176 compatible = "dallas,ds1338"; 177 reg = <0x68>; 178 }; 179 }; 180 181 net@10010000 { 182 compatible = "smsc,lan91c111"; 183 reg = <0x10010000 0x10000>; 184 interrupts = <25>; 185 }; 186 187 lcd@10008000 { 188 compatible = "arm,versatile-lcd"; 189 reg = <0x10008000 0x1000>; 190 }; 191 192 amba { 193 compatible = "simple-bus"; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 ranges; 197 198 vic: interrupt-controller@10140000 { 199 compatible = "arm,versatile-vic"; 200 interrupt-controller; 201 #interrupt-cells = <1>; 202 reg = <0x10140000 0x1000>; 203 valid-mask = <0xffffffff>; 204 }; 205 206 sic: interrupt-controller@10003000 { 207 compatible = "arm,versatile-sic"; 208 interrupt-controller; 209 #interrupt-cells = <1>; 210 reg = <0x10003000 0x1000>; 211 interrupt-parent = <&vic>; 212 interrupts = <31>; /* Cascaded to vic */ 213 clear-mask = <0xffffffff>; 214 /* 215 * Valid interrupt lines mask according to 216 * table 4-36 page 4-50 of ARM DUI 0225D 217 */ 218 valid-mask = <0x0760031b>; 219 }; 220 221 dma@10130000 { 222 compatible = "arm,pl081", "arm,primecell"; 223 reg = <0x10130000 0x1000>; 224 interrupts = <17>; 225 clocks = <&pclk>; 226 clock-names = "apb_pclk"; 227 }; 228 229 uart0: uart@101f1000 { 230 compatible = "arm,pl011", "arm,primecell"; 231 reg = <0x101f1000 0x1000>; 232 interrupts = <12>; 233 clocks = <&xtal24mhz>, <&pclk>; 234 clock-names = "uartclk", "apb_pclk"; 235 }; 236 237 uart1: uart@101f2000 { 238 compatible = "arm,pl011", "arm,primecell"; 239 reg = <0x101f2000 0x1000>; 240 interrupts = <13>; 241 clocks = <&xtal24mhz>, <&pclk>; 242 clock-names = "uartclk", "apb_pclk"; 243 }; 244 245 uart2: uart@101f3000 { 246 compatible = "arm,pl011", "arm,primecell"; 247 reg = <0x101f3000 0x1000>; 248 interrupts = <14>; 249 clocks = <&xtal24mhz>, <&pclk>; 250 clock-names = "uartclk", "apb_pclk"; 251 }; 252 253 smc@10100000 { 254 compatible = "arm,primecell"; 255 reg = <0x10100000 0x1000>; 256 clocks = <&pclk>; 257 clock-names = "apb_pclk"; 258 }; 259 260 mpmc@10110000 { 261 compatible = "arm,primecell"; 262 reg = <0x10110000 0x1000>; 263 clocks = <&pclk>; 264 clock-names = "apb_pclk"; 265 }; 266 267 display@10120000 { 268 compatible = "arm,pl110", "arm,primecell"; 269 reg = <0x10120000 0x1000>; 270 interrupts = <16>; 271 clocks = <&osc1>, <&pclk>; 272 clock-names = "clcdclk", "apb_pclk"; 273 /* 800x600 16bpp @ 36MHz works fine */ 274 max-memory-bandwidth = <54000000>; 275 276 /* 277 * This port is routed through a PLD (Programmable 278 * Logic Device) that routes the output from the CLCD 279 * (after transformations) to the VGA DAC and also an 280 * external panel connector. The PLD is essential for 281 * supporting RGB565/BGR565. 282 * 283 * The signals from the port thus reaches two endpoints. 284 * The PLD is managed through a few special bits in the 285 * FPGA "sysreg". 286 * 287 * This arrangement can be clearly seen in 288 * ARM DUI 0225D, page 3-41, figure 3-19. 289 */ 290 port@0 { 291 #address-cells = <1>; 292 #size-cells = <0>; 293 294 clcd_pads_panel: endpoint@0 { 295 reg = <0>; 296 remote-endpoint = <&panel_in>; 297 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 298 }; 299 clcd_pads_vga_dac: endpoint@1 { 300 reg = <1>; 301 remote-endpoint = <&vga_bridge_in>; 302 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 303 }; 304 }; 305 }; 306 307 sctl@101e0000 { 308 compatible = "arm,primecell"; 309 reg = <0x101e0000 0x1000>; 310 clocks = <&pclk>; 311 clock-names = "apb_pclk"; 312 }; 313 314 watchdog@101e1000 { 315 compatible = "arm,primecell"; 316 reg = <0x101e1000 0x1000>; 317 interrupts = <0>; 318 clocks = <&pclk>; 319 clock-names = "apb_pclk"; 320 }; 321 322 timer@101e2000 { 323 compatible = "arm,sp804", "arm,primecell"; 324 reg = <0x101e2000 0x1000>; 325 interrupts = <4>; 326 clocks = <&timclk>, <&timclk>, <&pclk>; 327 clock-names = "timer0", "timer1", "apb_pclk"; 328 }; 329 330 timer@101e3000 { 331 compatible = "arm,sp804", "arm,primecell"; 332 reg = <0x101e3000 0x1000>; 333 interrupts = <5>; 334 clocks = <&timclk>, <&timclk>, <&pclk>; 335 clock-names = "timer0", "timer1", "apb_pclk"; 336 }; 337 338 gpio0: gpio@101e4000 { 339 compatible = "arm,pl061", "arm,primecell"; 340 reg = <0x101e4000 0x1000>; 341 gpio-controller; 342 interrupts = <6>; 343 #gpio-cells = <2>; 344 interrupt-controller; 345 #interrupt-cells = <2>; 346 clocks = <&pclk>; 347 clock-names = "apb_pclk"; 348 }; 349 350 gpio1: gpio@101e5000 { 351 compatible = "arm,pl061", "arm,primecell"; 352 reg = <0x101e5000 0x1000>; 353 interrupts = <7>; 354 gpio-controller; 355 #gpio-cells = <2>; 356 interrupt-controller; 357 #interrupt-cells = <2>; 358 clocks = <&pclk>; 359 clock-names = "apb_pclk"; 360 }; 361 362 rtc@101e8000 { 363 compatible = "arm,pl030", "arm,primecell"; 364 reg = <0x101e8000 0x1000>; 365 interrupts = <10>; 366 clocks = <&pclk>; 367 clock-names = "apb_pclk"; 368 }; 369 370 sci@101f0000 { 371 compatible = "arm,primecell"; 372 reg = <0x101f0000 0x1000>; 373 interrupts = <15>; 374 clocks = <&pclk>; 375 clock-names = "apb_pclk"; 376 }; 377 378 spi@101f4000 { 379 compatible = "arm,pl022", "arm,primecell"; 380 reg = <0x101f4000 0x1000>; 381 interrupts = <11>; 382 clocks = <&xtal24mhz>, <&pclk>; 383 clock-names = "SSPCLK", "apb_pclk"; 384 }; 385 386 fpga { 387 compatible = "arm,versatile-fpga", "simple-bus"; 388 #address-cells = <1>; 389 #size-cells = <1>; 390 ranges = <0 0x10000000 0x10000>; 391 392 sysreg@0 { 393 compatible = "arm,versatile-sysreg", "syscon", "simple-mfd"; 394 reg = <0x00000 0x1000>; 395 396 panel: display@0 { 397 compatible = "arm,versatile-tft-panel"; 398 399 port { 400 panel_in: endpoint { 401 remote-endpoint = <&clcd_pads_panel>; 402 }; 403 }; 404 }; 405 }; 406 407 aaci@4000 { 408 compatible = "arm,primecell"; 409 reg = <0x4000 0x1000>; 410 interrupts = <24>; 411 clocks = <&pclk>; 412 clock-names = "apb_pclk"; 413 }; 414 mmc@5000 { 415 compatible = "arm,pl180", "arm,primecell"; 416 reg = <0x5000 0x1000>; 417 interrupts-extended = <&vic 22 &sic 1>; 418 clocks = <&xtal24mhz>, <&pclk>; 419 clock-names = "mclk", "apb_pclk"; 420 }; 421 kmi@6000 { 422 compatible = "arm,pl050", "arm,primecell"; 423 reg = <0x6000 0x1000>; 424 interrupt-parent = <&sic>; 425 interrupts = <3>; 426 clocks = <&xtal24mhz>, <&pclk>; 427 clock-names = "KMIREFCLK", "apb_pclk"; 428 }; 429 kmi@7000 { 430 compatible = "arm,pl050", "arm,primecell"; 431 reg = <0x7000 0x1000>; 432 interrupt-parent = <&sic>; 433 interrupts = <4>; 434 clocks = <&xtal24mhz>, <&pclk>; 435 clock-names = "KMIREFCLK", "apb_pclk"; 436 }; 437 }; 438 }; 439}; 440