1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1012A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2019-2020 NXP 7 * 8 */ 9 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 compatible = "fsl,ls1012a"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 crypto = &crypto; 21 rtc1 = &ftm_alarm0; 22 rtic-a = &rtic_a; 23 rtic-b = &rtic_b; 24 rtic-c = &rtic_c; 25 rtic-d = &rtic_d; 26 sec-mon = &sec_mon; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0>; 37 clocks = <&clockgen 1 0>; 38 #cooling-cells = <2>; 39 cpu-idle-states = <&CPU_PH20>; 40 }; 41 }; 42 43 idle-states { 44 /* 45 * PSCI node is not added default, U-boot will add missing 46 * parts if it determines to use PSCI. 47 */ 48 entry-method = "psci"; 49 50 CPU_PH20: cpu-ph20 { 51 compatible = "arm,idle-state"; 52 idle-state-name = "PH20"; 53 arm,psci-suspend-param = <0x0>; 54 entry-latency-us = <1000>; 55 exit-latency-us = <1000>; 56 min-residency-us = <3000>; 57 }; 58 }; 59 60 sysclk: sysclk { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 clock-frequency = <125000000>; 64 clock-output-names = "sysclk"; 65 }; 66 67 coreclk: coreclk { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <100000000>; 71 clock-output-names = "coreclk"; 72 }; 73 74 timer { 75 compatible = "arm,armv8-timer"; 76 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 77 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 78 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 79 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 80 }; 81 82 pmu { 83 compatible = "arm,armv8-pmuv3"; 84 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 85 }; 86 87 gic: interrupt-controller@1400000 { 88 compatible = "arm,gic-400"; 89 #interrupt-cells = <3>; 90 interrupt-controller; 91 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 92 <0x0 0x1402000 0 0x2000>, /* GICC */ 93 <0x0 0x1404000 0 0x2000>, /* GICH */ 94 <0x0 0x1406000 0 0x2000>; /* GICV */ 95 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>; 96 }; 97 98 reboot { 99 compatible = "syscon-reboot"; 100 regmap = <&dcfg>; 101 offset = <0xb0>; 102 mask = <0x02>; 103 }; 104 105 thermal-zones { 106 cpu_thermal: cpu-thermal { 107 polling-delay-passive = <1000>; 108 polling-delay = <5000>; 109 thermal-sensors = <&tmu 0>; 110 111 trips { 112 cpu_alert: cpu-alert { 113 temperature = <85000>; 114 hysteresis = <2000>; 115 type = "passive"; 116 }; 117 118 cpu_crit: cpu-crit { 119 temperature = <95000>; 120 hysteresis = <2000>; 121 type = "critical"; 122 }; 123 }; 124 125 cooling-maps { 126 map0 { 127 trip = <&cpu_alert>; 128 cooling-device = 129 <&cpu0 THERMAL_NO_LIMIT 130 THERMAL_NO_LIMIT>; 131 }; 132 }; 133 }; 134 }; 135 136 soc { 137 compatible = "simple-bus"; 138 #address-cells = <2>; 139 #size-cells = <2>; 140 ranges; 141 142 qspi: spi@1550000 { 143 compatible = "fsl,ls1021a-qspi"; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 reg = <0x0 0x1550000 0x0 0x10000>, 147 <0x0 0x40000000 0x0 0x10000000>; 148 reg-names = "QuadSPI", "QuadSPI-memory"; 149 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 150 clock-names = "qspi_en", "qspi"; 151 clocks = <&clockgen 4 0>, <&clockgen 4 0>; 152 status = "disabled"; 153 }; 154 155 esdhc0: esdhc@1560000 { 156 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; 157 reg = <0x0 0x1560000 0x0 0x10000>; 158 interrupts = <0 62 0x4>; 159 clocks = <&clockgen 4 0>; 160 voltage-ranges = <1800 1800 3300 3300>; 161 sdhci,auto-cmd12; 162 big-endian; 163 bus-width = <4>; 164 status = "disabled"; 165 }; 166 167 scfg: scfg@1570000 { 168 compatible = "fsl,ls1012a-scfg", "syscon"; 169 reg = <0x0 0x1570000 0x0 0x10000>; 170 big-endian; 171 }; 172 173 esdhc1: esdhc@1580000 { 174 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; 175 reg = <0x0 0x1580000 0x0 0x10000>; 176 interrupts = <0 65 0x4>; 177 clocks = <&clockgen 4 0>; 178 voltage-ranges = <1800 1800 3300 3300>; 179 sdhci,auto-cmd12; 180 big-endian; 181 broken-cd; 182 bus-width = <4>; 183 status = "disabled"; 184 }; 185 186 crypto: crypto@1700000 { 187 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 188 "fsl,sec-v4.0"; 189 fsl,sec-era = <8>; 190 #address-cells = <1>; 191 #size-cells = <1>; 192 ranges = <0x0 0x00 0x1700000 0x100000>; 193 reg = <0x00 0x1700000 0x0 0x100000>; 194 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 195 dma-coherent; 196 197 sec_jr0: jr@10000 { 198 compatible = "fsl,sec-v5.4-job-ring", 199 "fsl,sec-v5.0-job-ring", 200 "fsl,sec-v4.0-job-ring"; 201 reg = <0x10000 0x10000>; 202 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 203 }; 204 205 sec_jr1: jr@20000 { 206 compatible = "fsl,sec-v5.4-job-ring", 207 "fsl,sec-v5.0-job-ring", 208 "fsl,sec-v4.0-job-ring"; 209 reg = <0x20000 0x10000>; 210 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 211 }; 212 213 sec_jr2: jr@30000 { 214 compatible = "fsl,sec-v5.4-job-ring", 215 "fsl,sec-v5.0-job-ring", 216 "fsl,sec-v4.0-job-ring"; 217 reg = <0x30000 0x10000>; 218 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 219 }; 220 221 sec_jr3: jr@40000 { 222 compatible = "fsl,sec-v5.4-job-ring", 223 "fsl,sec-v5.0-job-ring", 224 "fsl,sec-v4.0-job-ring"; 225 reg = <0x40000 0x10000>; 226 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 227 }; 228 229 rtic@60000 { 230 compatible = "fsl,sec-v5.4-rtic", 231 "fsl,sec-v5.0-rtic", 232 "fsl,sec-v4.0-rtic"; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 reg = <0x60000 0x100 0x60e00 0x18>; 236 ranges = <0x0 0x60100 0x500>; 237 238 rtic_a: rtic-a@0 { 239 compatible = "fsl,sec-v5.4-rtic-memory", 240 "fsl,sec-v5.0-rtic-memory", 241 "fsl,sec-v4.0-rtic-memory"; 242 reg = <0x00 0x20 0x100 0x100>; 243 }; 244 245 rtic_b: rtic-b@20 { 246 compatible = "fsl,sec-v5.4-rtic-memory", 247 "fsl,sec-v5.0-rtic-memory", 248 "fsl,sec-v4.0-rtic-memory"; 249 reg = <0x20 0x20 0x200 0x100>; 250 }; 251 252 rtic_c: rtic-c@40 { 253 compatible = "fsl,sec-v5.4-rtic-memory", 254 "fsl,sec-v5.0-rtic-memory", 255 "fsl,sec-v4.0-rtic-memory"; 256 reg = <0x40 0x20 0x300 0x100>; 257 }; 258 259 rtic_d: rtic-d@60 { 260 compatible = "fsl,sec-v5.4-rtic-memory", 261 "fsl,sec-v5.0-rtic-memory", 262 "fsl,sec-v4.0-rtic-memory"; 263 reg = <0x60 0x20 0x400 0x100>; 264 }; 265 }; 266 }; 267 268 sec_mon: sec_mon@1e90000 { 269 compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", 270 "fsl,sec-v4.0-mon"; 271 reg = <0x0 0x1e90000 0x0 0x10000>; 272 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 274 }; 275 276 dcfg: dcfg@1ee0000 { 277 compatible = "fsl,ls1012a-dcfg", 278 "syscon"; 279 reg = <0x0 0x1ee0000 0x0 0x10000>; 280 big-endian; 281 }; 282 283 clockgen: clocking@1ee1000 { 284 compatible = "fsl,ls1012a-clockgen"; 285 reg = <0x0 0x1ee1000 0x0 0x1000>; 286 #clock-cells = <2>; 287 clocks = <&sysclk &coreclk>; 288 clock-names = "sysclk", "coreclk"; 289 }; 290 291 tmu: tmu@1f00000 { 292 compatible = "fsl,qoriq-tmu"; 293 reg = <0x0 0x1f00000 0x0 0x10000>; 294 interrupts = <0 33 0x4>; 295 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 296 fsl,tmu-calibration = <0x00000000 0x00000026 297 0x00000001 0x0000002d 298 0x00000002 0x00000032 299 0x00000003 0x00000039 300 0x00000004 0x0000003f 301 0x00000005 0x00000046 302 0x00000006 0x0000004d 303 0x00000007 0x00000054 304 0x00000008 0x0000005a 305 0x00000009 0x00000061 306 0x0000000a 0x0000006a 307 0x0000000b 0x00000071 308 309 0x00010000 0x00000025 310 0x00010001 0x0000002c 311 0x00010002 0x00000035 312 0x00010003 0x0000003d 313 0x00010004 0x00000045 314 0x00010005 0x0000004e 315 0x00010006 0x00000057 316 0x00010007 0x00000061 317 0x00010008 0x0000006b 318 0x00010009 0x00000076 319 320 0x00020000 0x00000029 321 0x00020001 0x00000033 322 0x00020002 0x0000003d 323 0x00020003 0x00000049 324 0x00020004 0x00000056 325 0x00020005 0x00000061 326 0x00020006 0x0000006d 327 328 0x00030000 0x00000021 329 0x00030001 0x0000002a 330 0x00030002 0x0000003c 331 0x00030003 0x0000004e>; 332 big-endian; 333 #thermal-sensor-cells = <1>; 334 }; 335 336 i2c0: i2c@2180000 { 337 compatible = "fsl,vf610-i2c"; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 reg = <0x0 0x2180000 0x0 0x10000>; 341 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&clockgen 4 3>; 343 status = "disabled"; 344 }; 345 346 i2c1: i2c@2190000 { 347 compatible = "fsl,vf610-i2c"; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 reg = <0x0 0x2190000 0x0 0x10000>; 351 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&clockgen 4 3>; 353 status = "disabled"; 354 }; 355 356 dspi: spi@2100000 { 357 compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi"; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 reg = <0x0 0x2100000 0x0 0x10000>; 361 interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; 362 clock-names = "dspi"; 363 clocks = <&clockgen 4 0>; 364 spi-num-chipselects = <5>; 365 big-endian; 366 status = "disabled"; 367 }; 368 369 duart0: serial@21c0500 { 370 compatible = "fsl,ns16550", "ns16550a"; 371 reg = <0x00 0x21c0500 0x0 0x100>; 372 interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&clockgen 4 0>; 374 status = "disabled"; 375 }; 376 377 duart1: serial@21c0600 { 378 compatible = "fsl,ns16550", "ns16550a"; 379 reg = <0x00 0x21c0600 0x0 0x100>; 380 interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&clockgen 4 0>; 382 status = "disabled"; 383 }; 384 385 gpio0: gpio@2300000 { 386 compatible = "fsl,qoriq-gpio"; 387 reg = <0x0 0x2300000 0x0 0x10000>; 388 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; 389 gpio-controller; 390 #gpio-cells = <2>; 391 interrupt-controller; 392 #interrupt-cells = <2>; 393 }; 394 395 gpio1: gpio@2310000 { 396 compatible = "fsl,qoriq-gpio"; 397 reg = <0x0 0x2310000 0x0 0x10000>; 398 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; 399 gpio-controller; 400 #gpio-cells = <2>; 401 interrupt-controller; 402 #interrupt-cells = <2>; 403 }; 404 405 wdog0: wdog@2ad0000 { 406 compatible = "fsl,ls1012a-wdt", 407 "fsl,imx21-wdt"; 408 reg = <0x0 0x2ad0000 0x0 0x10000>; 409 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&clockgen 4 0>; 411 big-endian; 412 }; 413 414 sai1: sai@2b50000 { 415 #sound-dai-cells = <0>; 416 compatible = "fsl,vf610-sai"; 417 reg = <0x0 0x2b50000 0x0 0x10000>; 418 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&clockgen 4 3>, <&clockgen 4 3>, 420 <&clockgen 4 3>, <&clockgen 4 3>; 421 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 422 dma-names = "tx", "rx"; 423 dmas = <&edma0 1 47>, 424 <&edma0 1 46>; 425 status = "disabled"; 426 }; 427 428 sai2: sai@2b60000 { 429 #sound-dai-cells = <0>; 430 compatible = "fsl,vf610-sai"; 431 reg = <0x0 0x2b60000 0x0 0x10000>; 432 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&clockgen 4 3>, <&clockgen 4 3>, 434 <&clockgen 4 3>, <&clockgen 4 3>; 435 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 436 dma-names = "tx", "rx"; 437 dmas = <&edma0 1 45>, 438 <&edma0 1 44>; 439 status = "disabled"; 440 }; 441 442 edma0: edma@2c00000 { 443 #dma-cells = <2>; 444 compatible = "fsl,vf610-edma"; 445 reg = <0x0 0x2c00000 0x0 0x10000>, 446 <0x0 0x2c10000 0x0 0x10000>, 447 <0x0 0x2c20000 0x0 0x10000>; 448 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>, 449 <0 103 IRQ_TYPE_LEVEL_HIGH>; 450 interrupt-names = "edma-tx", "edma-err"; 451 dma-channels = <32>; 452 big-endian; 453 clock-names = "dmamux0", "dmamux1"; 454 clocks = <&clockgen 4 3>, 455 <&clockgen 4 3>; 456 }; 457 458 usb0: usb3@2f00000 { 459 compatible = "snps,dwc3"; 460 reg = <0x0 0x2f00000 0x0 0x10000>; 461 interrupts = <0 60 0x4>; 462 dr_mode = "host"; 463 snps,quirk-frame-length-adjustment = <0x20>; 464 snps,dis_rxdet_inp3_quirk; 465 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 466 }; 467 468 sata: sata@3200000 { 469 compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; 470 reg = <0x0 0x3200000 0x0 0x10000>, 471 <0x0 0x20140520 0x0 0x4>; 472 reg-names = "ahci", "sata-ecc"; 473 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&clockgen 4 0>; 475 dma-coherent; 476 status = "disabled"; 477 }; 478 479 usb1: usb2@8600000 { 480 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 481 reg = <0x0 0x8600000 0x0 0x1000>; 482 interrupts = <0 139 0x4>; 483 dr_mode = "host"; 484 phy_type = "ulpi"; 485 }; 486 487 msi: msi-controller1@1572000 { 488 compatible = "fsl,ls1012a-msi"; 489 reg = <0x0 0x1572000 0x0 0x8>; 490 msi-controller; 491 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; 492 }; 493 494 pcie1: pcie@3400000 { 495 compatible = "fsl,ls1012a-pcie"; 496 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 497 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 498 reg-names = "regs", "config"; 499 interrupts = <0 118 0x4>, /* controller interrupt */ 500 <0 117 0x4>; /* PME interrupt */ 501 interrupt-names = "aer", "pme"; 502 #address-cells = <3>; 503 #size-cells = <2>; 504 device_type = "pci"; 505 num-viewport = <2>; 506 bus-range = <0x0 0xff>; 507 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 508 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 509 msi-parent = <&msi>; 510 #interrupt-cells = <1>; 511 interrupt-map-mask = <0 0 0 7>; 512 interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>, 513 <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, 514 <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, 515 <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; 516 status = "disabled"; 517 }; 518 519 rcpm: power-controller@1ee2140 { 520 compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+"; 521 reg = <0x0 0x1ee2140 0x0 0x4>; 522 #fsl,rcpm-wakeup-cells = <1>; 523 }; 524 525 ftm_alarm0: timer@29d0000 { 526 compatible = "fsl,ls1012a-ftm-alarm"; 527 reg = <0x0 0x29d0000 0x0 0x10000>; 528 fsl,rcpm-wakeup = <&rcpm 0x20000>; 529 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 530 big-endian; 531 }; 532 }; 533 534 firmware { 535 optee { 536 compatible = "linaro,optee-tz"; 537 method = "smc"; 538 }; 539 }; 540}; 541