1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1028a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 rtc1 = &ftm_alarm0; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a72"; 31 reg = <0x0>; 32 enable-method = "psci"; 33 clocks = <&clockgen 1 0>; 34 next-level-cache = <&l2>; 35 cpu-idle-states = <&CPU_PW20>; 36 #cooling-cells = <2>; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a72"; 42 reg = <0x1>; 43 enable-method = "psci"; 44 clocks = <&clockgen 1 0>; 45 next-level-cache = <&l2>; 46 cpu-idle-states = <&CPU_PW20>; 47 #cooling-cells = <2>; 48 }; 49 50 l2: l2-cache { 51 compatible = "cache"; 52 }; 53 }; 54 55 idle-states { 56 /* 57 * PSCI node is not added default, U-boot will add missing 58 * parts if it determines to use PSCI. 59 */ 60 entry-method = "psci"; 61 62 CPU_PW20: cpu-pw20 { 63 compatible = "arm,idle-state"; 64 idle-state-name = "PW20"; 65 arm,psci-suspend-param = <0x0>; 66 entry-latency-us = <2000>; 67 exit-latency-us = <2000>; 68 min-residency-us = <6000>; 69 }; 70 }; 71 72 sysclk: sysclk { 73 compatible = "fixed-clock"; 74 #clock-cells = <0>; 75 clock-frequency = <100000000>; 76 clock-output-names = "sysclk"; 77 }; 78 79 osc_27m: clock-osc-27m { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 clock-frequency = <27000000>; 83 clock-output-names = "phy_27m"; 84 }; 85 86 dpclk: clock-controller@f1f0000 { 87 compatible = "fsl,ls1028a-plldig"; 88 reg = <0x0 0xf1f0000 0x0 0xffff>; 89 #clock-cells = <0>; 90 clocks = <&osc_27m>; 91 }; 92 93 reboot { 94 compatible ="syscon-reboot"; 95 regmap = <&rst>; 96 offset = <0>; 97 mask = <0x02>; 98 }; 99 100 timer { 101 compatible = "arm,armv8-timer"; 102 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 103 IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 105 IRQ_TYPE_LEVEL_LOW)>, 106 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 107 IRQ_TYPE_LEVEL_LOW)>, 108 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 109 IRQ_TYPE_LEVEL_LOW)>; 110 }; 111 112 pmu { 113 compatible = "arm,cortex-a72-pmu"; 114 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 115 }; 116 117 gic: interrupt-controller@6000000 { 118 compatible= "arm,gic-v3"; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges; 122 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 123 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 124 #interrupt-cells= <3>; 125 interrupt-controller; 126 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 127 IRQ_TYPE_LEVEL_LOW)>; 128 its: gic-its@6020000 { 129 compatible = "arm,gic-v3-its"; 130 msi-controller; 131 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 132 }; 133 }; 134 135 thermal-zones { 136 ddr-controller { 137 polling-delay-passive = <1000>; 138 polling-delay = <5000>; 139 thermal-sensors = <&tmu 0>; 140 141 trips { 142 ddr-ctrler-alert { 143 temperature = <85000>; 144 hysteresis = <2000>; 145 type = "passive"; 146 }; 147 148 ddr-ctrler-crit { 149 temperature = <95000>; 150 hysteresis = <2000>; 151 type = "critical"; 152 }; 153 }; 154 }; 155 156 core-cluster { 157 polling-delay-passive = <1000>; 158 polling-delay = <5000>; 159 thermal-sensors = <&tmu 1>; 160 161 trips { 162 core_cluster_alert: core-cluster-alert { 163 temperature = <85000>; 164 hysteresis = <2000>; 165 type = "passive"; 166 }; 167 168 core_cluster_crit: core-cluster-crit { 169 temperature = <95000>; 170 hysteresis = <2000>; 171 type = "critical"; 172 }; 173 }; 174 175 cooling-maps { 176 map0 { 177 trip = <&core_cluster_alert>; 178 cooling-device = 179 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 180 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 181 }; 182 }; 183 }; 184 }; 185 186 soc: soc { 187 compatible = "simple-bus"; 188 #address-cells = <2>; 189 #size-cells = <2>; 190 ranges; 191 192 ddr: memory-controller@1080000 { 193 compatible = "fsl,qoriq-memory-controller"; 194 reg = <0x0 0x1080000 0x0 0x1000>; 195 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 196 little-endian; 197 }; 198 199 dcfg: syscon@1e00000 { 200 compatible = "fsl,ls1028a-dcfg", "syscon"; 201 reg = <0x0 0x1e00000 0x0 0x10000>; 202 little-endian; 203 }; 204 205 rst: syscon@1e60000 { 206 compatible = "syscon"; 207 reg = <0x0 0x1e60000 0x0 0x10000>; 208 little-endian; 209 }; 210 211 scfg: syscon@1fc0000 { 212 compatible = "fsl,ls1028a-scfg", "syscon"; 213 reg = <0x0 0x1fc0000 0x0 0x10000>; 214 big-endian; 215 }; 216 217 clockgen: clock-controller@1300000 { 218 compatible = "fsl,ls1028a-clockgen"; 219 reg = <0x0 0x1300000 0x0 0xa0000>; 220 #clock-cells = <2>; 221 clocks = <&sysclk>; 222 }; 223 224 i2c0: i2c@2000000 { 225 compatible = "fsl,vf610-i2c"; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 reg = <0x0 0x2000000 0x0 0x10000>; 229 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&clockgen 4 3>; 231 status = "disabled"; 232 }; 233 234 i2c1: i2c@2010000 { 235 compatible = "fsl,vf610-i2c"; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 reg = <0x0 0x2010000 0x0 0x10000>; 239 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&clockgen 4 3>; 241 status = "disabled"; 242 }; 243 244 i2c2: i2c@2020000 { 245 compatible = "fsl,vf610-i2c"; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 reg = <0x0 0x2020000 0x0 0x10000>; 249 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&clockgen 4 3>; 251 status = "disabled"; 252 }; 253 254 i2c3: i2c@2030000 { 255 compatible = "fsl,vf610-i2c"; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 reg = <0x0 0x2030000 0x0 0x10000>; 259 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&clockgen 4 3>; 261 status = "disabled"; 262 }; 263 264 i2c4: i2c@2040000 { 265 compatible = "fsl,vf610-i2c"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 reg = <0x0 0x2040000 0x0 0x10000>; 269 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&clockgen 4 3>; 271 status = "disabled"; 272 }; 273 274 i2c5: i2c@2050000 { 275 compatible = "fsl,vf610-i2c"; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 reg = <0x0 0x2050000 0x0 0x10000>; 279 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&clockgen 4 3>; 281 status = "disabled"; 282 }; 283 284 i2c6: i2c@2060000 { 285 compatible = "fsl,vf610-i2c"; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 reg = <0x0 0x2060000 0x0 0x10000>; 289 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&clockgen 4 3>; 291 status = "disabled"; 292 }; 293 294 i2c7: i2c@2070000 { 295 compatible = "fsl,vf610-i2c"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 reg = <0x0 0x2070000 0x0 0x10000>; 299 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&clockgen 4 3>; 301 status = "disabled"; 302 }; 303 304 fspi: spi@20c0000 { 305 compatible = "nxp,lx2160a-fspi"; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 reg = <0x0 0x20c0000 0x0 0x10000>, 309 <0x0 0x20000000 0x0 0x10000000>; 310 reg-names = "fspi_base", "fspi_mmap"; 311 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&clockgen 2 0>, <&clockgen 2 0>; 313 clock-names = "fspi_en", "fspi"; 314 status = "disabled"; 315 }; 316 317 dspi0: spi@2100000 { 318 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 reg = <0x0 0x2100000 0x0 0x10000>; 322 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 323 clock-names = "dspi"; 324 clocks = <&clockgen 4 1>; 325 dmas = <&edma0 0 62>, <&edma0 0 60>; 326 dma-names = "tx", "rx"; 327 spi-num-chipselects = <4>; 328 little-endian; 329 status = "disabled"; 330 }; 331 332 dspi1: spi@2110000 { 333 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 reg = <0x0 0x2110000 0x0 0x10000>; 337 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 338 clock-names = "dspi"; 339 clocks = <&clockgen 4 1>; 340 dmas = <&edma0 0 58>, <&edma0 0 56>; 341 dma-names = "tx", "rx"; 342 spi-num-chipselects = <4>; 343 little-endian; 344 status = "disabled"; 345 }; 346 347 dspi2: spi@2120000 { 348 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 reg = <0x0 0x2120000 0x0 0x10000>; 352 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 353 clock-names = "dspi"; 354 clocks = <&clockgen 4 1>; 355 dmas = <&edma0 0 54>, <&edma0 0 2>; 356 dma-names = "tx", "rx"; 357 spi-num-chipselects = <3>; 358 little-endian; 359 status = "disabled"; 360 }; 361 362 esdhc: mmc@2140000 { 363 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 364 reg = <0x0 0x2140000 0x0 0x10000>; 365 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 366 clock-frequency = <0>; /* fixed up by bootloader */ 367 clocks = <&clockgen 2 1>; 368 voltage-ranges = <1800 1800 3300 3300>; 369 sdhci,auto-cmd12; 370 little-endian; 371 bus-width = <4>; 372 status = "disabled"; 373 }; 374 375 esdhc1: mmc@2150000 { 376 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 377 reg = <0x0 0x2150000 0x0 0x10000>; 378 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 379 clock-frequency = <0>; /* fixed up by bootloader */ 380 clocks = <&clockgen 2 1>; 381 voltage-ranges = <1800 1800 3300 3300>; 382 sdhci,auto-cmd12; 383 broken-cd; 384 little-endian; 385 bus-width = <4>; 386 status = "disabled"; 387 }; 388 389 can0: can@2180000 { 390 compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; 391 reg = <0x0 0x2180000 0x0 0x10000>; 392 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&sysclk>, <&clockgen 4 1>; 394 clock-names = "ipg", "per"; 395 status = "disabled"; 396 }; 397 398 can1: can@2190000 { 399 compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; 400 reg = <0x0 0x2190000 0x0 0x10000>; 401 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&sysclk>, <&clockgen 4 1>; 403 clock-names = "ipg", "per"; 404 status = "disabled"; 405 }; 406 407 duart0: serial@21c0500 { 408 compatible = "fsl,ns16550", "ns16550a"; 409 reg = <0x00 0x21c0500 0x0 0x100>; 410 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&clockgen 4 1>; 412 status = "disabled"; 413 }; 414 415 duart1: serial@21c0600 { 416 compatible = "fsl,ns16550", "ns16550a"; 417 reg = <0x00 0x21c0600 0x0 0x100>; 418 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&clockgen 4 1>; 420 status = "disabled"; 421 }; 422 423 424 lpuart0: serial@2260000 { 425 compatible = "fsl,ls1028a-lpuart"; 426 reg = <0x0 0x2260000 0x0 0x1000>; 427 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&clockgen 4 1>; 429 clock-names = "ipg"; 430 dma-names = "rx","tx"; 431 dmas = <&edma0 1 32>, 432 <&edma0 1 33>; 433 status = "disabled"; 434 }; 435 436 lpuart1: serial@2270000 { 437 compatible = "fsl,ls1028a-lpuart"; 438 reg = <0x0 0x2270000 0x0 0x1000>; 439 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clockgen 4 1>; 441 clock-names = "ipg"; 442 dma-names = "rx","tx"; 443 dmas = <&edma0 1 30>, 444 <&edma0 1 31>; 445 status = "disabled"; 446 }; 447 448 lpuart2: serial@2280000 { 449 compatible = "fsl,ls1028a-lpuart"; 450 reg = <0x0 0x2280000 0x0 0x1000>; 451 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&clockgen 4 1>; 453 clock-names = "ipg"; 454 dma-names = "rx","tx"; 455 dmas = <&edma0 1 28>, 456 <&edma0 1 29>; 457 status = "disabled"; 458 }; 459 460 lpuart3: serial@2290000 { 461 compatible = "fsl,ls1028a-lpuart"; 462 reg = <0x0 0x2290000 0x0 0x1000>; 463 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&clockgen 4 1>; 465 clock-names = "ipg"; 466 dma-names = "rx","tx"; 467 dmas = <&edma0 1 26>, 468 <&edma0 1 27>; 469 status = "disabled"; 470 }; 471 472 lpuart4: serial@22a0000 { 473 compatible = "fsl,ls1028a-lpuart"; 474 reg = <0x0 0x22a0000 0x0 0x1000>; 475 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&clockgen 4 1>; 477 clock-names = "ipg"; 478 dma-names = "rx","tx"; 479 dmas = <&edma0 1 24>, 480 <&edma0 1 25>; 481 status = "disabled"; 482 }; 483 484 lpuart5: serial@22b0000 { 485 compatible = "fsl,ls1028a-lpuart"; 486 reg = <0x0 0x22b0000 0x0 0x1000>; 487 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&clockgen 4 1>; 489 clock-names = "ipg"; 490 dma-names = "rx","tx"; 491 dmas = <&edma0 1 22>, 492 <&edma0 1 23>; 493 status = "disabled"; 494 }; 495 496 edma0: dma-controller@22c0000 { 497 #dma-cells = <2>; 498 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 499 reg = <0x0 0x22c0000 0x0 0x10000>, 500 <0x0 0x22d0000 0x0 0x10000>, 501 <0x0 0x22e0000 0x0 0x10000>; 502 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 504 interrupt-names = "edma-tx", "edma-err"; 505 dma-channels = <32>; 506 clock-names = "dmamux0", "dmamux1"; 507 clocks = <&clockgen 4 1>, 508 <&clockgen 4 1>; 509 }; 510 511 gpio1: gpio@2300000 { 512 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 513 reg = <0x0 0x2300000 0x0 0x10000>; 514 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 515 gpio-controller; 516 #gpio-cells = <2>; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 little-endian; 520 }; 521 522 gpio2: gpio@2310000 { 523 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 524 reg = <0x0 0x2310000 0x0 0x10000>; 525 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 526 gpio-controller; 527 #gpio-cells = <2>; 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 little-endian; 531 }; 532 533 gpio3: gpio@2320000 { 534 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 535 reg = <0x0 0x2320000 0x0 0x10000>; 536 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 537 gpio-controller; 538 #gpio-cells = <2>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 little-endian; 542 }; 543 544 usb0: usb@3100000 { 545 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 546 reg = <0x0 0x3100000 0x0 0x10000>; 547 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 548 dr_mode = "host"; 549 snps,dis_rxdet_inp3_quirk; 550 snps,quirk-frame-length-adjustment = <0x20>; 551 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 552 }; 553 554 usb1: usb@3110000 { 555 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 556 reg = <0x0 0x3110000 0x0 0x10000>; 557 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 558 dr_mode = "host"; 559 snps,dis_rxdet_inp3_quirk; 560 snps,quirk-frame-length-adjustment = <0x20>; 561 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 562 }; 563 564 sata: sata@3200000 { 565 compatible = "fsl,ls1028a-ahci"; 566 reg = <0x0 0x3200000 0x0 0x10000>, 567 <0x7 0x100520 0x0 0x4>; 568 reg-names = "ahci", "sata-ecc"; 569 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&clockgen 4 1>; 571 status = "disabled"; 572 }; 573 574 pcie1: pcie@3400000 { 575 compatible = "fsl,ls1028a-pcie"; 576 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 577 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 578 reg-names = "regs", "config"; 579 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 580 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 581 interrupt-names = "pme", "aer"; 582 #address-cells = <3>; 583 #size-cells = <2>; 584 device_type = "pci"; 585 dma-coherent; 586 num-viewport = <8>; 587 bus-range = <0x0 0xff>; 588 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 589 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 590 msi-parent = <&its>; 591 #interrupt-cells = <1>; 592 interrupt-map-mask = <0 0 0 7>; 593 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 594 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 595 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 596 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 597 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 598 status = "disabled"; 599 }; 600 601 pcie2: pcie@3500000 { 602 compatible = "fsl,ls1028a-pcie"; 603 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 604 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 605 reg-names = "regs", "config"; 606 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 608 interrupt-names = "pme", "aer"; 609 #address-cells = <3>; 610 #size-cells = <2>; 611 device_type = "pci"; 612 dma-coherent; 613 num-viewport = <8>; 614 bus-range = <0x0 0xff>; 615 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 616 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 617 msi-parent = <&its>; 618 #interrupt-cells = <1>; 619 interrupt-map-mask = <0 0 0 7>; 620 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 621 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 622 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 623 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 624 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 625 status = "disabled"; 626 }; 627 628 smmu: iommu@5000000 { 629 compatible = "arm,mmu-500"; 630 reg = <0 0x5000000 0 0x800000>; 631 #global-interrupts = <8>; 632 #iommu-cells = <1>; 633 stream-match-mask = <0x7c00>; 634 /* global secure fault */ 635 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 636 /* combined secure interrupt */ 637 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 638 /* global non-secure fault */ 639 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 640 /* combined non-secure interrupt */ 641 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 642 /* performance counter interrupts 0-7 */ 643 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 645 /* per context interrupt, 64 interrupts */ 646 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 678 }; 679 680 crypto: crypto@8000000 { 681 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 682 fsl,sec-era = <10>; 683 #address-cells = <1>; 684 #size-cells = <1>; 685 ranges = <0x0 0x00 0x8000000 0x100000>; 686 reg = <0x00 0x8000000 0x0 0x100000>; 687 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 688 dma-coherent; 689 690 sec_jr0: jr@10000 { 691 compatible = "fsl,sec-v5.0-job-ring", 692 "fsl,sec-v4.0-job-ring"; 693 reg = <0x10000 0x10000>; 694 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 695 }; 696 697 sec_jr1: jr@20000 { 698 compatible = "fsl,sec-v5.0-job-ring", 699 "fsl,sec-v4.0-job-ring"; 700 reg = <0x20000 0x10000>; 701 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 702 }; 703 704 sec_jr2: jr@30000 { 705 compatible = "fsl,sec-v5.0-job-ring", 706 "fsl,sec-v4.0-job-ring"; 707 reg = <0x30000 0x10000>; 708 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 709 }; 710 711 sec_jr3: jr@40000 { 712 compatible = "fsl,sec-v5.0-job-ring", 713 "fsl,sec-v4.0-job-ring"; 714 reg = <0x40000 0x10000>; 715 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 716 }; 717 }; 718 719 qdma: dma-controller@8380000 { 720 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 721 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 722 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 723 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 724 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 729 interrupt-names = "qdma-error", "qdma-queue0", 730 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 731 dma-channels = <8>; 732 block-number = <1>; 733 block-offset = <0x10000>; 734 fsl,dma-queues = <2>; 735 status-sizes = <64>; 736 queue-sizes = <64 64>; 737 }; 738 739 cluster1_core0_watchdog: watchdog@c000000 { 740 compatible = "arm,sp805", "arm,primecell"; 741 reg = <0x0 0xc000000 0x0 0x1000>; 742 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 743 clock-names = "wdog_clk", "apb_pclk"; 744 }; 745 746 cluster1_core1_watchdog: watchdog@c010000 { 747 compatible = "arm,sp805", "arm,primecell"; 748 reg = <0x0 0xc010000 0x0 0x1000>; 749 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 750 clock-names = "wdog_clk", "apb_pclk"; 751 }; 752 753 sai1: audio-controller@f100000 { 754 #sound-dai-cells = <0>; 755 compatible = "fsl,vf610-sai"; 756 reg = <0x0 0xf100000 0x0 0x10000>; 757 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 759 <&clockgen 4 1>, <&clockgen 4 1>; 760 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 761 dma-names = "tx", "rx"; 762 dmas = <&edma0 1 4>, 763 <&edma0 1 3>; 764 fsl,sai-asynchronous; 765 status = "disabled"; 766 }; 767 768 sai2: audio-controller@f110000 { 769 #sound-dai-cells = <0>; 770 compatible = "fsl,vf610-sai"; 771 reg = <0x0 0xf110000 0x0 0x10000>; 772 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 774 <&clockgen 4 1>, <&clockgen 4 1>; 775 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 776 dma-names = "tx", "rx"; 777 dmas = <&edma0 1 6>, 778 <&edma0 1 5>; 779 fsl,sai-asynchronous; 780 status = "disabled"; 781 }; 782 783 sai3: audio-controller@f120000 { 784 #sound-dai-cells = <0>; 785 compatible = "fsl,vf610-sai"; 786 reg = <0x0 0xf120000 0x0 0x10000>; 787 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 789 <&clockgen 4 1>, <&clockgen 4 1>; 790 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 791 dma-names = "tx", "rx"; 792 dmas = <&edma0 1 8>, 793 <&edma0 1 7>; 794 fsl,sai-asynchronous; 795 status = "disabled"; 796 }; 797 798 sai4: audio-controller@f130000 { 799 #sound-dai-cells = <0>; 800 compatible = "fsl,vf610-sai"; 801 reg = <0x0 0xf130000 0x0 0x10000>; 802 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 804 <&clockgen 4 1>, <&clockgen 4 1>; 805 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 806 dma-names = "tx", "rx"; 807 dmas = <&edma0 1 10>, 808 <&edma0 1 9>; 809 fsl,sai-asynchronous; 810 status = "disabled"; 811 }; 812 813 sai5: audio-controller@f140000 { 814 #sound-dai-cells = <0>; 815 compatible = "fsl,vf610-sai"; 816 reg = <0x0 0xf140000 0x0 0x10000>; 817 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 819 <&clockgen 4 1>, <&clockgen 4 1>; 820 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 821 dma-names = "tx", "rx"; 822 dmas = <&edma0 1 12>, 823 <&edma0 1 11>; 824 fsl,sai-asynchronous; 825 status = "disabled"; 826 }; 827 828 sai6: audio-controller@f150000 { 829 #sound-dai-cells = <0>; 830 compatible = "fsl,vf610-sai"; 831 reg = <0x0 0xf150000 0x0 0x10000>; 832 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 834 <&clockgen 4 1>, <&clockgen 4 1>; 835 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 836 dma-names = "tx", "rx"; 837 dmas = <&edma0 1 14>, 838 <&edma0 1 13>; 839 fsl,sai-asynchronous; 840 status = "disabled"; 841 }; 842 843 tmu: tmu@1f80000 { 844 compatible = "fsl,qoriq-tmu"; 845 reg = <0x0 0x1f80000 0x0 0x10000>; 846 interrupts = <0 23 0x4>; 847 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 848 fsl,tmu-calibration = <0x00000000 0x00000024 849 0x00000001 0x0000002b 850 0x00000002 0x00000031 851 0x00000003 0x00000038 852 0x00000004 0x0000003f 853 0x00000005 0x00000045 854 0x00000006 0x0000004c 855 0x00000007 0x00000053 856 0x00000008 0x00000059 857 0x00000009 0x00000060 858 0x0000000a 0x00000066 859 0x0000000b 0x0000006d 860 861 0x00010000 0x0000001c 862 0x00010001 0x00000024 863 0x00010002 0x0000002c 864 0x00010003 0x00000035 865 0x00010004 0x0000003d 866 0x00010005 0x00000045 867 0x00010006 0x0000004d 868 0x00010007 0x00000055 869 0x00010008 0x0000005e 870 0x00010009 0x00000066 871 0x0001000a 0x0000006e 872 873 0x00020000 0x00000018 874 0x00020001 0x00000022 875 0x00020002 0x0000002d 876 0x00020003 0x00000038 877 0x00020004 0x00000043 878 0x00020005 0x0000004d 879 0x00020006 0x00000058 880 0x00020007 0x00000063 881 0x00020008 0x0000006e 882 883 0x00030000 0x00000010 884 0x00030001 0x0000001c 885 0x00030002 0x00000029 886 0x00030003 0x00000036 887 0x00030004 0x00000042 888 0x00030005 0x0000004f 889 0x00030006 0x0000005b 890 0x00030007 0x00000068>; 891 little-endian; 892 #thermal-sensor-cells = <1>; 893 }; 894 895 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 896 compatible = "pci-host-ecam-generic"; 897 reg = <0x01 0xf0000000 0x0 0x100000>; 898 #address-cells = <3>; 899 #size-cells = <2>; 900 msi-parent = <&its>; 901 device_type = "pci"; 902 bus-range = <0x0 0x0>; 903 dma-coherent; 904 msi-map = <0 &its 0x17 0xe>; 905 iommu-map = <0 &smmu 0x17 0xe>; 906 /* PF0-6 BAR0 - non-prefetchable memory */ 907 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 908 /* PF0-6 BAR2 - prefetchable memory */ 909 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 910 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 911 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 912 /* PF0: VF0-1 BAR2 - prefetchable memory */ 913 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 914 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 915 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 916 /* PF1: VF0-1 BAR2 - prefetchable memory */ 917 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 918 /* BAR4 (PF5) - non-prefetchable memory */ 919 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; 920 921 enetc_port0: ethernet@0,0 { 922 compatible = "fsl,enetc"; 923 reg = <0x000000 0 0 0 0>; 924 status = "disabled"; 925 }; 926 927 enetc_port1: ethernet@0,1 { 928 compatible = "fsl,enetc"; 929 reg = <0x000100 0 0 0 0>; 930 status = "disabled"; 931 }; 932 933 enetc_port2: ethernet@0,2 { 934 compatible = "fsl,enetc"; 935 reg = <0x000200 0 0 0 0>; 936 phy-mode = "internal"; 937 status = "disabled"; 938 939 fixed-link { 940 speed = <1000>; 941 full-duplex; 942 }; 943 }; 944 945 enetc_mdio_pf3: mdio@0,3 { 946 compatible = "fsl,enetc-mdio"; 947 reg = <0x000300 0 0 0 0>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 }; 951 952 ethernet@0,4 { 953 compatible = "fsl,enetc-ptp"; 954 reg = <0x000400 0 0 0 0>; 955 clocks = <&clockgen 2 3>; 956 little-endian; 957 fsl,extts-fifo; 958 }; 959 960 mscc_felix: ethernet-switch@0,5 { 961 reg = <0x000500 0 0 0 0>; 962 /* IEP INT_B */ 963 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 964 status = "disabled"; 965 966 ports { 967 #address-cells = <1>; 968 #size-cells = <0>; 969 970 /* External ports */ 971 mscc_felix_port0: port@0 { 972 reg = <0>; 973 status = "disabled"; 974 }; 975 976 mscc_felix_port1: port@1 { 977 reg = <1>; 978 status = "disabled"; 979 }; 980 981 mscc_felix_port2: port@2 { 982 reg = <2>; 983 status = "disabled"; 984 }; 985 986 mscc_felix_port3: port@3 { 987 reg = <3>; 988 status = "disabled"; 989 }; 990 991 /* Internal ports */ 992 mscc_felix_port4: port@4 { 993 reg = <4>; 994 phy-mode = "internal"; 995 status = "disabled"; 996 997 fixed-link { 998 speed = <2500>; 999 full-duplex; 1000 }; 1001 }; 1002 1003 mscc_felix_port5: port@5 { 1004 reg = <5>; 1005 phy-mode = "internal"; 1006 status = "disabled"; 1007 1008 fixed-link { 1009 speed = <1000>; 1010 full-duplex; 1011 }; 1012 }; 1013 }; 1014 }; 1015 1016 enetc_port3: ethernet@0,6 { 1017 compatible = "fsl,enetc"; 1018 reg = <0x000600 0 0 0 0>; 1019 phy-mode = "internal"; 1020 status = "disabled"; 1021 1022 fixed-link { 1023 speed = <1000>; 1024 full-duplex; 1025 }; 1026 }; 1027 }; 1028 1029 rcpm: power-controller@1e34040 { 1030 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1031 reg = <0x0 0x1e34040 0x0 0x1c>; 1032 #fsl,rcpm-wakeup-cells = <7>; 1033 little-endian; 1034 }; 1035 1036 ftm_alarm0: timer@2800000 { 1037 compatible = "fsl,ls1028a-ftm-alarm"; 1038 reg = <0x0 0x2800000 0x0 0x10000>; 1039 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1040 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1041 }; 1042 }; 1043 1044 malidp0: display@f080000 { 1045 compatible = "arm,mali-dp500"; 1046 reg = <0x0 0xf080000 0x0 0x10000>; 1047 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 1048 <0 223 IRQ_TYPE_LEVEL_HIGH>; 1049 interrupt-names = "DE", "SE"; 1050 clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, 1051 <&clockgen 2 2>; 1052 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 1053 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 1054 arm,malidp-arqos-value = <0xd000d000>; 1055 1056 port { 1057 dp0_out: endpoint { 1058 1059 }; 1060 }; 1061 }; 1062}; 1063