1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-aoss-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/reset/qcom,sdm845-aoss.h> 21#include <dt-bindings/reset/qcom,sdm845-pdc.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 spi0 = &spi0; 47 spi1 = &spi1; 48 spi3 = &spi3; 49 spi5 = &spi5; 50 spi6 = &spi6; 51 spi8 = &spi8; 52 spi10 = &spi10; 53 spi11 = &spi11; 54 }; 55 56 clocks { 57 xo_board: xo-board { 58 compatible = "fixed-clock"; 59 clock-frequency = <38400000>; 60 #clock-cells = <0>; 61 }; 62 63 sleep_clk: sleep-clk { 64 compatible = "fixed-clock"; 65 clock-frequency = <32764>; 66 #clock-cells = <0>; 67 }; 68 }; 69 70 reserved_memory: reserved-memory { 71 #address-cells = <2>; 72 #size-cells = <2>; 73 ranges; 74 75 hyp_mem: memory@80000000 { 76 reg = <0x0 0x80000000 0x0 0x600000>; 77 no-map; 78 }; 79 80 xbl_mem: memory@80600000 { 81 reg = <0x0 0x80600000 0x0 0x200000>; 82 no-map; 83 }; 84 85 aop_mem: memory@80800000 { 86 reg = <0x0 0x80800000 0x0 0x20000>; 87 no-map; 88 }; 89 90 aop_cmd_db_mem: memory@80820000 { 91 reg = <0x0 0x80820000 0x0 0x20000>; 92 compatible = "qcom,cmd-db"; 93 no-map; 94 }; 95 96 sec_apps_mem: memory@808ff000 { 97 reg = <0x0 0x808ff000 0x0 0x1000>; 98 no-map; 99 }; 100 101 smem_mem: memory@80900000 { 102 reg = <0x0 0x80900000 0x0 0x200000>; 103 no-map; 104 }; 105 106 tz_mem: memory@80b00000 { 107 reg = <0x0 0x80b00000 0x0 0x3900000>; 108 no-map; 109 }; 110 111 rmtfs_mem: memory@84400000 { 112 compatible = "qcom,rmtfs-mem"; 113 reg = <0x0 0x84400000 0x0 0x200000>; 114 no-map; 115 116 qcom,client-id = <1>; 117 qcom,vmid = <15>; 118 }; 119 }; 120 121 cpus { 122 #address-cells = <2>; 123 #size-cells = <0>; 124 125 CPU0: cpu@0 { 126 device_type = "cpu"; 127 compatible = "qcom,kryo468"; 128 reg = <0x0 0x0>; 129 enable-method = "psci"; 130 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 131 &LITTLE_CPU_SLEEP_1 132 &CLUSTER_SLEEP_0>; 133 capacity-dmips-mhz = <1024>; 134 dynamic-power-coefficient = <100>; 135 operating-points-v2 = <&cpu0_opp_table>; 136 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 137 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 138 next-level-cache = <&L2_0>; 139 #cooling-cells = <2>; 140 qcom,freq-domain = <&cpufreq_hw 0>; 141 L2_0: l2-cache { 142 compatible = "cache"; 143 next-level-cache = <&L3_0>; 144 L3_0: l3-cache { 145 compatible = "cache"; 146 }; 147 }; 148 }; 149 150 CPU1: cpu@100 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo468"; 153 reg = <0x0 0x100>; 154 enable-method = "psci"; 155 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 156 &LITTLE_CPU_SLEEP_1 157 &CLUSTER_SLEEP_0>; 158 capacity-dmips-mhz = <1024>; 159 dynamic-power-coefficient = <100>; 160 next-level-cache = <&L2_100>; 161 operating-points-v2 = <&cpu0_opp_table>; 162 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 163 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 164 #cooling-cells = <2>; 165 qcom,freq-domain = <&cpufreq_hw 0>; 166 L2_100: l2-cache { 167 compatible = "cache"; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU2: cpu@200 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo468"; 175 reg = <0x0 0x200>; 176 enable-method = "psci"; 177 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 178 &LITTLE_CPU_SLEEP_1 179 &CLUSTER_SLEEP_0>; 180 capacity-dmips-mhz = <1024>; 181 dynamic-power-coefficient = <100>; 182 next-level-cache = <&L2_200>; 183 operating-points-v2 = <&cpu0_opp_table>; 184 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 185 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 186 #cooling-cells = <2>; 187 qcom,freq-domain = <&cpufreq_hw 0>; 188 L2_200: l2-cache { 189 compatible = "cache"; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU3: cpu@300 { 195 device_type = "cpu"; 196 compatible = "qcom,kryo468"; 197 reg = <0x0 0x300>; 198 enable-method = "psci"; 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 200 &LITTLE_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <100>; 204 next-level-cache = <&L2_300>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 207 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 208 #cooling-cells = <2>; 209 qcom,freq-domain = <&cpufreq_hw 0>; 210 L2_300: l2-cache { 211 compatible = "cache"; 212 next-level-cache = <&L3_0>; 213 }; 214 }; 215 216 CPU4: cpu@400 { 217 device_type = "cpu"; 218 compatible = "qcom,kryo468"; 219 reg = <0x0 0x400>; 220 enable-method = "psci"; 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 222 &LITTLE_CPU_SLEEP_1 223 &CLUSTER_SLEEP_0>; 224 capacity-dmips-mhz = <1024>; 225 dynamic-power-coefficient = <100>; 226 next-level-cache = <&L2_400>; 227 operating-points-v2 = <&cpu0_opp_table>; 228 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 230 #cooling-cells = <2>; 231 qcom,freq-domain = <&cpufreq_hw 0>; 232 L2_400: l2-cache { 233 compatible = "cache"; 234 next-level-cache = <&L3_0>; 235 }; 236 }; 237 238 CPU5: cpu@500 { 239 device_type = "cpu"; 240 compatible = "qcom,kryo468"; 241 reg = <0x0 0x500>; 242 enable-method = "psci"; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246 capacity-dmips-mhz = <1024>; 247 dynamic-power-coefficient = <100>; 248 next-level-cache = <&L2_500>; 249 operating-points-v2 = <&cpu0_opp_table>; 250 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 251 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 252 #cooling-cells = <2>; 253 qcom,freq-domain = <&cpufreq_hw 0>; 254 L2_500: l2-cache { 255 compatible = "cache"; 256 next-level-cache = <&L3_0>; 257 }; 258 }; 259 260 CPU6: cpu@600 { 261 device_type = "cpu"; 262 compatible = "qcom,kryo468"; 263 reg = <0x0 0x600>; 264 enable-method = "psci"; 265 cpu-idle-states = <&BIG_CPU_SLEEP_0 266 &BIG_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268 capacity-dmips-mhz = <1740>; 269 dynamic-power-coefficient = <405>; 270 next-level-cache = <&L2_600>; 271 operating-points-v2 = <&cpu6_opp_table>; 272 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 273 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 274 #cooling-cells = <2>; 275 qcom,freq-domain = <&cpufreq_hw 1>; 276 L2_600: l2-cache { 277 compatible = "cache"; 278 next-level-cache = <&L3_0>; 279 }; 280 }; 281 282 CPU7: cpu@700 { 283 device_type = "cpu"; 284 compatible = "qcom,kryo468"; 285 reg = <0x0 0x700>; 286 enable-method = "psci"; 287 cpu-idle-states = <&BIG_CPU_SLEEP_0 288 &BIG_CPU_SLEEP_1 289 &CLUSTER_SLEEP_0>; 290 capacity-dmips-mhz = <1740>; 291 dynamic-power-coefficient = <405>; 292 next-level-cache = <&L2_700>; 293 operating-points-v2 = <&cpu6_opp_table>; 294 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 295 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 296 #cooling-cells = <2>; 297 qcom,freq-domain = <&cpufreq_hw 1>; 298 L2_700: l2-cache { 299 compatible = "cache"; 300 next-level-cache = <&L3_0>; 301 }; 302 }; 303 304 cpu-map { 305 cluster0 { 306 core0 { 307 cpu = <&CPU0>; 308 }; 309 310 core1 { 311 cpu = <&CPU1>; 312 }; 313 314 core2 { 315 cpu = <&CPU2>; 316 }; 317 318 core3 { 319 cpu = <&CPU3>; 320 }; 321 322 core4 { 323 cpu = <&CPU4>; 324 }; 325 326 core5 { 327 cpu = <&CPU5>; 328 }; 329 330 core6 { 331 cpu = <&CPU6>; 332 }; 333 334 core7 { 335 cpu = <&CPU7>; 336 }; 337 }; 338 }; 339 340 idle-states { 341 entry-method = "psci"; 342 343 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 344 compatible = "arm,idle-state"; 345 idle-state-name = "little-power-down"; 346 arm,psci-suspend-param = <0x40000003>; 347 entry-latency-us = <549>; 348 exit-latency-us = <901>; 349 min-residency-us = <1774>; 350 local-timer-stop; 351 }; 352 353 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 354 compatible = "arm,idle-state"; 355 idle-state-name = "little-rail-power-down"; 356 arm,psci-suspend-param = <0x40000004>; 357 entry-latency-us = <702>; 358 exit-latency-us = <915>; 359 min-residency-us = <4001>; 360 local-timer-stop; 361 }; 362 363 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 364 compatible = "arm,idle-state"; 365 idle-state-name = "big-power-down"; 366 arm,psci-suspend-param = <0x40000003>; 367 entry-latency-us = <523>; 368 exit-latency-us = <1244>; 369 min-residency-us = <2207>; 370 local-timer-stop; 371 }; 372 373 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 374 compatible = "arm,idle-state"; 375 idle-state-name = "big-rail-power-down"; 376 arm,psci-suspend-param = <0x40000004>; 377 entry-latency-us = <526>; 378 exit-latency-us = <1854>; 379 min-residency-us = <5555>; 380 local-timer-stop; 381 }; 382 383 CLUSTER_SLEEP_0: cluster-sleep-0 { 384 compatible = "arm,idle-state"; 385 idle-state-name = "cluster-power-down"; 386 arm,psci-suspend-param = <0x40003444>; 387 entry-latency-us = <3263>; 388 exit-latency-us = <6562>; 389 min-residency-us = <9926>; 390 local-timer-stop; 391 }; 392 }; 393 }; 394 395 cpu0_opp_table: cpu0_opp_table { 396 compatible = "operating-points-v2"; 397 opp-shared; 398 399 cpu0_opp1: opp-300000000 { 400 opp-hz = /bits/ 64 <300000000>; 401 opp-peak-kBps = <1200000 4800000>; 402 }; 403 404 cpu0_opp2: opp-576000000 { 405 opp-hz = /bits/ 64 <576000000>; 406 opp-peak-kBps = <1200000 4800000>; 407 }; 408 409 cpu0_opp3: opp-768000000 { 410 opp-hz = /bits/ 64 <768000000>; 411 opp-peak-kBps = <1200000 4800000>; 412 }; 413 414 cpu0_opp4: opp-1017600000 { 415 opp-hz = /bits/ 64 <1017600000>; 416 opp-peak-kBps = <1804000 8908800>; 417 }; 418 419 cpu0_opp5: opp-1248000000 { 420 opp-hz = /bits/ 64 <1248000000>; 421 opp-peak-kBps = <2188000 12902400>; 422 }; 423 424 cpu0_opp6: opp-1324800000 { 425 opp-hz = /bits/ 64 <1324800000>; 426 opp-peak-kBps = <2188000 12902400>; 427 }; 428 429 cpu0_opp7: opp-1516800000 { 430 opp-hz = /bits/ 64 <1516800000>; 431 opp-peak-kBps = <3072000 15052800>; 432 }; 433 434 cpu0_opp8: opp-1612800000 { 435 opp-hz = /bits/ 64 <1612800000>; 436 opp-peak-kBps = <3072000 15052800>; 437 }; 438 439 cpu0_opp9: opp-1708800000 { 440 opp-hz = /bits/ 64 <1708800000>; 441 opp-peak-kBps = <3072000 15052800>; 442 }; 443 444 cpu0_opp10: opp-1804800000 { 445 opp-hz = /bits/ 64 <1804800000>; 446 opp-peak-kBps = <4068000 22425600>; 447 }; 448 }; 449 450 cpu6_opp_table: cpu6_opp_table { 451 compatible = "operating-points-v2"; 452 opp-shared; 453 454 cpu6_opp1: opp-300000000 { 455 opp-hz = /bits/ 64 <300000000>; 456 opp-peak-kBps = <2188000 8908800>; 457 }; 458 459 cpu6_opp2: opp-652800000 { 460 opp-hz = /bits/ 64 <652800000>; 461 opp-peak-kBps = <2188000 8908800>; 462 }; 463 464 cpu6_opp3: opp-825600000 { 465 opp-hz = /bits/ 64 <825600000>; 466 opp-peak-kBps = <2188000 8908800>; 467 }; 468 469 cpu6_opp4: opp-979200000 { 470 opp-hz = /bits/ 64 <979200000>; 471 opp-peak-kBps = <2188000 8908800>; 472 }; 473 474 cpu6_opp5: opp-1113600000 { 475 opp-hz = /bits/ 64 <1113600000>; 476 opp-peak-kBps = <2188000 8908800>; 477 }; 478 479 cpu6_opp6: opp-1267200000 { 480 opp-hz = /bits/ 64 <1267200000>; 481 opp-peak-kBps = <4068000 12902400>; 482 }; 483 484 cpu6_opp7: opp-1555200000 { 485 opp-hz = /bits/ 64 <1555200000>; 486 opp-peak-kBps = <4068000 15052800>; 487 }; 488 489 cpu6_opp8: opp-1708800000 { 490 opp-hz = /bits/ 64 <1708800000>; 491 opp-peak-kBps = <6220000 19353600>; 492 }; 493 494 cpu6_opp9: opp-1843200000 { 495 opp-hz = /bits/ 64 <1843200000>; 496 opp-peak-kBps = <6220000 19353600>; 497 }; 498 499 cpu6_opp10: opp-1900800000 { 500 opp-hz = /bits/ 64 <1900800000>; 501 opp-peak-kBps = <6220000 22425600>; 502 }; 503 504 cpu6_opp11: opp-1996800000 { 505 opp-hz = /bits/ 64 <1996800000>; 506 opp-peak-kBps = <6220000 22425600>; 507 }; 508 509 cpu6_opp12: opp-2112000000 { 510 opp-hz = /bits/ 64 <2112000000>; 511 opp-peak-kBps = <6220000 22425600>; 512 }; 513 514 cpu6_opp13: opp-2208000000 { 515 opp-hz = /bits/ 64 <2208000000>; 516 opp-peak-kBps = <7216000 22425600>; 517 }; 518 519 cpu6_opp14: opp-2323200000 { 520 opp-hz = /bits/ 64 <2323200000>; 521 opp-peak-kBps = <7216000 22425600>; 522 }; 523 524 cpu6_opp15: opp-2400000000 { 525 opp-hz = /bits/ 64 <2400000000>; 526 opp-peak-kBps = <8532000 23347200>; 527 }; 528 }; 529 530 memory@80000000 { 531 device_type = "memory"; 532 /* We expect the bootloader to fill in the size */ 533 reg = <0 0x80000000 0 0>; 534 }; 535 536 pmu { 537 compatible = "arm,armv8-pmuv3"; 538 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 539 }; 540 541 firmware { 542 scm { 543 compatible = "qcom,scm-sc7180", "qcom,scm"; 544 }; 545 }; 546 547 tcsr_mutex: hwlock { 548 compatible = "qcom,tcsr-mutex"; 549 syscon = <&tcsr_mutex_regs 0 0x1000>; 550 #hwlock-cells = <1>; 551 }; 552 553 smem { 554 compatible = "qcom,smem"; 555 memory-region = <&smem_mem>; 556 hwlocks = <&tcsr_mutex 3>; 557 }; 558 559 smp2p-cdsp { 560 compatible = "qcom,smp2p"; 561 qcom,smem = <94>, <432>; 562 563 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 564 565 mboxes = <&apss_shared 6>; 566 567 qcom,local-pid = <0>; 568 qcom,remote-pid = <5>; 569 570 cdsp_smp2p_out: master-kernel { 571 qcom,entry-name = "master-kernel"; 572 #qcom,smem-state-cells = <1>; 573 }; 574 575 cdsp_smp2p_in: slave-kernel { 576 qcom,entry-name = "slave-kernel"; 577 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 }; 581 }; 582 583 smp2p-lpass { 584 compatible = "qcom,smp2p"; 585 qcom,smem = <443>, <429>; 586 587 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 588 589 mboxes = <&apss_shared 10>; 590 591 qcom,local-pid = <0>; 592 qcom,remote-pid = <2>; 593 594 adsp_smp2p_out: master-kernel { 595 qcom,entry-name = "master-kernel"; 596 #qcom,smem-state-cells = <1>; 597 }; 598 599 adsp_smp2p_in: slave-kernel { 600 qcom,entry-name = "slave-kernel"; 601 602 interrupt-controller; 603 #interrupt-cells = <2>; 604 }; 605 }; 606 607 smp2p-mpss { 608 compatible = "qcom,smp2p"; 609 qcom,smem = <435>, <428>; 610 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 611 mboxes = <&apss_shared 14>; 612 qcom,local-pid = <0>; 613 qcom,remote-pid = <1>; 614 615 modem_smp2p_out: master-kernel { 616 qcom,entry-name = "master-kernel"; 617 #qcom,smem-state-cells = <1>; 618 }; 619 620 modem_smp2p_in: slave-kernel { 621 qcom,entry-name = "slave-kernel"; 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 }; 625 626 ipa_smp2p_out: ipa-ap-to-modem { 627 qcom,entry-name = "ipa"; 628 #qcom,smem-state-cells = <1>; 629 }; 630 631 ipa_smp2p_in: ipa-modem-to-ap { 632 qcom,entry-name = "ipa"; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 }; 636 }; 637 638 psci { 639 compatible = "arm,psci-1.0"; 640 method = "smc"; 641 }; 642 643 soc: soc@0 { 644 #address-cells = <2>; 645 #size-cells = <2>; 646 ranges = <0 0 0 0 0x10 0>; 647 dma-ranges = <0 0 0 0 0x10 0>; 648 compatible = "simple-bus"; 649 650 gcc: clock-controller@100000 { 651 compatible = "qcom,gcc-sc7180"; 652 reg = <0 0x00100000 0 0x1f0000>; 653 clocks = <&rpmhcc RPMH_CXO_CLK>, 654 <&rpmhcc RPMH_CXO_CLK_A>, 655 <&sleep_clk>; 656 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 657 #clock-cells = <1>; 658 #reset-cells = <1>; 659 #power-domain-cells = <1>; 660 }; 661 662 qfprom: efuse@784000 { 663 compatible = "qcom,qfprom"; 664 reg = <0 0x00784000 0 0x8ff>, 665 <0 0x00780000 0 0x7a0>, 666 <0 0x00782000 0 0x100>, 667 <0 0x00786000 0 0x1fff>; 668 669 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 670 clock-names = "core"; 671 #address-cells = <1>; 672 #size-cells = <1>; 673 674 qusb2p_hstx_trim: hstx-trim-primary@25b { 675 reg = <0x25b 0x1>; 676 bits = <1 3>; 677 }; 678 }; 679 680 sdhc_1: sdhci@7c4000 { 681 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 682 reg = <0 0x7c4000 0 0x1000>, 683 <0 0x07c5000 0 0x1000>; 684 reg-names = "hc", "cqhci"; 685 686 iommus = <&apps_smmu 0x60 0x0>; 687 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 689 interrupt-names = "hc_irq", "pwr_irq"; 690 691 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 692 <&gcc GCC_SDCC1_AHB_CLK>; 693 clock-names = "core", "iface"; 694 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 695 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 696 interconnect-names = "sdhc-ddr","cpu-sdhc"; 697 power-domains = <&rpmhpd SC7180_CX>; 698 operating-points-v2 = <&sdhc1_opp_table>; 699 700 bus-width = <8>; 701 non-removable; 702 supports-cqe; 703 704 mmc-ddr-1_8v; 705 mmc-hs200-1_8v; 706 mmc-hs400-1_8v; 707 mmc-hs400-enhanced-strobe; 708 709 status = "disabled"; 710 711 sdhc1_opp_table: sdhc1-opp-table { 712 compatible = "operating-points-v2"; 713 714 opp-100000000 { 715 opp-hz = /bits/ 64 <100000000>; 716 required-opps = <&rpmhpd_opp_low_svs>; 717 opp-peak-kBps = <100000 100000>; 718 opp-avg-kBps = <100000 50000>; 719 }; 720 721 opp-384000000 { 722 opp-hz = /bits/ 64 <384000000>; 723 required-opps = <&rpmhpd_opp_svs_l1>; 724 opp-peak-kBps = <600000 900000>; 725 opp-avg-kBps = <261438 300000>; 726 }; 727 }; 728 }; 729 730 qup_opp_table: qup-opp-table { 731 compatible = "operating-points-v2"; 732 733 opp-75000000 { 734 opp-hz = /bits/ 64 <75000000>; 735 required-opps = <&rpmhpd_opp_low_svs>; 736 }; 737 738 opp-100000000 { 739 opp-hz = /bits/ 64 <100000000>; 740 required-opps = <&rpmhpd_opp_svs>; 741 }; 742 743 opp-128000000 { 744 opp-hz = /bits/ 64 <128000000>; 745 required-opps = <&rpmhpd_opp_nom>; 746 }; 747 }; 748 749 qupv3_id_0: geniqup@8c0000 { 750 compatible = "qcom,geni-se-qup"; 751 reg = <0 0x008c0000 0 0x6000>; 752 clock-names = "m-ahb", "s-ahb"; 753 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 754 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 755 #address-cells = <2>; 756 #size-cells = <2>; 757 ranges; 758 iommus = <&apps_smmu 0x43 0x0>; 759 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>; 760 interconnect-names = "qup-core"; 761 status = "disabled"; 762 763 i2c0: i2c@880000 { 764 compatible = "qcom,geni-i2c"; 765 reg = <0 0x00880000 0 0x4000>; 766 clock-names = "se"; 767 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&qup_i2c0_default>; 770 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 774 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 775 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 776 interconnect-names = "qup-core", "qup-config", 777 "qup-memory"; 778 status = "disabled"; 779 }; 780 781 spi0: spi@880000 { 782 compatible = "qcom,geni-spi"; 783 reg = <0 0x00880000 0 0x4000>; 784 clock-names = "se"; 785 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&qup_spi0_default>; 788 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 power-domains = <&rpmhpd SC7180_CX>; 792 operating-points-v2 = <&qup_opp_table>; 793 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 794 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 795 interconnect-names = "qup-core", "qup-config"; 796 status = "disabled"; 797 }; 798 799 uart0: serial@880000 { 800 compatible = "qcom,geni-uart"; 801 reg = <0 0x00880000 0 0x4000>; 802 clock-names = "se"; 803 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 804 pinctrl-names = "default"; 805 pinctrl-0 = <&qup_uart0_default>; 806 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 807 power-domains = <&rpmhpd SC7180_CX>; 808 operating-points-v2 = <&qup_opp_table>; 809 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 810 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 811 interconnect-names = "qup-core", "qup-config"; 812 status = "disabled"; 813 }; 814 815 i2c1: i2c@884000 { 816 compatible = "qcom,geni-i2c"; 817 reg = <0 0x00884000 0 0x4000>; 818 clock-names = "se"; 819 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 820 pinctrl-names = "default"; 821 pinctrl-0 = <&qup_i2c1_default>; 822 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 826 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 827 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 828 interconnect-names = "qup-core", "qup-config", 829 "qup-memory"; 830 status = "disabled"; 831 }; 832 833 spi1: spi@884000 { 834 compatible = "qcom,geni-spi"; 835 reg = <0 0x00884000 0 0x4000>; 836 clock-names = "se"; 837 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 838 pinctrl-names = "default"; 839 pinctrl-0 = <&qup_spi1_default>; 840 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 power-domains = <&rpmhpd SC7180_CX>; 844 operating-points-v2 = <&qup_opp_table>; 845 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 846 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 847 interconnect-names = "qup-core", "qup-config"; 848 status = "disabled"; 849 }; 850 851 uart1: serial@884000 { 852 compatible = "qcom,geni-uart"; 853 reg = <0 0x00884000 0 0x4000>; 854 clock-names = "se"; 855 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 856 pinctrl-names = "default"; 857 pinctrl-0 = <&qup_uart1_default>; 858 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 859 power-domains = <&rpmhpd SC7180_CX>; 860 operating-points-v2 = <&qup_opp_table>; 861 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 862 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 863 interconnect-names = "qup-core", "qup-config"; 864 status = "disabled"; 865 }; 866 867 i2c2: i2c@888000 { 868 compatible = "qcom,geni-i2c"; 869 reg = <0 0x00888000 0 0x4000>; 870 clock-names = "se"; 871 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 872 pinctrl-names = "default"; 873 pinctrl-0 = <&qup_i2c2_default>; 874 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 878 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 879 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 880 interconnect-names = "qup-core", "qup-config", 881 "qup-memory"; 882 status = "disabled"; 883 }; 884 885 uart2: serial@888000 { 886 compatible = "qcom,geni-uart"; 887 reg = <0 0x00888000 0 0x4000>; 888 clock-names = "se"; 889 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 890 pinctrl-names = "default"; 891 pinctrl-0 = <&qup_uart2_default>; 892 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 893 power-domains = <&rpmhpd SC7180_CX>; 894 operating-points-v2 = <&qup_opp_table>; 895 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 896 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 897 interconnect-names = "qup-core", "qup-config"; 898 status = "disabled"; 899 }; 900 901 i2c3: i2c@88c000 { 902 compatible = "qcom,geni-i2c"; 903 reg = <0 0x0088c000 0 0x4000>; 904 clock-names = "se"; 905 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 906 pinctrl-names = "default"; 907 pinctrl-0 = <&qup_i2c3_default>; 908 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 912 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 913 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 914 interconnect-names = "qup-core", "qup-config", 915 "qup-memory"; 916 status = "disabled"; 917 }; 918 919 spi3: spi@88c000 { 920 compatible = "qcom,geni-spi"; 921 reg = <0 0x0088c000 0 0x4000>; 922 clock-names = "se"; 923 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <&qup_spi3_default>; 926 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 power-domains = <&rpmhpd SC7180_CX>; 930 operating-points-v2 = <&qup_opp_table>; 931 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 932 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 933 interconnect-names = "qup-core", "qup-config"; 934 status = "disabled"; 935 }; 936 937 uart3: serial@88c000 { 938 compatible = "qcom,geni-uart"; 939 reg = <0 0x0088c000 0 0x4000>; 940 clock-names = "se"; 941 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&qup_uart3_default>; 944 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 945 power-domains = <&rpmhpd SC7180_CX>; 946 operating-points-v2 = <&qup_opp_table>; 947 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 948 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 949 interconnect-names = "qup-core", "qup-config"; 950 status = "disabled"; 951 }; 952 953 i2c4: i2c@890000 { 954 compatible = "qcom,geni-i2c"; 955 reg = <0 0x00890000 0 0x4000>; 956 clock-names = "se"; 957 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&qup_i2c4_default>; 960 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 964 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 965 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 966 interconnect-names = "qup-core", "qup-config", 967 "qup-memory"; 968 status = "disabled"; 969 }; 970 971 uart4: serial@890000 { 972 compatible = "qcom,geni-uart"; 973 reg = <0 0x00890000 0 0x4000>; 974 clock-names = "se"; 975 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&qup_uart4_default>; 978 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 979 power-domains = <&rpmhpd SC7180_CX>; 980 operating-points-v2 = <&qup_opp_table>; 981 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 982 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 983 interconnect-names = "qup-core", "qup-config"; 984 status = "disabled"; 985 }; 986 987 i2c5: i2c@894000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00894000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c5_default>; 994 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 999 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1000 interconnect-names = "qup-core", "qup-config", 1001 "qup-memory"; 1002 status = "disabled"; 1003 }; 1004 1005 spi5: spi@894000 { 1006 compatible = "qcom,geni-spi"; 1007 reg = <0 0x00894000 0 0x4000>; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&qup_spi5_default>; 1012 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 power-domains = <&rpmhpd SC7180_CX>; 1016 operating-points-v2 = <&qup_opp_table>; 1017 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1018 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1019 interconnect-names = "qup-core", "qup-config"; 1020 status = "disabled"; 1021 }; 1022 1023 uart5: serial@894000 { 1024 compatible = "qcom,geni-uart"; 1025 reg = <0 0x00894000 0 0x4000>; 1026 clock-names = "se"; 1027 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&qup_uart5_default>; 1030 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1031 power-domains = <&rpmhpd SC7180_CX>; 1032 operating-points-v2 = <&qup_opp_table>; 1033 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1034 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1035 interconnect-names = "qup-core", "qup-config"; 1036 status = "disabled"; 1037 }; 1038 }; 1039 1040 qupv3_id_1: geniqup@ac0000 { 1041 compatible = "qcom,geni-se-qup"; 1042 reg = <0 0x00ac0000 0 0x6000>; 1043 clock-names = "m-ahb", "s-ahb"; 1044 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1045 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1046 #address-cells = <2>; 1047 #size-cells = <2>; 1048 ranges; 1049 iommus = <&apps_smmu 0x4c3 0x0>; 1050 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>; 1051 interconnect-names = "qup-core"; 1052 status = "disabled"; 1053 1054 i2c6: i2c@a80000 { 1055 compatible = "qcom,geni-i2c"; 1056 reg = <0 0x00a80000 0 0x4000>; 1057 clock-names = "se"; 1058 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&qup_i2c6_default>; 1061 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1065 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1066 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1067 interconnect-names = "qup-core", "qup-config", 1068 "qup-memory"; 1069 status = "disabled"; 1070 }; 1071 1072 spi6: spi@a80000 { 1073 compatible = "qcom,geni-spi"; 1074 reg = <0 0x00a80000 0 0x4000>; 1075 clock-names = "se"; 1076 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&qup_spi6_default>; 1079 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 power-domains = <&rpmhpd SC7180_CX>; 1083 operating-points-v2 = <&qup_opp_table>; 1084 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1085 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1086 interconnect-names = "qup-core", "qup-config"; 1087 status = "disabled"; 1088 }; 1089 1090 uart6: serial@a80000 { 1091 compatible = "qcom,geni-uart"; 1092 reg = <0 0x00a80000 0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_uart6_default>; 1097 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1098 power-domains = <&rpmhpd SC7180_CX>; 1099 operating-points-v2 = <&qup_opp_table>; 1100 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1101 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1102 interconnect-names = "qup-core", "qup-config"; 1103 status = "disabled"; 1104 }; 1105 1106 i2c7: i2c@a84000 { 1107 compatible = "qcom,geni-i2c"; 1108 reg = <0 0x00a84000 0 0x4000>; 1109 clock-names = "se"; 1110 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1111 pinctrl-names = "default"; 1112 pinctrl-0 = <&qup_i2c7_default>; 1113 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1117 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1118 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1119 interconnect-names = "qup-core", "qup-config", 1120 "qup-memory"; 1121 status = "disabled"; 1122 }; 1123 1124 uart7: serial@a84000 { 1125 compatible = "qcom,geni-uart"; 1126 reg = <0 0x00a84000 0 0x4000>; 1127 clock-names = "se"; 1128 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&qup_uart7_default>; 1131 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1132 power-domains = <&rpmhpd SC7180_CX>; 1133 operating-points-v2 = <&qup_opp_table>; 1134 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1135 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1136 interconnect-names = "qup-core", "qup-config"; 1137 status = "disabled"; 1138 }; 1139 1140 i2c8: i2c@a88000 { 1141 compatible = "qcom,geni-i2c"; 1142 reg = <0 0x00a88000 0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_i2c8_default>; 1147 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1151 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1152 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1153 interconnect-names = "qup-core", "qup-config", 1154 "qup-memory"; 1155 status = "disabled"; 1156 }; 1157 1158 spi8: spi@a88000 { 1159 compatible = "qcom,geni-spi"; 1160 reg = <0 0x00a88000 0 0x4000>; 1161 clock-names = "se"; 1162 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_spi8_default>; 1165 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 power-domains = <&rpmhpd SC7180_CX>; 1169 operating-points-v2 = <&qup_opp_table>; 1170 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1171 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1172 interconnect-names = "qup-core", "qup-config"; 1173 status = "disabled"; 1174 }; 1175 1176 uart8: serial@a88000 { 1177 compatible = "qcom,geni-debug-uart"; 1178 reg = <0 0x00a88000 0 0x4000>; 1179 clock-names = "se"; 1180 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&qup_uart8_default>; 1183 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1184 power-domains = <&rpmhpd SC7180_CX>; 1185 operating-points-v2 = <&qup_opp_table>; 1186 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1187 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1188 interconnect-names = "qup-core", "qup-config"; 1189 status = "disabled"; 1190 }; 1191 1192 i2c9: i2c@a8c000 { 1193 compatible = "qcom,geni-i2c"; 1194 reg = <0 0x00a8c000 0 0x4000>; 1195 clock-names = "se"; 1196 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1197 pinctrl-names = "default"; 1198 pinctrl-0 = <&qup_i2c9_default>; 1199 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1204 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1205 interconnect-names = "qup-core", "qup-config", 1206 "qup-memory"; 1207 status = "disabled"; 1208 }; 1209 1210 uart9: serial@a8c000 { 1211 compatible = "qcom,geni-uart"; 1212 reg = <0 0x00a8c000 0 0x4000>; 1213 clock-names = "se"; 1214 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&qup_uart9_default>; 1217 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1218 power-domains = <&rpmhpd SC7180_CX>; 1219 operating-points-v2 = <&qup_opp_table>; 1220 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1222 interconnect-names = "qup-core", "qup-config"; 1223 status = "disabled"; 1224 }; 1225 1226 i2c10: i2c@a90000 { 1227 compatible = "qcom,geni-i2c"; 1228 reg = <0 0x00a90000 0 0x4000>; 1229 clock-names = "se"; 1230 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&qup_i2c10_default>; 1233 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1238 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1239 interconnect-names = "qup-core", "qup-config", 1240 "qup-memory"; 1241 status = "disabled"; 1242 }; 1243 1244 spi10: spi@a90000 { 1245 compatible = "qcom,geni-spi"; 1246 reg = <0 0x00a90000 0 0x4000>; 1247 clock-names = "se"; 1248 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&qup_spi10_default>; 1251 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 power-domains = <&rpmhpd SC7180_CX>; 1255 operating-points-v2 = <&qup_opp_table>; 1256 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1257 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1258 interconnect-names = "qup-core", "qup-config"; 1259 status = "disabled"; 1260 }; 1261 1262 uart10: serial@a90000 { 1263 compatible = "qcom,geni-uart"; 1264 reg = <0 0x00a90000 0 0x4000>; 1265 clock-names = "se"; 1266 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_uart10_default>; 1269 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1270 power-domains = <&rpmhpd SC7180_CX>; 1271 operating-points-v2 = <&qup_opp_table>; 1272 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1273 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1274 interconnect-names = "qup-core", "qup-config"; 1275 status = "disabled"; 1276 }; 1277 1278 i2c11: i2c@a94000 { 1279 compatible = "qcom,geni-i2c"; 1280 reg = <0 0x00a94000 0 0x4000>; 1281 clock-names = "se"; 1282 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_i2c11_default>; 1285 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1290 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1291 interconnect-names = "qup-core", "qup-config", 1292 "qup-memory"; 1293 status = "disabled"; 1294 }; 1295 1296 spi11: spi@a94000 { 1297 compatible = "qcom,geni-spi"; 1298 reg = <0 0x00a94000 0 0x4000>; 1299 clock-names = "se"; 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&qup_spi11_default>; 1303 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 power-domains = <&rpmhpd SC7180_CX>; 1307 operating-points-v2 = <&qup_opp_table>; 1308 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1309 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1310 interconnect-names = "qup-core", "qup-config"; 1311 status = "disabled"; 1312 }; 1313 1314 uart11: serial@a94000 { 1315 compatible = "qcom,geni-uart"; 1316 reg = <0 0x00a94000 0 0x4000>; 1317 clock-names = "se"; 1318 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1319 pinctrl-names = "default"; 1320 pinctrl-0 = <&qup_uart11_default>; 1321 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1322 power-domains = <&rpmhpd SC7180_CX>; 1323 operating-points-v2 = <&qup_opp_table>; 1324 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1325 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1326 interconnect-names = "qup-core", "qup-config"; 1327 status = "disabled"; 1328 }; 1329 }; 1330 1331 config_noc: interconnect@1500000 { 1332 compatible = "qcom,sc7180-config-noc"; 1333 reg = <0 0x01500000 0 0x28000>; 1334 #interconnect-cells = <2>; 1335 qcom,bcm-voters = <&apps_bcm_voter>; 1336 }; 1337 1338 system_noc: interconnect@1620000 { 1339 compatible = "qcom,sc7180-system-noc"; 1340 reg = <0 0x01620000 0 0x17080>; 1341 #interconnect-cells = <2>; 1342 qcom,bcm-voters = <&apps_bcm_voter>; 1343 }; 1344 1345 mc_virt: interconnect@1638000 { 1346 compatible = "qcom,sc7180-mc-virt"; 1347 reg = <0 0x01638000 0 0x1000>; 1348 #interconnect-cells = <2>; 1349 qcom,bcm-voters = <&apps_bcm_voter>; 1350 }; 1351 1352 qup_virt: interconnect@1650000 { 1353 compatible = "qcom,sc7180-qup-virt"; 1354 reg = <0 0x01650000 0 0x1000>; 1355 #interconnect-cells = <2>; 1356 qcom,bcm-voters = <&apps_bcm_voter>; 1357 }; 1358 1359 aggre1_noc: interconnect@16e0000 { 1360 compatible = "qcom,sc7180-aggre1-noc"; 1361 reg = <0 0x016e0000 0 0x15080>; 1362 #interconnect-cells = <2>; 1363 qcom,bcm-voters = <&apps_bcm_voter>; 1364 }; 1365 1366 aggre2_noc: interconnect@1705000 { 1367 compatible = "qcom,sc7180-aggre2-noc"; 1368 reg = <0 0x01705000 0 0x9000>; 1369 #interconnect-cells = <2>; 1370 qcom,bcm-voters = <&apps_bcm_voter>; 1371 }; 1372 1373 compute_noc: interconnect@170e000 { 1374 compatible = "qcom,sc7180-compute-noc"; 1375 reg = <0 0x0170e000 0 0x6000>; 1376 #interconnect-cells = <2>; 1377 qcom,bcm-voters = <&apps_bcm_voter>; 1378 }; 1379 1380 mmss_noc: interconnect@1740000 { 1381 compatible = "qcom,sc7180-mmss-noc"; 1382 reg = <0 0x01740000 0 0x1c100>; 1383 #interconnect-cells = <2>; 1384 qcom,bcm-voters = <&apps_bcm_voter>; 1385 }; 1386 1387 ipa_virt: interconnect@1e00000 { 1388 compatible = "qcom,sc7180-ipa-virt"; 1389 reg = <0 0x01e00000 0 0x1000>; 1390 #interconnect-cells = <2>; 1391 qcom,bcm-voters = <&apps_bcm_voter>; 1392 }; 1393 1394 ipa: ipa@1e40000 { 1395 compatible = "qcom,sc7180-ipa"; 1396 1397 iommus = <&apps_smmu 0x440 0x0>, 1398 <&apps_smmu 0x442 0x0>; 1399 reg = <0 0x1e40000 0 0x7000>, 1400 <0 0x1e47000 0 0x2000>, 1401 <0 0x1e04000 0 0x2c000>; 1402 reg-names = "ipa-reg", 1403 "ipa-shared", 1404 "gsi"; 1405 1406 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, 1407 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 1408 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1409 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1410 interrupt-names = "ipa", 1411 "gsi", 1412 "ipa-clock-query", 1413 "ipa-setup-ready"; 1414 1415 clocks = <&rpmhcc RPMH_IPA_CLK>; 1416 clock-names = "core"; 1417 1418 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1419 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1420 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1421 interconnect-names = "memory", 1422 "imem", 1423 "config"; 1424 1425 qcom,smem-states = <&ipa_smp2p_out 0>, 1426 <&ipa_smp2p_out 1>; 1427 qcom,smem-state-names = "ipa-clock-enabled-valid", 1428 "ipa-clock-enabled"; 1429 1430 modem-remoteproc = <&remoteproc_mpss>; 1431 1432 status = "disabled"; 1433 }; 1434 1435 tcsr_mutex_regs: syscon@1f40000 { 1436 compatible = "syscon"; 1437 reg = <0 0x01f40000 0 0x40000>; 1438 }; 1439 1440 tcsr_regs: syscon@1fc0000 { 1441 compatible = "syscon"; 1442 reg = <0 0x01fc0000 0 0x40000>; 1443 }; 1444 1445 tlmm: pinctrl@3500000 { 1446 compatible = "qcom,sc7180-pinctrl"; 1447 reg = <0 0x03500000 0 0x300000>, 1448 <0 0x03900000 0 0x300000>, 1449 <0 0x03d00000 0 0x300000>; 1450 reg-names = "west", "north", "south"; 1451 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1452 gpio-controller; 1453 #gpio-cells = <2>; 1454 interrupt-controller; 1455 #interrupt-cells = <2>; 1456 gpio-ranges = <&tlmm 0 0 120>; 1457 wakeup-parent = <&pdc>; 1458 1459 dp_hot_plug_det: dp-hot-plug-det { 1460 pinmux { 1461 pins = "gpio117"; 1462 function = "dp_hot"; 1463 }; 1464 1465 pinconf { 1466 pins = "gpio117"; 1467 bias-disable; 1468 input-enable; 1469 }; 1470 }; 1471 1472 qspi_clk: qspi-clk { 1473 pinmux { 1474 pins = "gpio63"; 1475 function = "qspi_clk"; 1476 }; 1477 }; 1478 1479 qspi_cs0: qspi-cs0 { 1480 pinmux { 1481 pins = "gpio68"; 1482 function = "qspi_cs"; 1483 }; 1484 }; 1485 1486 qspi_cs1: qspi-cs1 { 1487 pinmux { 1488 pins = "gpio72"; 1489 function = "qspi_cs"; 1490 }; 1491 }; 1492 1493 qspi_data01: qspi-data01 { 1494 pinmux-data { 1495 pins = "gpio64", "gpio65"; 1496 function = "qspi_data"; 1497 }; 1498 }; 1499 1500 qspi_data12: qspi-data12 { 1501 pinmux-data { 1502 pins = "gpio66", "gpio67"; 1503 function = "qspi_data"; 1504 }; 1505 }; 1506 1507 qup_i2c0_default: qup-i2c0-default { 1508 pinmux { 1509 pins = "gpio34", "gpio35"; 1510 function = "qup00"; 1511 }; 1512 }; 1513 1514 qup_i2c1_default: qup-i2c1-default { 1515 pinmux { 1516 pins = "gpio0", "gpio1"; 1517 function = "qup01"; 1518 }; 1519 }; 1520 1521 qup_i2c2_default: qup-i2c2-default { 1522 pinmux { 1523 pins = "gpio15", "gpio16"; 1524 function = "qup02_i2c"; 1525 }; 1526 }; 1527 1528 qup_i2c3_default: qup-i2c3-default { 1529 pinmux { 1530 pins = "gpio38", "gpio39"; 1531 function = "qup03"; 1532 }; 1533 }; 1534 1535 qup_i2c4_default: qup-i2c4-default { 1536 pinmux { 1537 pins = "gpio115", "gpio116"; 1538 function = "qup04_i2c"; 1539 }; 1540 }; 1541 1542 qup_i2c5_default: qup-i2c5-default { 1543 pinmux { 1544 pins = "gpio25", "gpio26"; 1545 function = "qup05"; 1546 }; 1547 }; 1548 1549 qup_i2c6_default: qup-i2c6-default { 1550 pinmux { 1551 pins = "gpio59", "gpio60"; 1552 function = "qup10"; 1553 }; 1554 }; 1555 1556 qup_i2c7_default: qup-i2c7-default { 1557 pinmux { 1558 pins = "gpio6", "gpio7"; 1559 function = "qup11_i2c"; 1560 }; 1561 }; 1562 1563 qup_i2c8_default: qup-i2c8-default { 1564 pinmux { 1565 pins = "gpio42", "gpio43"; 1566 function = "qup12"; 1567 }; 1568 }; 1569 1570 qup_i2c9_default: qup-i2c9-default { 1571 pinmux { 1572 pins = "gpio46", "gpio47"; 1573 function = "qup13_i2c"; 1574 }; 1575 }; 1576 1577 qup_i2c10_default: qup-i2c10-default { 1578 pinmux { 1579 pins = "gpio86", "gpio87"; 1580 function = "qup14"; 1581 }; 1582 }; 1583 1584 qup_i2c11_default: qup-i2c11-default { 1585 pinmux { 1586 pins = "gpio53", "gpio54"; 1587 function = "qup15"; 1588 }; 1589 }; 1590 1591 qup_spi0_default: qup-spi0-default { 1592 pinmux { 1593 pins = "gpio34", "gpio35", 1594 "gpio36", "gpio37"; 1595 function = "qup00"; 1596 }; 1597 }; 1598 1599 qup_spi1_default: qup-spi1-default { 1600 pinmux { 1601 pins = "gpio0", "gpio1", 1602 "gpio2", "gpio3"; 1603 function = "qup01"; 1604 }; 1605 }; 1606 1607 qup_spi3_default: qup-spi3-default { 1608 pinmux { 1609 pins = "gpio38", "gpio39", 1610 "gpio40", "gpio41"; 1611 function = "qup03"; 1612 }; 1613 }; 1614 1615 qup_spi5_default: qup-spi5-default { 1616 pinmux { 1617 pins = "gpio25", "gpio26", 1618 "gpio27", "gpio28"; 1619 function = "qup05"; 1620 }; 1621 }; 1622 1623 qup_spi6_default: qup-spi6-default { 1624 pinmux { 1625 pins = "gpio59", "gpio60", 1626 "gpio61", "gpio62"; 1627 function = "qup10"; 1628 }; 1629 }; 1630 1631 qup_spi8_default: qup-spi8-default { 1632 pinmux { 1633 pins = "gpio42", "gpio43", 1634 "gpio44", "gpio45"; 1635 function = "qup12"; 1636 }; 1637 }; 1638 1639 qup_spi10_default: qup-spi10-default { 1640 pinmux { 1641 pins = "gpio86", "gpio87", 1642 "gpio88", "gpio89"; 1643 function = "qup14"; 1644 }; 1645 }; 1646 1647 qup_spi11_default: qup-spi11-default { 1648 pinmux { 1649 pins = "gpio53", "gpio54", 1650 "gpio55", "gpio56"; 1651 function = "qup15"; 1652 }; 1653 }; 1654 1655 qup_uart0_default: qup-uart0-default { 1656 pinmux { 1657 pins = "gpio34", "gpio35", 1658 "gpio36", "gpio37"; 1659 function = "qup00"; 1660 }; 1661 }; 1662 1663 qup_uart1_default: qup-uart1-default { 1664 pinmux { 1665 pins = "gpio0", "gpio1", 1666 "gpio2", "gpio3"; 1667 function = "qup01"; 1668 }; 1669 }; 1670 1671 qup_uart2_default: qup-uart2-default { 1672 pinmux { 1673 pins = "gpio15", "gpio16"; 1674 function = "qup02_uart"; 1675 }; 1676 }; 1677 1678 qup_uart3_default: qup-uart3-default { 1679 pinmux { 1680 pins = "gpio38", "gpio39", 1681 "gpio40", "gpio41"; 1682 function = "qup03"; 1683 }; 1684 }; 1685 1686 qup_uart4_default: qup-uart4-default { 1687 pinmux { 1688 pins = "gpio115", "gpio116"; 1689 function = "qup04_uart"; 1690 }; 1691 }; 1692 1693 qup_uart5_default: qup-uart5-default { 1694 pinmux { 1695 pins = "gpio25", "gpio26", 1696 "gpio27", "gpio28"; 1697 function = "qup05"; 1698 }; 1699 }; 1700 1701 qup_uart6_default: qup-uart6-default { 1702 pinmux { 1703 pins = "gpio59", "gpio60", 1704 "gpio61", "gpio62"; 1705 function = "qup10"; 1706 }; 1707 }; 1708 1709 qup_uart7_default: qup-uart7-default { 1710 pinmux { 1711 pins = "gpio6", "gpio7"; 1712 function = "qup11_uart"; 1713 }; 1714 }; 1715 1716 qup_uart8_default: qup-uart8-default { 1717 pinmux { 1718 pins = "gpio44", "gpio45"; 1719 function = "qup12"; 1720 }; 1721 }; 1722 1723 qup_uart9_default: qup-uart9-default { 1724 pinmux { 1725 pins = "gpio46", "gpio47"; 1726 function = "qup13_uart"; 1727 }; 1728 }; 1729 1730 qup_uart10_default: qup-uart10-default { 1731 pinmux { 1732 pins = "gpio86", "gpio87", 1733 "gpio88", "gpio89"; 1734 function = "qup14"; 1735 }; 1736 }; 1737 1738 qup_uart11_default: qup-uart11-default { 1739 pinmux { 1740 pins = "gpio53", "gpio54", 1741 "gpio55", "gpio56"; 1742 function = "qup15"; 1743 }; 1744 }; 1745 1746 sdc1_on: sdc1-on { 1747 pinconf-clk { 1748 pins = "sdc1_clk"; 1749 bias-disable; 1750 drive-strength = <16>; 1751 }; 1752 1753 pinconf-cmd { 1754 pins = "sdc1_cmd"; 1755 bias-pull-up; 1756 drive-strength = <10>; 1757 }; 1758 1759 pinconf-data { 1760 pins = "sdc1_data"; 1761 bias-pull-up; 1762 drive-strength = <10>; 1763 }; 1764 1765 pinconf-rclk { 1766 pins = "sdc1_rclk"; 1767 bias-pull-down; 1768 }; 1769 }; 1770 1771 sdc1_off: sdc1-off { 1772 pinconf-clk { 1773 pins = "sdc1_clk"; 1774 bias-disable; 1775 drive-strength = <2>; 1776 }; 1777 1778 pinconf-cmd { 1779 pins = "sdc1_cmd"; 1780 bias-pull-up; 1781 drive-strength = <2>; 1782 }; 1783 1784 pinconf-data { 1785 pins = "sdc1_data"; 1786 bias-pull-up; 1787 drive-strength = <2>; 1788 }; 1789 1790 pinconf-rclk { 1791 pins = "sdc1_rclk"; 1792 bias-pull-down; 1793 }; 1794 }; 1795 1796 sdc2_on: sdc2-on { 1797 pinconf-clk { 1798 pins = "sdc2_clk"; 1799 bias-disable; 1800 drive-strength = <16>; 1801 }; 1802 1803 pinconf-cmd { 1804 pins = "sdc2_cmd"; 1805 bias-pull-up; 1806 drive-strength = <10>; 1807 }; 1808 1809 pinconf-data { 1810 pins = "sdc2_data"; 1811 bias-pull-up; 1812 drive-strength = <10>; 1813 }; 1814 1815 pinconf-sd-cd { 1816 pins = "gpio69"; 1817 bias-pull-up; 1818 drive-strength = <2>; 1819 }; 1820 }; 1821 1822 sdc2_off: sdc2-off { 1823 pinconf-clk { 1824 pins = "sdc2_clk"; 1825 bias-disable; 1826 drive-strength = <2>; 1827 }; 1828 1829 pinconf-cmd { 1830 pins = "sdc2_cmd"; 1831 bias-pull-up; 1832 drive-strength = <2>; 1833 }; 1834 1835 pinconf-data { 1836 pins = "sdc2_data"; 1837 bias-pull-up; 1838 drive-strength = <2>; 1839 }; 1840 1841 pinconf-sd-cd { 1842 pins = "gpio69"; 1843 bias-disable; 1844 drive-strength = <2>; 1845 }; 1846 }; 1847 }; 1848 1849 remoteproc_mpss: remoteproc@4080000 { 1850 compatible = "qcom,sc7180-mpss-pas"; 1851 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 1852 reg-names = "qdsp6", "rmb"; 1853 1854 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1855 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1856 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1857 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1858 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1859 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1860 interrupt-names = "wdog", "fatal", "ready", "handover", 1861 "stop-ack", "shutdown-ack"; 1862 1863 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1864 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 1865 <&gcc GCC_MSS_NAV_AXI_CLK>, 1866 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1867 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 1868 <&rpmhcc RPMH_CXO_CLK>; 1869 clock-names = "iface", "bus", "nav", "snoc_axi", 1870 "mnoc_axi", "xo"; 1871 1872 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 1873 <&rpmhpd SC7180_CX>, 1874 <&rpmhpd SC7180_MX>, 1875 <&rpmhpd SC7180_MSS>; 1876 power-domain-names = "load_state", "cx", "mx", "mss"; 1877 1878 memory-region = <&mpss_mem>; 1879 1880 qcom,smem-states = <&modem_smp2p_out 0>; 1881 qcom,smem-state-names = "stop"; 1882 1883 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1884 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1885 reset-names = "mss_restart", "pdc_reset"; 1886 1887 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1888 qcom,spare-regs = <&tcsr_regs 0xb3e4>; 1889 1890 status = "disabled"; 1891 1892 glink-edge { 1893 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1894 label = "modem"; 1895 qcom,remote-pid = <1>; 1896 mboxes = <&apss_shared 12>; 1897 }; 1898 }; 1899 1900 gpu: gpu@5000000 { 1901 compatible = "qcom,adreno-618.0", "qcom,adreno"; 1902 #stream-id-cells = <16>; 1903 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 1904 <0 0x05061000 0 0x800>; 1905 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 1906 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1907 iommus = <&adreno_smmu 0>; 1908 operating-points-v2 = <&gpu_opp_table>; 1909 qcom,gmu = <&gmu>; 1910 1911 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1912 interconnect-names = "gfx-mem"; 1913 1914 gpu_opp_table: opp-table { 1915 compatible = "operating-points-v2"; 1916 1917 opp-800000000 { 1918 opp-hz = /bits/ 64 <800000000>; 1919 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1920 opp-peak-kBps = <8532000>; 1921 }; 1922 1923 opp-650000000 { 1924 opp-hz = /bits/ 64 <650000000>; 1925 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1926 opp-peak-kBps = <7216000>; 1927 }; 1928 1929 opp-565000000 { 1930 opp-hz = /bits/ 64 <565000000>; 1931 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1932 opp-peak-kBps = <5412000>; 1933 }; 1934 1935 opp-430000000 { 1936 opp-hz = /bits/ 64 <430000000>; 1937 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1938 opp-peak-kBps = <5412000>; 1939 }; 1940 1941 opp-355000000 { 1942 opp-hz = /bits/ 64 <355000000>; 1943 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1944 opp-peak-kBps = <3072000>; 1945 }; 1946 1947 opp-267000000 { 1948 opp-hz = /bits/ 64 <267000000>; 1949 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1950 opp-peak-kBps = <3072000>; 1951 }; 1952 1953 opp-180000000 { 1954 opp-hz = /bits/ 64 <180000000>; 1955 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1956 opp-peak-kBps = <1804000>; 1957 }; 1958 }; 1959 }; 1960 1961 adreno_smmu: iommu@5040000 { 1962 compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; 1963 reg = <0 0x05040000 0 0x10000>; 1964 #iommu-cells = <1>; 1965 #global-interrupts = <2>; 1966 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 1969 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 1970 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 1971 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 1972 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 1973 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 1974 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 1975 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 1976 1977 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1978 <&gcc GCC_GPU_CFG_AHB_CLK>; 1979 clock-names = "bus", "iface"; 1980 1981 power-domains = <&gpucc CX_GDSC>; 1982 }; 1983 1984 gmu: gmu@506a000 { 1985 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 1986 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 1987 <0 0x0b490000 0 0x10000>; 1988 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1989 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1991 interrupt-names = "hfi", "gmu"; 1992 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1993 <&gpucc GPU_CC_CXO_CLK>, 1994 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1995 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1996 clock-names = "gmu", "cxo", "axi", "memnoc"; 1997 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 1998 power-domain-names = "cx", "gx"; 1999 iommus = <&adreno_smmu 5>; 2000 operating-points-v2 = <&gmu_opp_table>; 2001 2002 gmu_opp_table: opp-table { 2003 compatible = "operating-points-v2"; 2004 2005 opp-200000000 { 2006 opp-hz = /bits/ 64 <200000000>; 2007 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2008 }; 2009 }; 2010 }; 2011 2012 gpucc: clock-controller@5090000 { 2013 compatible = "qcom,sc7180-gpucc"; 2014 reg = <0 0x05090000 0 0x9000>; 2015 clocks = <&rpmhcc RPMH_CXO_CLK>, 2016 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2017 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2018 clock-names = "bi_tcxo", 2019 "gcc_gpu_gpll0_clk_src", 2020 "gcc_gpu_gpll0_div_clk_src"; 2021 #clock-cells = <1>; 2022 #reset-cells = <1>; 2023 #power-domain-cells = <1>; 2024 }; 2025 2026 stm@6002000 { 2027 compatible = "arm,coresight-stm", "arm,primecell"; 2028 reg = <0 0x06002000 0 0x1000>, 2029 <0 0x16280000 0 0x180000>; 2030 reg-names = "stm-base", "stm-stimulus-base"; 2031 2032 clocks = <&aoss_qmp>; 2033 clock-names = "apb_pclk"; 2034 2035 out-ports { 2036 port { 2037 stm_out: endpoint { 2038 remote-endpoint = <&funnel0_in7>; 2039 }; 2040 }; 2041 }; 2042 }; 2043 2044 funnel@6041000 { 2045 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2046 reg = <0 0x06041000 0 0x1000>; 2047 2048 clocks = <&aoss_qmp>; 2049 clock-names = "apb_pclk"; 2050 2051 out-ports { 2052 port { 2053 funnel0_out: endpoint { 2054 remote-endpoint = <&merge_funnel_in0>; 2055 }; 2056 }; 2057 }; 2058 2059 in-ports { 2060 #address-cells = <1>; 2061 #size-cells = <0>; 2062 2063 port@7 { 2064 reg = <7>; 2065 funnel0_in7: endpoint { 2066 remote-endpoint = <&stm_out>; 2067 }; 2068 }; 2069 }; 2070 }; 2071 2072 funnel@6042000 { 2073 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2074 reg = <0 0x06042000 0 0x1000>; 2075 2076 clocks = <&aoss_qmp>; 2077 clock-names = "apb_pclk"; 2078 2079 out-ports { 2080 port { 2081 funnel1_out: endpoint { 2082 remote-endpoint = <&merge_funnel_in1>; 2083 }; 2084 }; 2085 }; 2086 2087 in-ports { 2088 #address-cells = <1>; 2089 #size-cells = <0>; 2090 2091 port@4 { 2092 reg = <4>; 2093 funnel1_in4: endpoint { 2094 remote-endpoint = <&apss_merge_funnel_out>; 2095 }; 2096 }; 2097 }; 2098 }; 2099 2100 funnel@6045000 { 2101 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2102 reg = <0 0x06045000 0 0x1000>; 2103 2104 clocks = <&aoss_qmp>; 2105 clock-names = "apb_pclk"; 2106 2107 out-ports { 2108 port { 2109 merge_funnel_out: endpoint { 2110 remote-endpoint = <&swao_funnel_in>; 2111 }; 2112 }; 2113 }; 2114 2115 in-ports { 2116 #address-cells = <1>; 2117 #size-cells = <0>; 2118 2119 port@0 { 2120 reg = <0>; 2121 merge_funnel_in0: endpoint { 2122 remote-endpoint = <&funnel0_out>; 2123 }; 2124 }; 2125 2126 port@1 { 2127 reg = <1>; 2128 merge_funnel_in1: endpoint { 2129 remote-endpoint = <&funnel1_out>; 2130 }; 2131 }; 2132 }; 2133 }; 2134 2135 replicator@6046000 { 2136 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2137 reg = <0 0x06046000 0 0x1000>; 2138 2139 clocks = <&aoss_qmp>; 2140 clock-names = "apb_pclk"; 2141 2142 out-ports { 2143 port { 2144 replicator_out: endpoint { 2145 remote-endpoint = <&etr_in>; 2146 }; 2147 }; 2148 }; 2149 2150 in-ports { 2151 port { 2152 replicator_in: endpoint { 2153 remote-endpoint = <&swao_replicator_out>; 2154 }; 2155 }; 2156 }; 2157 }; 2158 2159 etr@6048000 { 2160 compatible = "arm,coresight-tmc", "arm,primecell"; 2161 reg = <0 0x06048000 0 0x1000>; 2162 iommus = <&apps_smmu 0x04a0 0x20>; 2163 2164 clocks = <&aoss_qmp>; 2165 clock-names = "apb_pclk"; 2166 arm,scatter-gather; 2167 2168 in-ports { 2169 port { 2170 etr_in: endpoint { 2171 remote-endpoint = <&replicator_out>; 2172 }; 2173 }; 2174 }; 2175 }; 2176 2177 funnel@6b04000 { 2178 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2179 reg = <0 0x06b04000 0 0x1000>; 2180 2181 clocks = <&aoss_qmp>; 2182 clock-names = "apb_pclk"; 2183 2184 out-ports { 2185 port { 2186 swao_funnel_out: endpoint { 2187 remote-endpoint = <&etf_in>; 2188 }; 2189 }; 2190 }; 2191 2192 in-ports { 2193 #address-cells = <1>; 2194 #size-cells = <0>; 2195 2196 port@7 { 2197 reg = <7>; 2198 swao_funnel_in: endpoint { 2199 remote-endpoint = <&merge_funnel_out>; 2200 }; 2201 }; 2202 }; 2203 }; 2204 2205 etf@6b05000 { 2206 compatible = "arm,coresight-tmc", "arm,primecell"; 2207 reg = <0 0x06b05000 0 0x1000>; 2208 2209 clocks = <&aoss_qmp>; 2210 clock-names = "apb_pclk"; 2211 2212 out-ports { 2213 port { 2214 etf_out: endpoint { 2215 remote-endpoint = <&swao_replicator_in>; 2216 }; 2217 }; 2218 }; 2219 2220 in-ports { 2221 port { 2222 etf_in: endpoint { 2223 remote-endpoint = <&swao_funnel_out>; 2224 }; 2225 }; 2226 }; 2227 }; 2228 2229 replicator@6b06000 { 2230 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2231 reg = <0 0x06b06000 0 0x1000>; 2232 2233 clocks = <&aoss_qmp>; 2234 clock-names = "apb_pclk"; 2235 qcom,replicator-loses-context; 2236 2237 out-ports { 2238 port { 2239 swao_replicator_out: endpoint { 2240 remote-endpoint = <&replicator_in>; 2241 }; 2242 }; 2243 }; 2244 2245 in-ports { 2246 port { 2247 swao_replicator_in: endpoint { 2248 remote-endpoint = <&etf_out>; 2249 }; 2250 }; 2251 }; 2252 }; 2253 2254 etm@7040000 { 2255 compatible = "arm,coresight-etm4x", "arm,primecell"; 2256 reg = <0 0x07040000 0 0x1000>; 2257 2258 cpu = <&CPU0>; 2259 2260 clocks = <&aoss_qmp>; 2261 clock-names = "apb_pclk"; 2262 arm,coresight-loses-context-with-cpu; 2263 qcom,skip-power-up; 2264 2265 out-ports { 2266 port { 2267 etm0_out: endpoint { 2268 remote-endpoint = <&apss_funnel_in0>; 2269 }; 2270 }; 2271 }; 2272 }; 2273 2274 etm@7140000 { 2275 compatible = "arm,coresight-etm4x", "arm,primecell"; 2276 reg = <0 0x07140000 0 0x1000>; 2277 2278 cpu = <&CPU1>; 2279 2280 clocks = <&aoss_qmp>; 2281 clock-names = "apb_pclk"; 2282 arm,coresight-loses-context-with-cpu; 2283 qcom,skip-power-up; 2284 2285 out-ports { 2286 port { 2287 etm1_out: endpoint { 2288 remote-endpoint = <&apss_funnel_in1>; 2289 }; 2290 }; 2291 }; 2292 }; 2293 2294 etm@7240000 { 2295 compatible = "arm,coresight-etm4x", "arm,primecell"; 2296 reg = <0 0x07240000 0 0x1000>; 2297 2298 cpu = <&CPU2>; 2299 2300 clocks = <&aoss_qmp>; 2301 clock-names = "apb_pclk"; 2302 arm,coresight-loses-context-with-cpu; 2303 qcom,skip-power-up; 2304 2305 out-ports { 2306 port { 2307 etm2_out: endpoint { 2308 remote-endpoint = <&apss_funnel_in2>; 2309 }; 2310 }; 2311 }; 2312 }; 2313 2314 etm@7340000 { 2315 compatible = "arm,coresight-etm4x", "arm,primecell"; 2316 reg = <0 0x07340000 0 0x1000>; 2317 2318 cpu = <&CPU3>; 2319 2320 clocks = <&aoss_qmp>; 2321 clock-names = "apb_pclk"; 2322 arm,coresight-loses-context-with-cpu; 2323 qcom,skip-power-up; 2324 2325 out-ports { 2326 port { 2327 etm3_out: endpoint { 2328 remote-endpoint = <&apss_funnel_in3>; 2329 }; 2330 }; 2331 }; 2332 }; 2333 2334 etm@7440000 { 2335 compatible = "arm,coresight-etm4x", "arm,primecell"; 2336 reg = <0 0x07440000 0 0x1000>; 2337 2338 cpu = <&CPU4>; 2339 2340 clocks = <&aoss_qmp>; 2341 clock-names = "apb_pclk"; 2342 arm,coresight-loses-context-with-cpu; 2343 qcom,skip-power-up; 2344 2345 out-ports { 2346 port { 2347 etm4_out: endpoint { 2348 remote-endpoint = <&apss_funnel_in4>; 2349 }; 2350 }; 2351 }; 2352 }; 2353 2354 etm@7540000 { 2355 compatible = "arm,coresight-etm4x", "arm,primecell"; 2356 reg = <0 0x07540000 0 0x1000>; 2357 2358 cpu = <&CPU5>; 2359 2360 clocks = <&aoss_qmp>; 2361 clock-names = "apb_pclk"; 2362 arm,coresight-loses-context-with-cpu; 2363 qcom,skip-power-up; 2364 2365 out-ports { 2366 port { 2367 etm5_out: endpoint { 2368 remote-endpoint = <&apss_funnel_in5>; 2369 }; 2370 }; 2371 }; 2372 }; 2373 2374 etm@7640000 { 2375 compatible = "arm,coresight-etm4x", "arm,primecell"; 2376 reg = <0 0x07640000 0 0x1000>; 2377 2378 cpu = <&CPU6>; 2379 2380 clocks = <&aoss_qmp>; 2381 clock-names = "apb_pclk"; 2382 arm,coresight-loses-context-with-cpu; 2383 qcom,skip-power-up; 2384 2385 out-ports { 2386 port { 2387 etm6_out: endpoint { 2388 remote-endpoint = <&apss_funnel_in6>; 2389 }; 2390 }; 2391 }; 2392 }; 2393 2394 etm@7740000 { 2395 compatible = "arm,coresight-etm4x", "arm,primecell"; 2396 reg = <0 0x07740000 0 0x1000>; 2397 2398 cpu = <&CPU7>; 2399 2400 clocks = <&aoss_qmp>; 2401 clock-names = "apb_pclk"; 2402 arm,coresight-loses-context-with-cpu; 2403 qcom,skip-power-up; 2404 2405 out-ports { 2406 port { 2407 etm7_out: endpoint { 2408 remote-endpoint = <&apss_funnel_in7>; 2409 }; 2410 }; 2411 }; 2412 }; 2413 2414 funnel@7800000 { /* APSS Funnel */ 2415 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2416 reg = <0 0x07800000 0 0x1000>; 2417 2418 clocks = <&aoss_qmp>; 2419 clock-names = "apb_pclk"; 2420 2421 out-ports { 2422 port { 2423 apss_funnel_out: endpoint { 2424 remote-endpoint = <&apss_merge_funnel_in>; 2425 }; 2426 }; 2427 }; 2428 2429 in-ports { 2430 #address-cells = <1>; 2431 #size-cells = <0>; 2432 2433 port@0 { 2434 reg = <0>; 2435 apss_funnel_in0: endpoint { 2436 remote-endpoint = <&etm0_out>; 2437 }; 2438 }; 2439 2440 port@1 { 2441 reg = <1>; 2442 apss_funnel_in1: endpoint { 2443 remote-endpoint = <&etm1_out>; 2444 }; 2445 }; 2446 2447 port@2 { 2448 reg = <2>; 2449 apss_funnel_in2: endpoint { 2450 remote-endpoint = <&etm2_out>; 2451 }; 2452 }; 2453 2454 port@3 { 2455 reg = <3>; 2456 apss_funnel_in3: endpoint { 2457 remote-endpoint = <&etm3_out>; 2458 }; 2459 }; 2460 2461 port@4 { 2462 reg = <4>; 2463 apss_funnel_in4: endpoint { 2464 remote-endpoint = <&etm4_out>; 2465 }; 2466 }; 2467 2468 port@5 { 2469 reg = <5>; 2470 apss_funnel_in5: endpoint { 2471 remote-endpoint = <&etm5_out>; 2472 }; 2473 }; 2474 2475 port@6 { 2476 reg = <6>; 2477 apss_funnel_in6: endpoint { 2478 remote-endpoint = <&etm6_out>; 2479 }; 2480 }; 2481 2482 port@7 { 2483 reg = <7>; 2484 apss_funnel_in7: endpoint { 2485 remote-endpoint = <&etm7_out>; 2486 }; 2487 }; 2488 }; 2489 }; 2490 2491 funnel@7810000 { 2492 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2493 reg = <0 0x07810000 0 0x1000>; 2494 2495 clocks = <&aoss_qmp>; 2496 clock-names = "apb_pclk"; 2497 2498 out-ports { 2499 port { 2500 apss_merge_funnel_out: endpoint { 2501 remote-endpoint = <&funnel1_in4>; 2502 }; 2503 }; 2504 }; 2505 2506 in-ports { 2507 port { 2508 apss_merge_funnel_in: endpoint { 2509 remote-endpoint = <&apss_funnel_out>; 2510 }; 2511 }; 2512 }; 2513 }; 2514 2515 sdhc_2: sdhci@8804000 { 2516 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2517 reg = <0 0x08804000 0 0x1000>; 2518 2519 iommus = <&apps_smmu 0x80 0>; 2520 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2521 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2522 interrupt-names = "hc_irq", "pwr_irq"; 2523 2524 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2525 <&gcc GCC_SDCC2_AHB_CLK>; 2526 clock-names = "core", "iface"; 2527 2528 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2529 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2530 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2531 power-domains = <&rpmhpd SC7180_CX>; 2532 operating-points-v2 = <&sdhc2_opp_table>; 2533 2534 bus-width = <4>; 2535 2536 status = "disabled"; 2537 2538 sdhc2_opp_table: sdhc2-opp-table { 2539 compatible = "operating-points-v2"; 2540 2541 opp-100000000 { 2542 opp-hz = /bits/ 64 <100000000>; 2543 required-opps = <&rpmhpd_opp_low_svs>; 2544 opp-peak-kBps = <160000 100000>; 2545 opp-avg-kBps = <80000 50000>; 2546 }; 2547 2548 opp-202000000 { 2549 opp-hz = /bits/ 64 <202000000>; 2550 required-opps = <&rpmhpd_opp_svs_l1>; 2551 opp-peak-kBps = <200000 120000>; 2552 opp-avg-kBps = <100000 60000>; 2553 }; 2554 }; 2555 }; 2556 2557 qspi_opp_table: qspi-opp-table { 2558 compatible = "operating-points-v2"; 2559 2560 opp-75000000 { 2561 opp-hz = /bits/ 64 <75000000>; 2562 required-opps = <&rpmhpd_opp_low_svs>; 2563 }; 2564 2565 opp-150000000 { 2566 opp-hz = /bits/ 64 <150000000>; 2567 required-opps = <&rpmhpd_opp_svs>; 2568 }; 2569 2570 opp-300000000 { 2571 opp-hz = /bits/ 64 <300000000>; 2572 required-opps = <&rpmhpd_opp_nom>; 2573 }; 2574 }; 2575 2576 qspi: spi@88dc000 { 2577 compatible = "qcom,qspi-v1"; 2578 reg = <0 0x088dc000 0 0x600>; 2579 #address-cells = <1>; 2580 #size-cells = <0>; 2581 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2582 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2583 <&gcc GCC_QSPI_CORE_CLK>; 2584 clock-names = "iface", "core"; 2585 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2586 &config_noc SLAVE_QSPI_0 0>; 2587 interconnect-names = "qspi-config"; 2588 power-domains = <&rpmhpd SC7180_CX>; 2589 operating-points-v2 = <&qspi_opp_table>; 2590 status = "disabled"; 2591 }; 2592 2593 usb_1_hsphy: phy@88e3000 { 2594 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2595 reg = <0 0x088e3000 0 0x400>; 2596 status = "disabled"; 2597 #phy-cells = <0>; 2598 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2599 <&rpmhcc RPMH_CXO_CLK>; 2600 clock-names = "cfg_ahb", "ref"; 2601 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2602 2603 nvmem-cells = <&qusb2p_hstx_trim>; 2604 }; 2605 2606 usb_1_qmpphy: phy-wrapper@88e9000 { 2607 compatible = "qcom,sc7180-qmp-usb3-phy"; 2608 reg = <0 0x088e9000 0 0x18c>, 2609 <0 0x088e8000 0 0x38>; 2610 reg-names = "reg-base", "dp_com"; 2611 status = "disabled"; 2612 #clock-cells = <1>; 2613 #address-cells = <2>; 2614 #size-cells = <2>; 2615 ranges; 2616 2617 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2618 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2619 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2620 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2621 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2622 2623 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2624 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2625 reset-names = "phy", "common"; 2626 2627 usb_1_ssphy: phy@88e9200 { 2628 reg = <0 0x088e9200 0 0x128>, 2629 <0 0x088e9400 0 0x200>, 2630 <0 0x088e9c00 0 0x218>, 2631 <0 0x088e9600 0 0x128>, 2632 <0 0x088e9800 0 0x200>, 2633 <0 0x088e9a00 0 0x18>; 2634 #clock-cells = <0>; 2635 #phy-cells = <0>; 2636 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2637 clock-names = "pipe0"; 2638 clock-output-names = "usb3_phy_pipe_clk_src"; 2639 }; 2640 }; 2641 2642 dc_noc: interconnect@9160000 { 2643 compatible = "qcom,sc7180-dc-noc"; 2644 reg = <0 0x09160000 0 0x03200>; 2645 #interconnect-cells = <2>; 2646 qcom,bcm-voters = <&apps_bcm_voter>; 2647 }; 2648 2649 system-cache-controller@9200000 { 2650 compatible = "qcom,sc7180-llcc"; 2651 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2652 reg-names = "llcc_base", "llcc_broadcast_base"; 2653 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2654 }; 2655 2656 gem_noc: interconnect@9680000 { 2657 compatible = "qcom,sc7180-gem-noc"; 2658 reg = <0 0x09680000 0 0x3e200>; 2659 #interconnect-cells = <2>; 2660 qcom,bcm-voters = <&apps_bcm_voter>; 2661 }; 2662 2663 npu_noc: interconnect@9990000 { 2664 compatible = "qcom,sc7180-npu-noc"; 2665 reg = <0 0x09990000 0 0x1600>; 2666 #interconnect-cells = <2>; 2667 qcom,bcm-voters = <&apps_bcm_voter>; 2668 }; 2669 2670 usb_1: usb@a6f8800 { 2671 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2672 reg = <0 0x0a6f8800 0 0x400>; 2673 status = "disabled"; 2674 #address-cells = <2>; 2675 #size-cells = <2>; 2676 ranges; 2677 dma-ranges; 2678 2679 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2680 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2681 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2682 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2683 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2684 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2685 "sleep"; 2686 2687 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2688 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2689 assigned-clock-rates = <19200000>, <150000000>; 2690 2691 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2692 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2694 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2695 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2696 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2697 2698 power-domains = <&gcc USB30_PRIM_GDSC>; 2699 2700 resets = <&gcc GCC_USB30_PRIM_BCR>; 2701 2702 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2703 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2704 interconnect-names = "usb-ddr", "apps-usb"; 2705 2706 usb_1_dwc3: dwc3@a600000 { 2707 compatible = "snps,dwc3"; 2708 reg = <0 0x0a600000 0 0xe000>; 2709 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2710 iommus = <&apps_smmu 0x540 0>; 2711 snps,dis_u2_susphy_quirk; 2712 snps,dis_enblslpm_quirk; 2713 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2714 phy-names = "usb2-phy", "usb3-phy"; 2715 maximum-speed = "super-speed"; 2716 }; 2717 }; 2718 2719 venus: video-codec@aa00000 { 2720 compatible = "qcom,sc7180-venus"; 2721 reg = <0 0x0aa00000 0 0xff000>; 2722 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2723 power-domains = <&videocc VENUS_GDSC>, 2724 <&videocc VCODEC0_GDSC>, 2725 <&rpmhpd SC7180_CX>; 2726 power-domain-names = "venus", "vcodec0", "cx"; 2727 operating-points-v2 = <&venus_opp_table>; 2728 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2729 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2730 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2731 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2732 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2733 clock-names = "core", "iface", "bus", 2734 "vcodec0_core", "vcodec0_bus"; 2735 iommus = <&apps_smmu 0x0c00 0x60>; 2736 memory-region = <&venus_mem>; 2737 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2738 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2739 interconnect-names = "video-mem", "cpu-cfg"; 2740 2741 video-decoder { 2742 compatible = "venus-decoder"; 2743 }; 2744 2745 video-encoder { 2746 compatible = "venus-encoder"; 2747 }; 2748 2749 venus_opp_table: venus-opp-table { 2750 compatible = "operating-points-v2"; 2751 2752 opp-150000000 { 2753 opp-hz = /bits/ 64 <150000000>; 2754 required-opps = <&rpmhpd_opp_low_svs>; 2755 }; 2756 2757 opp-270000000 { 2758 opp-hz = /bits/ 64 <270000000>; 2759 required-opps = <&rpmhpd_opp_svs>; 2760 }; 2761 2762 opp-340000000 { 2763 opp-hz = /bits/ 64 <340000000>; 2764 required-opps = <&rpmhpd_opp_svs_l1>; 2765 }; 2766 2767 opp-434000000 { 2768 opp-hz = /bits/ 64 <434000000>; 2769 required-opps = <&rpmhpd_opp_nom>; 2770 }; 2771 2772 opp-500000097 { 2773 opp-hz = /bits/ 64 <500000097>; 2774 required-opps = <&rpmhpd_opp_turbo>; 2775 }; 2776 }; 2777 }; 2778 2779 videocc: clock-controller@ab00000 { 2780 compatible = "qcom,sc7180-videocc"; 2781 reg = <0 0x0ab00000 0 0x10000>; 2782 clocks = <&rpmhcc RPMH_CXO_CLK>; 2783 clock-names = "bi_tcxo"; 2784 #clock-cells = <1>; 2785 #reset-cells = <1>; 2786 #power-domain-cells = <1>; 2787 }; 2788 2789 camnoc_virt: interconnect@ac00000 { 2790 compatible = "qcom,sc7180-camnoc-virt"; 2791 reg = <0 0x0ac00000 0 0x1000>; 2792 #interconnect-cells = <2>; 2793 qcom,bcm-voters = <&apps_bcm_voter>; 2794 }; 2795 2796 mdss: mdss@ae00000 { 2797 compatible = "qcom,sc7180-mdss"; 2798 reg = <0 0x0ae00000 0 0x1000>; 2799 reg-names = "mdss"; 2800 2801 power-domains = <&dispcc MDSS_GDSC>; 2802 2803 clocks = <&gcc GCC_DISP_AHB_CLK>, 2804 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2805 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2806 clock-names = "iface", "ahb", "core"; 2807 2808 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2809 assigned-clock-rates = <300000000>; 2810 2811 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2812 interrupt-controller; 2813 #interrupt-cells = <1>; 2814 2815 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2816 interconnect-names = "mdp0-mem"; 2817 2818 iommus = <&apps_smmu 0x800 0x2>; 2819 2820 #address-cells = <2>; 2821 #size-cells = <2>; 2822 ranges; 2823 2824 status = "disabled"; 2825 2826 mdp: mdp@ae01000 { 2827 compatible = "qcom,sc7180-dpu"; 2828 reg = <0 0x0ae01000 0 0x8f000>, 2829 <0 0x0aeb0000 0 0x2008>; 2830 reg-names = "mdp", "vbif"; 2831 2832 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2833 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2834 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2835 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2836 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2837 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2838 clock-names = "bus", "iface", "rot", "lut", "core", 2839 "vsync"; 2840 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2841 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2842 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2843 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2844 assigned-clock-rates = <300000000>, 2845 <19200000>, 2846 <19200000>, 2847 <19200000>; 2848 operating-points-v2 = <&mdp_opp_table>; 2849 power-domains = <&rpmhpd SC7180_CX>; 2850 2851 interrupt-parent = <&mdss>; 2852 interrupts = <0>; 2853 2854 status = "disabled"; 2855 2856 ports { 2857 #address-cells = <1>; 2858 #size-cells = <0>; 2859 2860 port@0 { 2861 reg = <0>; 2862 dpu_intf1_out: endpoint { 2863 remote-endpoint = <&dsi0_in>; 2864 }; 2865 }; 2866 }; 2867 2868 mdp_opp_table: mdp-opp-table { 2869 compatible = "operating-points-v2"; 2870 2871 opp-200000000 { 2872 opp-hz = /bits/ 64 <200000000>; 2873 required-opps = <&rpmhpd_opp_low_svs>; 2874 }; 2875 2876 opp-300000000 { 2877 opp-hz = /bits/ 64 <300000000>; 2878 required-opps = <&rpmhpd_opp_svs>; 2879 }; 2880 2881 opp-345000000 { 2882 opp-hz = /bits/ 64 <345000000>; 2883 required-opps = <&rpmhpd_opp_svs_l1>; 2884 }; 2885 2886 opp-460000000 { 2887 opp-hz = /bits/ 64 <460000000>; 2888 required-opps = <&rpmhpd_opp_nom>; 2889 }; 2890 }; 2891 2892 }; 2893 2894 dsi0: dsi@ae94000 { 2895 compatible = "qcom,mdss-dsi-ctrl"; 2896 reg = <0 0x0ae94000 0 0x400>; 2897 reg-names = "dsi_ctrl"; 2898 2899 interrupt-parent = <&mdss>; 2900 interrupts = <4>; 2901 2902 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2903 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2904 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2905 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2906 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2907 <&gcc GCC_DISP_HF_AXI_CLK>; 2908 clock-names = "byte", 2909 "byte_intf", 2910 "pixel", 2911 "core", 2912 "iface", 2913 "bus"; 2914 2915 operating-points-v2 = <&dsi_opp_table>; 2916 power-domains = <&rpmhpd SC7180_CX>; 2917 2918 phys = <&dsi_phy>; 2919 phy-names = "dsi"; 2920 2921 #address-cells = <1>; 2922 #size-cells = <0>; 2923 2924 status = "disabled"; 2925 2926 ports { 2927 #address-cells = <1>; 2928 #size-cells = <0>; 2929 2930 port@0 { 2931 reg = <0>; 2932 dsi0_in: endpoint { 2933 remote-endpoint = <&dpu_intf1_out>; 2934 }; 2935 }; 2936 2937 port@1 { 2938 reg = <1>; 2939 dsi0_out: endpoint { 2940 }; 2941 }; 2942 }; 2943 2944 dsi_opp_table: dsi-opp-table { 2945 compatible = "operating-points-v2"; 2946 2947 opp-187500000 { 2948 opp-hz = /bits/ 64 <187500000>; 2949 required-opps = <&rpmhpd_opp_low_svs>; 2950 }; 2951 2952 opp-300000000 { 2953 opp-hz = /bits/ 64 <300000000>; 2954 required-opps = <&rpmhpd_opp_svs>; 2955 }; 2956 2957 opp-358000000 { 2958 opp-hz = /bits/ 64 <358000000>; 2959 required-opps = <&rpmhpd_opp_svs_l1>; 2960 }; 2961 }; 2962 }; 2963 2964 dsi_phy: dsi-phy@ae94400 { 2965 compatible = "qcom,dsi-phy-10nm"; 2966 reg = <0 0x0ae94400 0 0x200>, 2967 <0 0x0ae94600 0 0x280>, 2968 <0 0x0ae94a00 0 0x1e0>; 2969 reg-names = "dsi_phy", 2970 "dsi_phy_lane", 2971 "dsi_pll"; 2972 2973 #clock-cells = <1>; 2974 #phy-cells = <0>; 2975 2976 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2977 <&rpmhcc RPMH_CXO_CLK>; 2978 clock-names = "iface", "ref"; 2979 2980 status = "disabled"; 2981 }; 2982 }; 2983 2984 dispcc: clock-controller@af00000 { 2985 compatible = "qcom,sc7180-dispcc"; 2986 reg = <0 0x0af00000 0 0x200000>; 2987 clocks = <&rpmhcc RPMH_CXO_CLK>, 2988 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2989 <&dsi_phy 0>, 2990 <&dsi_phy 1>, 2991 <0>, 2992 <0>; 2993 clock-names = "bi_tcxo", 2994 "gcc_disp_gpll0_clk_src", 2995 "dsi0_phy_pll_out_byteclk", 2996 "dsi0_phy_pll_out_dsiclk", 2997 "dp_phy_pll_link_clk", 2998 "dp_phy_pll_vco_div_clk"; 2999 #clock-cells = <1>; 3000 #reset-cells = <1>; 3001 #power-domain-cells = <1>; 3002 }; 3003 3004 pdc: interrupt-controller@b220000 { 3005 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3006 reg = <0 0x0b220000 0 0x30000>; 3007 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3008 #interrupt-cells = <2>; 3009 interrupt-parent = <&intc>; 3010 interrupt-controller; 3011 }; 3012 3013 pdc_reset: reset-controller@b2e0000 { 3014 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3015 reg = <0 0x0b2e0000 0 0x20000>; 3016 #reset-cells = <1>; 3017 }; 3018 3019 tsens0: thermal-sensor@c263000 { 3020 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3021 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3022 <0 0x0c222000 0 0x1ff>; /* SROT */ 3023 #qcom,sensors = <15>; 3024 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3025 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3026 interrupt-names = "uplow","critical"; 3027 #thermal-sensor-cells = <1>; 3028 }; 3029 3030 tsens1: thermal-sensor@c265000 { 3031 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3032 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3033 <0 0x0c223000 0 0x1ff>; /* SROT */ 3034 #qcom,sensors = <10>; 3035 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3036 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3037 interrupt-names = "uplow","critical"; 3038 #thermal-sensor-cells = <1>; 3039 }; 3040 3041 aoss_reset: reset-controller@c2a0000 { 3042 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3043 reg = <0 0x0c2a0000 0 0x31000>; 3044 #reset-cells = <1>; 3045 }; 3046 3047 aoss_qmp: qmp@c300000 { 3048 compatible = "qcom,sc7180-aoss-qmp"; 3049 reg = <0 0x0c300000 0 0x100000>; 3050 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3051 mboxes = <&apss_shared 0>; 3052 3053 #clock-cells = <0>; 3054 #power-domain-cells = <1>; 3055 }; 3056 3057 spmi_bus: spmi@c440000 { 3058 compatible = "qcom,spmi-pmic-arb"; 3059 reg = <0 0x0c440000 0 0x1100>, 3060 <0 0x0c600000 0 0x2000000>, 3061 <0 0x0e600000 0 0x100000>, 3062 <0 0x0e700000 0 0xa0000>, 3063 <0 0x0c40a000 0 0x26000>; 3064 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3065 interrupt-names = "periph_irq"; 3066 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3067 qcom,ee = <0>; 3068 qcom,channel = <0>; 3069 #address-cells = <1>; 3070 #size-cells = <1>; 3071 interrupt-controller; 3072 #interrupt-cells = <4>; 3073 cell-index = <0>; 3074 }; 3075 3076 apps_smmu: iommu@15000000 { 3077 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3078 reg = <0 0x15000000 0 0x100000>; 3079 #iommu-cells = <2>; 3080 #global-interrupts = <1>; 3081 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3101 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3162 }; 3163 3164 intc: interrupt-controller@17a00000 { 3165 compatible = "arm,gic-v3"; 3166 #address-cells = <2>; 3167 #size-cells = <2>; 3168 ranges; 3169 #interrupt-cells = <3>; 3170 interrupt-controller; 3171 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3172 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3173 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3174 3175 msi-controller@17a40000 { 3176 compatible = "arm,gic-v3-its"; 3177 msi-controller; 3178 #msi-cells = <1>; 3179 reg = <0 0x17a40000 0 0x20000>; 3180 status = "disabled"; 3181 }; 3182 }; 3183 3184 apss_shared: mailbox@17c00000 { 3185 compatible = "qcom,sc7180-apss-shared"; 3186 reg = <0 0x17c00000 0 0x10000>; 3187 #mbox-cells = <1>; 3188 }; 3189 3190 watchdog@17c10000 { 3191 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3192 reg = <0 0x17c10000 0 0x1000>; 3193 clocks = <&sleep_clk>; 3194 }; 3195 3196 timer@17c20000{ 3197 #address-cells = <2>; 3198 #size-cells = <2>; 3199 ranges; 3200 compatible = "arm,armv7-timer-mem"; 3201 reg = <0 0x17c20000 0 0x1000>; 3202 3203 frame@17c21000 { 3204 frame-number = <0>; 3205 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3206 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3207 reg = <0 0x17c21000 0 0x1000>, 3208 <0 0x17c22000 0 0x1000>; 3209 }; 3210 3211 frame@17c23000 { 3212 frame-number = <1>; 3213 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3214 reg = <0 0x17c23000 0 0x1000>; 3215 status = "disabled"; 3216 }; 3217 3218 frame@17c25000 { 3219 frame-number = <2>; 3220 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3221 reg = <0 0x17c25000 0 0x1000>; 3222 status = "disabled"; 3223 }; 3224 3225 frame@17c27000 { 3226 frame-number = <3>; 3227 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3228 reg = <0 0x17c27000 0 0x1000>; 3229 status = "disabled"; 3230 }; 3231 3232 frame@17c29000 { 3233 frame-number = <4>; 3234 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3235 reg = <0 0x17c29000 0 0x1000>; 3236 status = "disabled"; 3237 }; 3238 3239 frame@17c2b000 { 3240 frame-number = <5>; 3241 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3242 reg = <0 0x17c2b000 0 0x1000>; 3243 status = "disabled"; 3244 }; 3245 3246 frame@17c2d000 { 3247 frame-number = <6>; 3248 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3249 reg = <0 0x17c2d000 0 0x1000>; 3250 status = "disabled"; 3251 }; 3252 }; 3253 3254 apps_rsc: rsc@18200000 { 3255 compatible = "qcom,rpmh-rsc"; 3256 reg = <0 0x18200000 0 0x10000>, 3257 <0 0x18210000 0 0x10000>, 3258 <0 0x18220000 0 0x10000>; 3259 reg-names = "drv-0", "drv-1", "drv-2"; 3260 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3263 qcom,tcs-offset = <0xd00>; 3264 qcom,drv-id = <2>; 3265 qcom,tcs-config = <ACTIVE_TCS 2>, 3266 <SLEEP_TCS 3>, 3267 <WAKE_TCS 3>, 3268 <CONTROL_TCS 1>; 3269 3270 rpmhcc: clock-controller { 3271 compatible = "qcom,sc7180-rpmh-clk"; 3272 clocks = <&xo_board>; 3273 clock-names = "xo"; 3274 #clock-cells = <1>; 3275 }; 3276 3277 rpmhpd: power-controller { 3278 compatible = "qcom,sc7180-rpmhpd"; 3279 #power-domain-cells = <1>; 3280 operating-points-v2 = <&rpmhpd_opp_table>; 3281 3282 rpmhpd_opp_table: opp-table { 3283 compatible = "operating-points-v2"; 3284 3285 rpmhpd_opp_ret: opp1 { 3286 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3287 }; 3288 3289 rpmhpd_opp_min_svs: opp2 { 3290 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3291 }; 3292 3293 rpmhpd_opp_low_svs: opp3 { 3294 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3295 }; 3296 3297 rpmhpd_opp_svs: opp4 { 3298 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3299 }; 3300 3301 rpmhpd_opp_svs_l1: opp5 { 3302 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3303 }; 3304 3305 rpmhpd_opp_svs_l2: opp6 { 3306 opp-level = <224>; 3307 }; 3308 3309 rpmhpd_opp_nom: opp7 { 3310 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3311 }; 3312 3313 rpmhpd_opp_nom_l1: opp8 { 3314 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3315 }; 3316 3317 rpmhpd_opp_nom_l2: opp9 { 3318 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3319 }; 3320 3321 rpmhpd_opp_turbo: opp10 { 3322 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3323 }; 3324 3325 rpmhpd_opp_turbo_l1: opp11 { 3326 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3327 }; 3328 }; 3329 }; 3330 3331 apps_bcm_voter: bcm_voter { 3332 compatible = "qcom,bcm-voter"; 3333 }; 3334 }; 3335 3336 osm_l3: interconnect@18321000 { 3337 compatible = "qcom,sc7180-osm-l3"; 3338 reg = <0 0x18321000 0 0x1400>; 3339 3340 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3341 clock-names = "xo", "alternate"; 3342 3343 #interconnect-cells = <1>; 3344 }; 3345 3346 cpufreq_hw: cpufreq@18323000 { 3347 compatible = "qcom,cpufreq-hw"; 3348 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3349 reg-names = "freq-domain0", "freq-domain1"; 3350 3351 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3352 clock-names = "xo", "alternate"; 3353 3354 #freq-domain-cells = <1>; 3355 }; 3356 3357 wifi: wifi@18800000 { 3358 compatible = "qcom,wcn3990-wifi"; 3359 reg = <0 0x18800000 0 0x800000>; 3360 reg-names = "membase"; 3361 iommus = <&apps_smmu 0xc0 0x1>; 3362 interrupts = 3363 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3364 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3365 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3366 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3367 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3368 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3369 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3370 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3371 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3372 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3373 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3374 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3375 memory-region = <&wlan_mem>; 3376 qcom,msa-fixed-perm; 3377 status = "disabled"; 3378 }; 3379 3380 lpasscc: clock-controller@62d00000 { 3381 compatible = "qcom,sc7180-lpasscorecc"; 3382 reg = <0 0x62d00000 0 0x50000>, 3383 <0 0x62780000 0 0x30000>; 3384 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3385 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3386 <&rpmhcc RPMH_CXO_CLK>; 3387 clock-names = "iface", "bi_tcxo"; 3388 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3389 #clock-cells = <1>; 3390 #power-domain-cells = <1>; 3391 }; 3392 3393 lpass_hm: clock-controller@63000000 { 3394 compatible = "qcom,sc7180-lpasshm"; 3395 reg = <0 0x63000000 0 0x28>; 3396 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3397 <&rpmhcc RPMH_CXO_CLK>; 3398 clock-names = "iface", "bi_tcxo"; 3399 #clock-cells = <1>; 3400 #power-domain-cells = <1>; 3401 }; 3402 }; 3403 3404 thermal-zones { 3405 cpu0-thermal { 3406 polling-delay-passive = <0>; 3407 polling-delay = <0>; 3408 3409 thermal-sensors = <&tsens0 1>; 3410 sustainable-power = <768>; 3411 3412 trips { 3413 cpu0_alert0: trip-point0 { 3414 temperature = <90000>; 3415 hysteresis = <2000>; 3416 type = "passive"; 3417 }; 3418 3419 cpu0_alert1: trip-point1 { 3420 temperature = <95000>; 3421 hysteresis = <2000>; 3422 type = "passive"; 3423 }; 3424 3425 cpu0_crit: cpu_crit { 3426 temperature = <110000>; 3427 hysteresis = <1000>; 3428 type = "critical"; 3429 }; 3430 }; 3431 3432 cooling-maps { 3433 map0 { 3434 trip = <&cpu0_alert0>; 3435 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3436 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3437 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3438 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3439 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3440 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3441 }; 3442 map1 { 3443 trip = <&cpu0_alert1>; 3444 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3445 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3446 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3447 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3448 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3449 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3450 }; 3451 }; 3452 }; 3453 3454 cpu1-thermal { 3455 polling-delay-passive = <0>; 3456 polling-delay = <0>; 3457 3458 thermal-sensors = <&tsens0 2>; 3459 sustainable-power = <768>; 3460 3461 trips { 3462 cpu1_alert0: trip-point0 { 3463 temperature = <90000>; 3464 hysteresis = <2000>; 3465 type = "passive"; 3466 }; 3467 3468 cpu1_alert1: trip-point1 { 3469 temperature = <95000>; 3470 hysteresis = <2000>; 3471 type = "passive"; 3472 }; 3473 3474 cpu1_crit: cpu_crit { 3475 temperature = <110000>; 3476 hysteresis = <1000>; 3477 type = "critical"; 3478 }; 3479 }; 3480 3481 cooling-maps { 3482 map0 { 3483 trip = <&cpu1_alert0>; 3484 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3485 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3486 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3487 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3488 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3489 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3490 }; 3491 map1 { 3492 trip = <&cpu1_alert1>; 3493 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3494 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3495 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3496 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3497 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3498 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3499 }; 3500 }; 3501 }; 3502 3503 cpu2-thermal { 3504 polling-delay-passive = <0>; 3505 polling-delay = <0>; 3506 3507 thermal-sensors = <&tsens0 3>; 3508 sustainable-power = <768>; 3509 3510 trips { 3511 cpu2_alert0: trip-point0 { 3512 temperature = <90000>; 3513 hysteresis = <2000>; 3514 type = "passive"; 3515 }; 3516 3517 cpu2_alert1: trip-point1 { 3518 temperature = <95000>; 3519 hysteresis = <2000>; 3520 type = "passive"; 3521 }; 3522 3523 cpu2_crit: cpu_crit { 3524 temperature = <110000>; 3525 hysteresis = <1000>; 3526 type = "critical"; 3527 }; 3528 }; 3529 3530 cooling-maps { 3531 map0 { 3532 trip = <&cpu2_alert0>; 3533 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3534 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3535 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3536 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3537 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3538 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3539 }; 3540 map1 { 3541 trip = <&cpu2_alert1>; 3542 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3543 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3544 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3545 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3546 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3547 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3548 }; 3549 }; 3550 }; 3551 3552 cpu3-thermal { 3553 polling-delay-passive = <0>; 3554 polling-delay = <0>; 3555 3556 thermal-sensors = <&tsens0 4>; 3557 sustainable-power = <768>; 3558 3559 trips { 3560 cpu3_alert0: trip-point0 { 3561 temperature = <90000>; 3562 hysteresis = <2000>; 3563 type = "passive"; 3564 }; 3565 3566 cpu3_alert1: trip-point1 { 3567 temperature = <95000>; 3568 hysteresis = <2000>; 3569 type = "passive"; 3570 }; 3571 3572 cpu3_crit: cpu_crit { 3573 temperature = <110000>; 3574 hysteresis = <1000>; 3575 type = "critical"; 3576 }; 3577 }; 3578 3579 cooling-maps { 3580 map0 { 3581 trip = <&cpu3_alert0>; 3582 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3583 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3584 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3585 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3586 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3587 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3588 }; 3589 map1 { 3590 trip = <&cpu3_alert1>; 3591 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3592 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3593 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3594 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3595 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3596 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3597 }; 3598 }; 3599 }; 3600 3601 cpu4-thermal { 3602 polling-delay-passive = <0>; 3603 polling-delay = <0>; 3604 3605 thermal-sensors = <&tsens0 5>; 3606 sustainable-power = <768>; 3607 3608 trips { 3609 cpu4_alert0: trip-point0 { 3610 temperature = <90000>; 3611 hysteresis = <2000>; 3612 type = "passive"; 3613 }; 3614 3615 cpu4_alert1: trip-point1 { 3616 temperature = <95000>; 3617 hysteresis = <2000>; 3618 type = "passive"; 3619 }; 3620 3621 cpu4_crit: cpu_crit { 3622 temperature = <110000>; 3623 hysteresis = <1000>; 3624 type = "critical"; 3625 }; 3626 }; 3627 3628 cooling-maps { 3629 map0 { 3630 trip = <&cpu4_alert0>; 3631 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3632 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3633 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3634 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3635 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3636 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3637 }; 3638 map1 { 3639 trip = <&cpu4_alert1>; 3640 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3641 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3642 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3643 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3644 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3645 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3646 }; 3647 }; 3648 }; 3649 3650 cpu5-thermal { 3651 polling-delay-passive = <0>; 3652 polling-delay = <0>; 3653 3654 thermal-sensors = <&tsens0 6>; 3655 sustainable-power = <768>; 3656 3657 trips { 3658 cpu5_alert0: trip-point0 { 3659 temperature = <90000>; 3660 hysteresis = <2000>; 3661 type = "passive"; 3662 }; 3663 3664 cpu5_alert1: trip-point1 { 3665 temperature = <95000>; 3666 hysteresis = <2000>; 3667 type = "passive"; 3668 }; 3669 3670 cpu5_crit: cpu_crit { 3671 temperature = <110000>; 3672 hysteresis = <1000>; 3673 type = "critical"; 3674 }; 3675 }; 3676 3677 cooling-maps { 3678 map0 { 3679 trip = <&cpu5_alert0>; 3680 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3681 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3682 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3683 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3684 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3685 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3686 }; 3687 map1 { 3688 trip = <&cpu5_alert1>; 3689 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3690 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3691 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3692 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3693 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3694 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3695 }; 3696 }; 3697 }; 3698 3699 cpu6-thermal { 3700 polling-delay-passive = <0>; 3701 polling-delay = <0>; 3702 3703 thermal-sensors = <&tsens0 9>; 3704 sustainable-power = <1202>; 3705 3706 trips { 3707 cpu6_alert0: trip-point0 { 3708 temperature = <90000>; 3709 hysteresis = <2000>; 3710 type = "passive"; 3711 }; 3712 3713 cpu6_alert1: trip-point1 { 3714 temperature = <95000>; 3715 hysteresis = <2000>; 3716 type = "passive"; 3717 }; 3718 3719 cpu6_crit: cpu_crit { 3720 temperature = <110000>; 3721 hysteresis = <1000>; 3722 type = "critical"; 3723 }; 3724 }; 3725 3726 cooling-maps { 3727 map0 { 3728 trip = <&cpu6_alert0>; 3729 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3730 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3731 }; 3732 map1 { 3733 trip = <&cpu6_alert1>; 3734 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3735 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3736 }; 3737 }; 3738 }; 3739 3740 cpu7-thermal { 3741 polling-delay-passive = <0>; 3742 polling-delay = <0>; 3743 3744 thermal-sensors = <&tsens0 10>; 3745 sustainable-power = <1202>; 3746 3747 trips { 3748 cpu7_alert0: trip-point0 { 3749 temperature = <90000>; 3750 hysteresis = <2000>; 3751 type = "passive"; 3752 }; 3753 3754 cpu7_alert1: trip-point1 { 3755 temperature = <95000>; 3756 hysteresis = <2000>; 3757 type = "passive"; 3758 }; 3759 3760 cpu7_crit: cpu_crit { 3761 temperature = <110000>; 3762 hysteresis = <1000>; 3763 type = "critical"; 3764 }; 3765 }; 3766 3767 cooling-maps { 3768 map0 { 3769 trip = <&cpu7_alert0>; 3770 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3771 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3772 }; 3773 map1 { 3774 trip = <&cpu7_alert1>; 3775 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3776 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3777 }; 3778 }; 3779 }; 3780 3781 cpu8-thermal { 3782 polling-delay-passive = <0>; 3783 polling-delay = <0>; 3784 3785 thermal-sensors = <&tsens0 11>; 3786 sustainable-power = <1202>; 3787 3788 trips { 3789 cpu8_alert0: trip-point0 { 3790 temperature = <90000>; 3791 hysteresis = <2000>; 3792 type = "passive"; 3793 }; 3794 3795 cpu8_alert1: trip-point1 { 3796 temperature = <95000>; 3797 hysteresis = <2000>; 3798 type = "passive"; 3799 }; 3800 3801 cpu8_crit: cpu_crit { 3802 temperature = <110000>; 3803 hysteresis = <1000>; 3804 type = "critical"; 3805 }; 3806 }; 3807 3808 cooling-maps { 3809 map0 { 3810 trip = <&cpu8_alert0>; 3811 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3812 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3813 }; 3814 map1 { 3815 trip = <&cpu8_alert1>; 3816 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3817 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3818 }; 3819 }; 3820 }; 3821 3822 cpu9-thermal { 3823 polling-delay-passive = <0>; 3824 polling-delay = <0>; 3825 3826 thermal-sensors = <&tsens0 12>; 3827 sustainable-power = <1202>; 3828 3829 trips { 3830 cpu9_alert0: trip-point0 { 3831 temperature = <90000>; 3832 hysteresis = <2000>; 3833 type = "passive"; 3834 }; 3835 3836 cpu9_alert1: trip-point1 { 3837 temperature = <95000>; 3838 hysteresis = <2000>; 3839 type = "passive"; 3840 }; 3841 3842 cpu9_crit: cpu_crit { 3843 temperature = <110000>; 3844 hysteresis = <1000>; 3845 type = "critical"; 3846 }; 3847 }; 3848 3849 cooling-maps { 3850 map0 { 3851 trip = <&cpu9_alert0>; 3852 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3853 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3854 }; 3855 map1 { 3856 trip = <&cpu9_alert1>; 3857 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3858 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3859 }; 3860 }; 3861 }; 3862 3863 aoss0-thermal { 3864 polling-delay-passive = <0>; 3865 polling-delay = <0>; 3866 3867 thermal-sensors = <&tsens0 0>; 3868 3869 trips { 3870 aoss0_alert0: trip-point0 { 3871 temperature = <90000>; 3872 hysteresis = <2000>; 3873 type = "hot"; 3874 }; 3875 3876 aoss0_crit: aoss0_crit { 3877 temperature = <110000>; 3878 hysteresis = <2000>; 3879 type = "critical"; 3880 }; 3881 }; 3882 }; 3883 3884 cpuss0-thermal { 3885 polling-delay-passive = <0>; 3886 polling-delay = <0>; 3887 3888 thermal-sensors = <&tsens0 7>; 3889 3890 trips { 3891 cpuss0_alert0: trip-point0 { 3892 temperature = <90000>; 3893 hysteresis = <2000>; 3894 type = "hot"; 3895 }; 3896 cpuss0_crit: cluster0_crit { 3897 temperature = <110000>; 3898 hysteresis = <2000>; 3899 type = "critical"; 3900 }; 3901 }; 3902 }; 3903 3904 cpuss1-thermal { 3905 polling-delay-passive = <0>; 3906 polling-delay = <0>; 3907 3908 thermal-sensors = <&tsens0 8>; 3909 3910 trips { 3911 cpuss1_alert0: trip-point0 { 3912 temperature = <90000>; 3913 hysteresis = <2000>; 3914 type = "hot"; 3915 }; 3916 cpuss1_crit: cluster0_crit { 3917 temperature = <110000>; 3918 hysteresis = <2000>; 3919 type = "critical"; 3920 }; 3921 }; 3922 }; 3923 3924 gpuss0-thermal { 3925 polling-delay-passive = <0>; 3926 polling-delay = <0>; 3927 3928 thermal-sensors = <&tsens0 13>; 3929 3930 trips { 3931 gpuss0_alert0: trip-point0 { 3932 temperature = <90000>; 3933 hysteresis = <2000>; 3934 type = "hot"; 3935 }; 3936 3937 gpuss0_crit: gpuss0_crit { 3938 temperature = <110000>; 3939 hysteresis = <2000>; 3940 type = "critical"; 3941 }; 3942 }; 3943 }; 3944 3945 gpuss1-thermal { 3946 polling-delay-passive = <0>; 3947 polling-delay = <0>; 3948 3949 thermal-sensors = <&tsens0 14>; 3950 3951 trips { 3952 gpuss1_alert0: trip-point0 { 3953 temperature = <90000>; 3954 hysteresis = <2000>; 3955 type = "hot"; 3956 }; 3957 3958 gpuss1_crit: gpuss1_crit { 3959 temperature = <110000>; 3960 hysteresis = <2000>; 3961 type = "critical"; 3962 }; 3963 }; 3964 }; 3965 3966 aoss1-thermal { 3967 polling-delay-passive = <0>; 3968 polling-delay = <0>; 3969 3970 thermal-sensors = <&tsens1 0>; 3971 3972 trips { 3973 aoss1_alert0: trip-point0 { 3974 temperature = <90000>; 3975 hysteresis = <2000>; 3976 type = "hot"; 3977 }; 3978 3979 aoss1_crit: aoss1_crit { 3980 temperature = <110000>; 3981 hysteresis = <2000>; 3982 type = "critical"; 3983 }; 3984 }; 3985 }; 3986 3987 cwlan-thermal { 3988 polling-delay-passive = <0>; 3989 polling-delay = <0>; 3990 3991 thermal-sensors = <&tsens1 1>; 3992 3993 trips { 3994 cwlan_alert0: trip-point0 { 3995 temperature = <90000>; 3996 hysteresis = <2000>; 3997 type = "hot"; 3998 }; 3999 4000 cwlan_crit: cwlan_crit { 4001 temperature = <110000>; 4002 hysteresis = <2000>; 4003 type = "critical"; 4004 }; 4005 }; 4006 }; 4007 4008 audio-thermal { 4009 polling-delay-passive = <0>; 4010 polling-delay = <0>; 4011 4012 thermal-sensors = <&tsens1 2>; 4013 4014 trips { 4015 audio_alert0: trip-point0 { 4016 temperature = <90000>; 4017 hysteresis = <2000>; 4018 type = "hot"; 4019 }; 4020 4021 audio_crit: audio_crit { 4022 temperature = <110000>; 4023 hysteresis = <2000>; 4024 type = "critical"; 4025 }; 4026 }; 4027 }; 4028 4029 ddr-thermal { 4030 polling-delay-passive = <0>; 4031 polling-delay = <0>; 4032 4033 thermal-sensors = <&tsens1 3>; 4034 4035 trips { 4036 ddr_alert0: trip-point0 { 4037 temperature = <90000>; 4038 hysteresis = <2000>; 4039 type = "hot"; 4040 }; 4041 4042 ddr_crit: ddr_crit { 4043 temperature = <110000>; 4044 hysteresis = <2000>; 4045 type = "critical"; 4046 }; 4047 }; 4048 }; 4049 4050 q6-hvx-thermal { 4051 polling-delay-passive = <0>; 4052 polling-delay = <0>; 4053 4054 thermal-sensors = <&tsens1 4>; 4055 4056 trips { 4057 q6_hvx_alert0: trip-point0 { 4058 temperature = <90000>; 4059 hysteresis = <2000>; 4060 type = "hot"; 4061 }; 4062 4063 q6_hvx_crit: q6_hvx_crit { 4064 temperature = <110000>; 4065 hysteresis = <2000>; 4066 type = "critical"; 4067 }; 4068 }; 4069 }; 4070 4071 camera-thermal { 4072 polling-delay-passive = <0>; 4073 polling-delay = <0>; 4074 4075 thermal-sensors = <&tsens1 5>; 4076 4077 trips { 4078 camera_alert0: trip-point0 { 4079 temperature = <90000>; 4080 hysteresis = <2000>; 4081 type = "hot"; 4082 }; 4083 4084 camera_crit: camera_crit { 4085 temperature = <110000>; 4086 hysteresis = <2000>; 4087 type = "critical"; 4088 }; 4089 }; 4090 }; 4091 4092 mdm-core-thermal { 4093 polling-delay-passive = <0>; 4094 polling-delay = <0>; 4095 4096 thermal-sensors = <&tsens1 6>; 4097 4098 trips { 4099 mdm_alert0: trip-point0 { 4100 temperature = <90000>; 4101 hysteresis = <2000>; 4102 type = "hot"; 4103 }; 4104 4105 mdm_crit: mdm_crit { 4106 temperature = <110000>; 4107 hysteresis = <2000>; 4108 type = "critical"; 4109 }; 4110 }; 4111 }; 4112 4113 mdm-dsp-thermal { 4114 polling-delay-passive = <0>; 4115 polling-delay = <0>; 4116 4117 thermal-sensors = <&tsens1 7>; 4118 4119 trips { 4120 mdm_dsp_alert0: trip-point0 { 4121 temperature = <90000>; 4122 hysteresis = <2000>; 4123 type = "hot"; 4124 }; 4125 4126 mdm_dsp_crit: mdm_dsp_crit { 4127 temperature = <110000>; 4128 hysteresis = <2000>; 4129 type = "critical"; 4130 }; 4131 }; 4132 }; 4133 4134 npu-thermal { 4135 polling-delay-passive = <0>; 4136 polling-delay = <0>; 4137 4138 thermal-sensors = <&tsens1 8>; 4139 4140 trips { 4141 npu_alert0: trip-point0 { 4142 temperature = <90000>; 4143 hysteresis = <2000>; 4144 type = "hot"; 4145 }; 4146 4147 npu_crit: npu_crit { 4148 temperature = <110000>; 4149 hysteresis = <2000>; 4150 type = "critical"; 4151 }; 4152 }; 4153 }; 4154 4155 video-thermal { 4156 polling-delay-passive = <0>; 4157 polling-delay = <0>; 4158 4159 thermal-sensors = <&tsens1 9>; 4160 4161 trips { 4162 video_alert0: trip-point0 { 4163 temperature = <90000>; 4164 hysteresis = <2000>; 4165 type = "hot"; 4166 }; 4167 4168 video_crit: video_crit { 4169 temperature = <110000>; 4170 hysteresis = <2000>; 4171 type = "critical"; 4172 }; 4173 }; 4174 }; 4175 }; 4176 4177 timer { 4178 compatible = "arm,armv8-timer"; 4179 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4180 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4181 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4182 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4183 }; 4184}; 4185