1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sdm660.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <19200000>; 24 clock-output-names = "xo_board"; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <32764>; 31 clock-output-names = "sleep_clk"; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@100 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x0 0x100>; 43 enable-method = "psci"; 44 cpu-idle-states = <&PERF_CPU_SLEEP_0 45 &PERF_CPU_SLEEP_1 46 &PERF_CLUSTER_SLEEP_0 47 &PERF_CLUSTER_SLEEP_1 48 &PERF_CLUSTER_SLEEP_2>; 49 capacity-dmips-mhz = <1126>; 50 #cooling-cells = <2>; 51 next-level-cache = <&L2_1>; 52 L2_1: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 }; 56 }; 57 58 CPU1: cpu@101 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53"; 61 reg = <0x0 0x101>; 62 enable-method = "psci"; 63 cpu-idle-states = <&PERF_CPU_SLEEP_0 64 &PERF_CPU_SLEEP_1 65 &PERF_CLUSTER_SLEEP_0 66 &PERF_CLUSTER_SLEEP_1 67 &PERF_CLUSTER_SLEEP_2>; 68 capacity-dmips-mhz = <1126>; 69 #cooling-cells = <2>; 70 next-level-cache = <&L2_1>; 71 }; 72 73 CPU2: cpu@102 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x0 0x102>; 77 enable-method = "psci"; 78 cpu-idle-states = <&PERF_CPU_SLEEP_0 79 &PERF_CPU_SLEEP_1 80 &PERF_CLUSTER_SLEEP_0 81 &PERF_CLUSTER_SLEEP_1 82 &PERF_CLUSTER_SLEEP_2>; 83 capacity-dmips-mhz = <1126>; 84 #cooling-cells = <2>; 85 next-level-cache = <&L2_1>; 86 }; 87 88 CPU3: cpu@103 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x0 0x103>; 92 enable-method = "psci"; 93 cpu-idle-states = <&PERF_CPU_SLEEP_0 94 &PERF_CPU_SLEEP_1 95 &PERF_CLUSTER_SLEEP_0 96 &PERF_CLUSTER_SLEEP_1 97 &PERF_CLUSTER_SLEEP_2>; 98 capacity-dmips-mhz = <1126>; 99 #cooling-cells = <2>; 100 next-level-cache = <&L2_1>; 101 }; 102 103 CPU4: cpu@0 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53"; 106 reg = <0x0 0x0>; 107 enable-method = "psci"; 108 cpu-idle-states = <&PWR_CPU_SLEEP_0 109 &PWR_CPU_SLEEP_1 110 &PWR_CLUSTER_SLEEP_0 111 &PWR_CLUSTER_SLEEP_1 112 &PWR_CLUSTER_SLEEP_2>; 113 capacity-dmips-mhz = <1024>; 114 #cooling-cells = <2>; 115 next-level-cache = <&L2_0>; 116 L2_0: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 }; 120 }; 121 122 CPU5: cpu@1 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53"; 125 reg = <0x0 0x1>; 126 enable-method = "psci"; 127 cpu-idle-states = <&PWR_CPU_SLEEP_0 128 &PWR_CPU_SLEEP_1 129 &PWR_CLUSTER_SLEEP_0 130 &PWR_CLUSTER_SLEEP_1 131 &PWR_CLUSTER_SLEEP_2>; 132 capacity-dmips-mhz = <1024>; 133 #cooling-cells = <2>; 134 next-level-cache = <&L2_0>; 135 }; 136 137 CPU6: cpu@2 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a53"; 140 reg = <0x0 0x2>; 141 enable-method = "psci"; 142 cpu-idle-states = <&PWR_CPU_SLEEP_0 143 &PWR_CPU_SLEEP_1 144 &PWR_CLUSTER_SLEEP_0 145 &PWR_CLUSTER_SLEEP_1 146 &PWR_CLUSTER_SLEEP_2>; 147 capacity-dmips-mhz = <1024>; 148 #cooling-cells = <2>; 149 next-level-cache = <&L2_0>; 150 }; 151 152 CPU7: cpu@3 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a53"; 155 reg = <0x0 0x3>; 156 enable-method = "psci"; 157 cpu-idle-states = <&PWR_CPU_SLEEP_0 158 &PWR_CPU_SLEEP_1 159 &PWR_CLUSTER_SLEEP_0 160 &PWR_CLUSTER_SLEEP_1 161 &PWR_CLUSTER_SLEEP_2>; 162 capacity-dmips-mhz = <1024>; 163 #cooling-cells = <2>; 164 next-level-cache = <&L2_0>; 165 }; 166 167 cpu-map { 168 cluster0 { 169 core0 { 170 cpu = <&CPU4>; 171 }; 172 173 core1 { 174 cpu = <&CPU5>; 175 }; 176 177 core2 { 178 cpu = <&CPU6>; 179 }; 180 181 core3 { 182 cpu = <&CPU7>; 183 }; 184 }; 185 186 cluster1 { 187 core0 { 188 cpu = <&CPU0>; 189 }; 190 191 core1 { 192 cpu = <&CPU1>; 193 }; 194 195 core2 { 196 cpu = <&CPU2>; 197 }; 198 199 core3 { 200 cpu = <&CPU3>; 201 }; 202 }; 203 }; 204 205 idle-states { 206 entry-method = "psci"; 207 208 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 209 compatible = "arm,idle-state"; 210 idle-state-name = "pwr-retention"; 211 arm,psci-suspend-param = <0x40000002>; 212 entry-latency-us = <338>; 213 exit-latency-us = <423>; 214 min-residency-us = <200>; 215 }; 216 217 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 218 compatible = "arm,idle-state"; 219 idle-state-name = "pwr-power-collapse"; 220 arm,psci-suspend-param = <0x40000003>; 221 entry-latency-us = <515>; 222 exit-latency-us = <1821>; 223 min-residency-us = <1000>; 224 local-timer-stop; 225 }; 226 227 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 228 compatible = "arm,idle-state"; 229 idle-state-name = "perf-retention"; 230 arm,psci-suspend-param = <0x40000002>; 231 entry-latency-us = <154>; 232 exit-latency-us = <87>; 233 min-residency-us = <200>; 234 }; 235 236 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 237 compatible = "arm,idle-state"; 238 idle-state-name = "perf-power-collapse"; 239 arm,psci-suspend-param = <0x40000003>; 240 entry-latency-us = <262>; 241 exit-latency-us = <301>; 242 min-residency-us = <1000>; 243 local-timer-stop; 244 }; 245 246 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 247 compatible = "arm,idle-state"; 248 idle-state-name = "pwr-cluster-dynamic-retention"; 249 arm,psci-suspend-param = <0x400000F2>; 250 entry-latency-us = <284>; 251 exit-latency-us = <384>; 252 min-residency-us = <9987>; 253 local-timer-stop; 254 }; 255 256 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 257 compatible = "arm,idle-state"; 258 idle-state-name = "pwr-cluster-retention"; 259 arm,psci-suspend-param = <0x400000F3>; 260 entry-latency-us = <338>; 261 exit-latency-us = <423>; 262 min-residency-us = <9987>; 263 local-timer-stop; 264 }; 265 266 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 267 compatible = "arm,idle-state"; 268 idle-state-name = "pwr-cluster-retention"; 269 arm,psci-suspend-param = <0x400000F4>; 270 entry-latency-us = <515>; 271 exit-latency-us = <1821>; 272 min-residency-us = <9987>; 273 local-timer-stop; 274 }; 275 276 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 277 compatible = "arm,idle-state"; 278 idle-state-name = "perf-cluster-dynamic-retention"; 279 arm,psci-suspend-param = <0x400000F2>; 280 entry-latency-us = <272>; 281 exit-latency-us = <329>; 282 min-residency-us = <9987>; 283 local-timer-stop; 284 }; 285 286 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 287 compatible = "arm,idle-state"; 288 idle-state-name = "perf-cluster-retention"; 289 arm,psci-suspend-param = <0x400000F3>; 290 entry-latency-us = <332>; 291 exit-latency-us = <368>; 292 min-residency-us = <9987>; 293 local-timer-stop; 294 }; 295 296 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 297 compatible = "arm,idle-state"; 298 idle-state-name = "perf-cluster-retention"; 299 arm,psci-suspend-param = <0x400000F4>; 300 entry-latency-us = <545>; 301 exit-latency-us = <1609>; 302 min-residency-us = <9987>; 303 local-timer-stop; 304 }; 305 }; 306 }; 307 308 firmware { 309 scm { 310 compatible = "qcom,scm-msm8998", "qcom,scm"; 311 }; 312 }; 313 314 memory { 315 device_type = "memory"; 316 /* We expect the bootloader to fill in the reg */ 317 reg = <0 0 0 0>; 318 }; 319 320 pmu { 321 compatible = "arm,armv8-pmuv3"; 322 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 323 }; 324 325 psci { 326 compatible = "arm,psci-1.0"; 327 method = "smc"; 328 }; 329 330 reserved-memory { 331 #address-cells = <2>; 332 #size-cells = <2>; 333 ranges; 334 335 wlan_msa_guard: wlan-msa-guard@85600000 { 336 reg = <0x0 0x85600000 0x0 0x100000>; 337 no-map; 338 }; 339 340 wlan_msa_mem: wlan-msa-mem@85700000 { 341 reg = <0x0 0x85700000 0x0 0x100000>; 342 no-map; 343 }; 344 345 qhee_code: qhee-code@85800000 { 346 reg = <0x0 0x85800000 0x0 0x600000>; 347 no-map; 348 }; 349 350 rmtfs_mem: memory@85e00000 { 351 compatible = "qcom,rmtfs-mem"; 352 reg = <0x0 0x85e00000 0x0 0x200000>; 353 no-map; 354 355 qcom,client-id = <1>; 356 qcom,vmid = <15>; 357 }; 358 359 smem_region: smem-mem@86000000 { 360 reg = <0 0x86000000 0 0x200000>; 361 no-map; 362 }; 363 364 tz_mem: memory@86200000 { 365 reg = <0x0 0x86200000 0x0 0x3300000>; 366 no-map; 367 }; 368 369 mpss_region: mpss@8ac00000 { 370 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 371 no-map; 372 }; 373 374 adsp_region: adsp@92a00000 { 375 reg = <0x0 0x92a00000 0x0 0x1e00000>; 376 no-map; 377 }; 378 379 mba_region: mba@94800000 { 380 reg = <0x0 0x94800000 0x0 0x200000>; 381 no-map; 382 }; 383 384 buffer_mem: tzbuffer@94a00000 { 385 reg = <0x0 0x94a00000 0x0 0x100000>; 386 no-map; 387 }; 388 389 venus_region: venus@9f800000 { 390 reg = <0x0 0x9f800000 0x0 0x800000>; 391 no-map; 392 }; 393 394 adsp_mem: adsp-region@f6000000 { 395 reg = <0x0 0xf6000000 0x0 0x800000>; 396 no-map; 397 }; 398 399 qseecom_mem: qseecom-region@f6800000 { 400 reg = <0x0 0xf6800000 0x0 0x1400000>; 401 no-map; 402 }; 403 404 zap_shader_region: gpu@fed00000 { 405 compatible = "shared-dma-pool"; 406 reg = <0x0 0xfed00000 0x0 0xa00000>; 407 no-map; 408 }; 409 }; 410 411 rpm-glink { 412 compatible = "qcom,glink-rpm"; 413 414 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 415 qcom,rpm-msg-ram = <&rpm_msg_ram>; 416 mboxes = <&apcs_glb 0>; 417 418 rpm_requests: rpm-requests { 419 compatible = "qcom,rpm-sdm660"; 420 qcom,glink-channels = "rpm_requests"; 421 422 rpmcc: clock-controller { 423 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 424 #clock-cells = <1>; 425 }; 426 }; 427 }; 428 429 smem: smem { 430 compatible = "qcom,smem"; 431 memory-region = <&smem_region>; 432 hwlocks = <&tcsr_mutex 3>; 433 }; 434 435 soc { 436 #address-cells = <1>; 437 #size-cells = <1>; 438 ranges = <0 0 0 0xffffffff>; 439 compatible = "simple-bus"; 440 441 gcc: clock-controller@100000 { 442 compatible = "qcom,gcc-sdm630"; 443 #clock-cells = <1>; 444 #reset-cells = <1>; 445 #power-domain-cells = <1>; 446 reg = <0x00100000 0x94000>; 447 448 clock-names = "xo", "sleep_clk"; 449 clocks = <&xo_board>, 450 <&sleep_clk>; 451 }; 452 453 rpm_msg_ram: memory@778000 { 454 compatible = "qcom,rpm-msg-ram"; 455 reg = <0x00778000 0x7000>; 456 }; 457 458 qfprom: qfprom@780000 { 459 compatible = "qcom,qfprom"; 460 reg = <0x00780000 0x621c>; 461 #address-cells = <1>; 462 #size-cells = <1>; 463 }; 464 465 rng: rng@793000 { 466 compatible = "qcom,prng-ee"; 467 reg = <0x00793000 0x1000>; 468 clocks = <&gcc GCC_PRNG_AHB_CLK>; 469 clock-names = "core"; 470 }; 471 472 restart@10ac000 { 473 compatible = "qcom,pshold"; 474 reg = <0x010ac000 0x4>; 475 }; 476 477 anoc2_smmu: iommu@16c0000 { 478 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 479 reg = <0x016c0000 0x40000>; 480 #iommu-cells = <1>; 481 482 #global-interrupts = <2>; 483 interrupts = 484 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 486 487 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 489 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 490 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 491 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 492 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 493 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 516 517 status = "disabled"; 518 }; 519 520 tcsr_mutex_regs: syscon@1f40000 { 521 compatible = "syscon"; 522 reg = <0x01f40000 0x20000>; 523 }; 524 525 tlmm: pinctrl@3100000 { 526 compatible = "qcom,sdm630-pinctrl"; 527 reg = <0x03100000 0x400000>, 528 <0x03500000 0x400000>, 529 <0x03900000 0x400000>; 530 reg-names = "south", "center", "north"; 531 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 532 gpio-controller; 533 gpio-ranges = <&tlmm 0 0 114>; 534 #gpio-cells = <2>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 538 blsp1_uart1_default: blsp1-uart1-default { 539 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 540 drive-strength = <2>; 541 bias-disable; 542 }; 543 544 blsp1_uart1_sleep: blsp1-uart1-sleep { 545 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 546 drive-strength = <2>; 547 bias-disable; 548 }; 549 550 blsp1_uart2_default: blsp1-uart2-default { 551 pins = "gpio4", "gpio5"; 552 drive-strength = <2>; 553 bias-disable; 554 }; 555 556 blsp2_uart1_default: blsp2-uart1-active { 557 tx-rts { 558 pins = "gpio16", "gpio19"; 559 function = "blsp_uart5"; 560 drive-strength = <2>; 561 bias-disable; 562 }; 563 564 rx { 565 /* 566 * Avoid garbage data while BT module 567 * is powered off or not driving signal 568 */ 569 pins = "gpio17"; 570 function = "blsp_uart5"; 571 drive-strength = <2>; 572 bias-pull-up; 573 }; 574 575 cts { 576 /* Match the pull of the BT module */ 577 pins = "gpio18"; 578 function = "blsp_uart5"; 579 drive-strength = <2>; 580 bias-pull-down; 581 }; 582 }; 583 584 blsp2_uart1_sleep: blsp2-uart1-sleep { 585 tx { 586 pins = "gpio16"; 587 function = "gpio"; 588 drive-strength = <2>; 589 bias-pull-up; 590 }; 591 592 rx-cts-rts { 593 pins = "gpio17", "gpio18", "gpio19"; 594 function = "gpio"; 595 drive-strength = <2>; 596 bias-no-pull; 597 }; 598 }; 599 600 i2c1_default: i2c1-default { 601 pins = "gpio2", "gpio3"; 602 drive-strength = <2>; 603 bias-disable; 604 }; 605 606 i2c1_sleep: i2c1-sleep { 607 pins = "gpio2", "gpio3"; 608 drive-strength = <2>; 609 bias-pull-up; 610 }; 611 612 i2c2_default: i2c2-default { 613 pins = "gpio6", "gpio7"; 614 drive-strength = <2>; 615 bias-disable; 616 }; 617 618 i2c2_sleep: i2c2-sleep { 619 pins = "gpio6", "gpio7"; 620 drive-strength = <2>; 621 bias-pull-up; 622 }; 623 624 i2c3_default: i2c3-default { 625 pins = "gpio10", "gpio11"; 626 drive-strength = <2>; 627 bias-disable; 628 }; 629 630 i2c3_sleep: i2c3-sleep { 631 pins = "gpio10", "gpio11"; 632 drive-strength = <2>; 633 bias-pull-up; 634 }; 635 636 i2c4_default: i2c4-default { 637 pins = "gpio14", "gpio15"; 638 drive-strength = <2>; 639 bias-disable; 640 }; 641 642 i2c4_sleep: i2c4-sleep { 643 pins = "gpio14", "gpio15"; 644 drive-strength = <2>; 645 bias-pull-up; 646 }; 647 648 i2c5_default: i2c5-default { 649 pins = "gpio18", "gpio19"; 650 drive-strength = <2>; 651 bias-disable; 652 }; 653 654 i2c5_sleep: i2c5-sleep { 655 pins = "gpio18", "gpio19"; 656 drive-strength = <2>; 657 bias-pull-up; 658 }; 659 660 i2c6_default: i2c6-default { 661 pins = "gpio22", "gpio23"; 662 drive-strength = <2>; 663 bias-disable; 664 }; 665 666 i2c6_sleep: i2c6-sleep { 667 pins = "gpio22", "gpio23"; 668 drive-strength = <2>; 669 bias-pull-up; 670 }; 671 672 i2c7_default: i2c7-default { 673 pins = "gpio26", "gpio27"; 674 drive-strength = <2>; 675 bias-disable; 676 }; 677 678 i2c7_sleep: i2c7-sleep { 679 pins = "gpio26", "gpio27"; 680 drive-strength = <2>; 681 bias-pull-up; 682 }; 683 684 i2c8_default: i2c8-default { 685 pins = "gpio30", "gpio31"; 686 drive-strength = <2>; 687 bias-disable; 688 }; 689 690 i2c8_sleep: i2c8-sleep { 691 pins = "gpio30", "gpio31"; 692 drive-strength = <2>; 693 bias-pull-up; 694 }; 695 696 sdc1_state_on: sdc1-on { 697 clk { 698 pins = "sdc1_clk"; 699 bias-disable; 700 drive-strength = <16>; 701 }; 702 703 cmd { 704 pins = "sdc1_cmd"; 705 bias-pull-up; 706 drive-strength = <10>; 707 }; 708 709 data { 710 pins = "sdc1_data"; 711 bias-pull-up; 712 drive-strength = <10>; 713 }; 714 715 rclk { 716 pins = "sdc1_rclk"; 717 bias-pull-down; 718 }; 719 }; 720 721 sdc1_state_off: sdc1-off { 722 clk { 723 pins = "sdc1_clk"; 724 bias-disable; 725 drive-strength = <2>; 726 }; 727 728 cmd { 729 pins = "sdc1_cmd"; 730 bias-pull-up; 731 drive-strength = <2>; 732 }; 733 734 data { 735 pins = "sdc1_data"; 736 bias-pull-up; 737 drive-strength = <2>; 738 }; 739 740 rclk { 741 pins = "sdc1_rclk"; 742 bias-pull-down; 743 }; 744 }; 745 746 sdc2_state_on: sdc2-on { 747 clk { 748 pins = "sdc2_clk"; 749 bias-disable; 750 drive-strength = <16>; 751 }; 752 753 cmd { 754 pins = "sdc2_cmd"; 755 bias-pull-up; 756 drive-strength = <10>; 757 }; 758 759 data { 760 pins = "sdc2_data"; 761 bias-pull-up; 762 drive-strength = <10>; 763 }; 764 765 sd-cd { 766 pins = "gpio54"; 767 bias-pull-up; 768 drive-strength = <2>; 769 }; 770 }; 771 772 sdc2_state_off: sdc2-off { 773 clk { 774 pins = "sdc2_clk"; 775 bias-disable; 776 drive-strength = <2>; 777 }; 778 779 cmd { 780 pins = "sdc2_cmd"; 781 bias-pull-up; 782 drive-strength = <2>; 783 }; 784 785 data { 786 pins = "sdc2_data"; 787 bias-pull-up; 788 drive-strength = <2>; 789 }; 790 791 sd-cd { 792 pins = "gpio54"; 793 bias-disable; 794 drive-strength = <2>; 795 }; 796 }; 797 }; 798 799 kgsl_smmu: iommu@5040000 { 800 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 801 reg = <0x05040000 0x10000>; 802 #iommu-cells = <1>; 803 804 #global-interrupts = <2>; 805 interrupts = 806 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 808 809 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 817 818 status = "disabled"; 819 }; 820 821 lpass_smmu: iommu@5100000 { 822 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 823 reg = <0x05100000 0x40000>; 824 #iommu-cells = <1>; 825 826 #global-interrupts = <2>; 827 interrupts = 828 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 830 831 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 848 849 status = "disabled"; 850 }; 851 852 spmi_bus: spmi@800f000 { 853 compatible = "qcom,spmi-pmic-arb"; 854 reg = <0x0800f000 0x1000>, 855 <0x08400000 0x1000000>, 856 <0x09400000 0x1000000>, 857 <0x0a400000 0x220000>, 858 <0x0800a000 0x3000>; 859 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 860 interrupt-names = "periph_irq"; 861 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 862 qcom,ee = <0>; 863 qcom,channel = <0>; 864 #address-cells = <2>; 865 #size-cells = <0>; 866 interrupt-controller; 867 #interrupt-cells = <4>; 868 cell-index = <0>; 869 }; 870 871 sdhc_1: sdhci@c0c4000 { 872 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 873 reg = <0x0c0c4000 0x1000>, 874 <0x0c0c5000 0x1000>; 875 reg-names = "hc", "cqhci"; 876 877 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 879 interrupt-names = "hc_irq", "pwr_irq"; 880 881 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 882 <&gcc GCC_SDCC1_AHB_CLK>, 883 <&xo_board>; 884 clock-names = "core", "iface", "xo"; 885 886 pinctrl-names = "default", "sleep"; 887 pinctrl-0 = <&sdc1_state_on>; 888 pinctrl-1 = <&sdc1_state_off>; 889 890 bus-width = <8>; 891 non-removable; 892 893 status = "disabled"; 894 }; 895 896 blsp1_dma: dma@c144000 { 897 compatible = "qcom,bam-v1.7.0"; 898 reg = <0x0c144000 0x1f000>; 899 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 901 clock-names = "bam_clk"; 902 #dma-cells = <1>; 903 qcom,ee = <0>; 904 qcom,controlled-remotely; 905 num-channels = <18>; 906 qcom,num-ees = <4>; 907 }; 908 909 blsp1_uart1: serial@c16f000 { 910 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 911 reg = <0x0c16f000 0x200>; 912 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 914 <&gcc GCC_BLSP1_AHB_CLK>; 915 clock-names = "core", "iface"; 916 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 917 dma-names = "tx", "rx"; 918 pinctrl-names = "default", "sleep"; 919 pinctrl-0 = <&blsp1_uart1_default>; 920 pinctrl-1 = <&blsp1_uart1_sleep>; 921 status = "disabled"; 922 }; 923 924 blsp1_uart2: serial@c170000 { 925 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 926 reg = <0x0c170000 0x1000>; 927 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 929 <&gcc GCC_BLSP1_AHB_CLK>; 930 clock-names = "core", "iface"; 931 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 932 dma-names = "tx", "rx"; 933 pinctrl-names = "default"; 934 pinctrl-0 = <&blsp1_uart2_default>; 935 status = "disabled"; 936 }; 937 938 blsp_i2c1: i2c@c175000 { 939 compatible = "qcom,i2c-qup-v2.2.1"; 940 reg = <0x0c175000 0x600>; 941 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 942 943 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 944 <&gcc GCC_BLSP1_AHB_CLK>; 945 clock-names = "core", "iface"; 946 clock-frequency = <400000>; 947 948 pinctrl-names = "default", "sleep"; 949 pinctrl-0 = <&i2c1_default>; 950 pinctrl-1 = <&i2c1_sleep>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 status = "disabled"; 954 }; 955 956 blsp_i2c2: i2c@c176000 { 957 compatible = "qcom,i2c-qup-v2.2.1"; 958 reg = <0x0c176000 0x600>; 959 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 960 961 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 962 <&gcc GCC_BLSP1_AHB_CLK>; 963 clock-names = "core", "iface"; 964 clock-frequency = <400000>; 965 966 pinctrl-names = "default", "sleep"; 967 pinctrl-0 = <&i2c2_default>; 968 pinctrl-1 = <&i2c2_sleep>; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 status = "disabled"; 972 }; 973 974 blsp_i2c3: i2c@c177000 { 975 compatible = "qcom,i2c-qup-v2.2.1"; 976 reg = <0x0c177000 0x600>; 977 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 978 979 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 980 <&gcc GCC_BLSP1_AHB_CLK>; 981 clock-names = "core", "iface"; 982 clock-frequency = <400000>; 983 984 pinctrl-names = "default", "sleep"; 985 pinctrl-0 = <&i2c3_default>; 986 pinctrl-1 = <&i2c3_sleep>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 }; 991 992 blsp_i2c4: i2c@c178000 { 993 compatible = "qcom,i2c-qup-v2.2.1"; 994 reg = <0x0c178000 0x600>; 995 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 996 997 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 998 <&gcc GCC_BLSP1_AHB_CLK>; 999 clock-names = "core", "iface"; 1000 clock-frequency = <400000>; 1001 1002 pinctrl-names = "default", "sleep"; 1003 pinctrl-0 = <&i2c4_default>; 1004 pinctrl-1 = <&i2c4_sleep>; 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 status = "disabled"; 1008 }; 1009 1010 blsp2_dma: dma@c184000 { 1011 compatible = "qcom,bam-v1.7.0"; 1012 reg = <0x0c184000 0x1f000>; 1013 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1015 clock-names = "bam_clk"; 1016 #dma-cells = <1>; 1017 qcom,ee = <0>; 1018 qcom,controlled-remotely; 1019 num-channels = <18>; 1020 qcom,num-ees = <4>; 1021 }; 1022 1023 blsp2_uart1: serial@c1af000 { 1024 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1025 reg = <0x0c1af000 0x200>; 1026 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1028 <&gcc GCC_BLSP2_AHB_CLK>; 1029 clock-names = "core", "iface"; 1030 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1031 dma-names = "tx", "rx"; 1032 pinctrl-names = "default", "sleep"; 1033 pinctrl-0 = <&blsp2_uart1_default>; 1034 pinctrl-1 = <&blsp2_uart1_sleep>; 1035 status = "disabled"; 1036 }; 1037 1038 blsp_i2c5: i2c@c1b5000 { 1039 compatible = "qcom,i2c-qup-v2.2.1"; 1040 reg = <0x0c1b5000 0x600>; 1041 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1042 1043 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1044 <&gcc GCC_BLSP2_AHB_CLK>; 1045 clock-names = "core", "iface"; 1046 clock-frequency = <400000>; 1047 1048 pinctrl-names = "default", "sleep"; 1049 pinctrl-0 = <&i2c5_default>; 1050 pinctrl-1 = <&i2c5_sleep>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 blsp_i2c6: i2c@c1b6000 { 1057 compatible = "qcom,i2c-qup-v2.2.1"; 1058 reg = <0x0c1b6000 0x600>; 1059 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1060 1061 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1062 <&gcc GCC_BLSP2_AHB_CLK>; 1063 clock-names = "core", "iface"; 1064 clock-frequency = <400000>; 1065 1066 pinctrl-names = "default", "sleep"; 1067 pinctrl-0 = <&i2c6_default>; 1068 pinctrl-1 = <&i2c6_sleep>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 status = "disabled"; 1072 }; 1073 1074 blsp_i2c7: i2c@c1b7000 { 1075 compatible = "qcom,i2c-qup-v2.2.1"; 1076 reg = <0x0c1b7000 0x600>; 1077 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1078 1079 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1080 <&gcc GCC_BLSP2_AHB_CLK>; 1081 clock-names = "core", "iface"; 1082 clock-frequency = <400000>; 1083 1084 pinctrl-names = "default", "sleep"; 1085 pinctrl-0 = <&i2c7_default>; 1086 pinctrl-1 = <&i2c7_sleep>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 status = "disabled"; 1090 }; 1091 1092 blsp_i2c8: i2c@c1b8000 { 1093 compatible = "qcom,i2c-qup-v2.2.1"; 1094 reg = <0x0c1b8000 0x600>; 1095 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1096 1097 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1098 <&gcc GCC_BLSP2_AHB_CLK>; 1099 clock-names = "core", "iface"; 1100 clock-frequency = <400000>; 1101 1102 pinctrl-names = "default", "sleep"; 1103 pinctrl-0 = <&i2c8_default>; 1104 pinctrl-1 = <&i2c8_sleep>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 mmss_smmu: iommu@cd00000 { 1111 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1112 reg = <0x0cd00000 0x40000>; 1113 #iommu-cells = <1>; 1114 1115 #global-interrupts = <2>; 1116 interrupts = 1117 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1119 1120 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 1144 1145 status = "disabled"; 1146 }; 1147 1148 apcs_glb: mailbox@17911000 { 1149 compatible = "qcom,sdm660-apcs-hmss-global"; 1150 reg = <0x17911000 0x1000>; 1151 1152 #mbox-cells = <1>; 1153 }; 1154 1155 timer@17920000 { 1156 #address-cells = <1>; 1157 #size-cells = <1>; 1158 ranges; 1159 compatible = "arm,armv7-timer-mem"; 1160 reg = <0x17920000 0x1000>; 1161 clock-frequency = <19200000>; 1162 1163 frame@17921000 { 1164 frame-number = <0>; 1165 interrupts = <0 8 0x4>, 1166 <0 7 0x4>; 1167 reg = <0x17921000 0x1000>, 1168 <0x17922000 0x1000>; 1169 }; 1170 1171 frame@17923000 { 1172 frame-number = <1>; 1173 interrupts = <0 9 0x4>; 1174 reg = <0x17923000 0x1000>; 1175 status = "disabled"; 1176 }; 1177 1178 frame@17924000 { 1179 frame-number = <2>; 1180 interrupts = <0 10 0x4>; 1181 reg = <0x17924000 0x1000>; 1182 status = "disabled"; 1183 }; 1184 1185 frame@17925000 { 1186 frame-number = <3>; 1187 interrupts = <0 11 0x4>; 1188 reg = <0x17925000 0x1000>; 1189 status = "disabled"; 1190 }; 1191 1192 frame@17926000 { 1193 frame-number = <4>; 1194 interrupts = <0 12 0x4>; 1195 reg = <0x17926000 0x1000>; 1196 status = "disabled"; 1197 }; 1198 1199 frame@17927000 { 1200 frame-number = <5>; 1201 interrupts = <0 13 0x4>; 1202 reg = <0x17927000 0x1000>; 1203 status = "disabled"; 1204 }; 1205 1206 frame@17928000 { 1207 frame-number = <6>; 1208 interrupts = <0 14 0x4>; 1209 reg = <0x17928000 0x1000>; 1210 status = "disabled"; 1211 }; 1212 }; 1213 1214 intc: interrupt-controller@17a00000 { 1215 compatible = "arm,gic-v3"; 1216 reg = <0x17a00000 0x10000>, /* GICD */ 1217 <0x17b00000 0x100000>; /* GICR * 8 */ 1218 #interrupt-cells = <3>; 1219 #address-cells = <1>; 1220 #size-cells = <1>; 1221 ranges; 1222 interrupt-controller; 1223 #redistributor-regions = <1>; 1224 redistributor-stride = <0x0 0x20000>; 1225 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1226 }; 1227 }; 1228 1229 tcsr_mutex: hwlock { 1230 compatible = "qcom,tcsr-mutex"; 1231 syscon = <&tcsr_mutex_regs 0 0x1000>; 1232 #hwlock-cells = <1>; 1233 }; 1234 1235 timer { 1236 compatible = "arm,armv8-timer"; 1237 interrupts = <GIC_PPI 1 0xf08>, 1238 <GIC_PPI 2 0xf08>, 1239 <GIC_PPI 3 0xf08>, 1240 <GIC_PPI 0 0xf08>; 1241 }; 1242}; 1243 1244