1 // SPDX-License-Identifier: GPL-2.0
2 /***************************************************************************/
3
4 /*
5 * m527x.c -- platform support for ColdFire 527x based boards
6 *
7 * Sub-architcture dependent initialization code for the Freescale
8 * 5270/5271 and 5274/5275 CPUs.
9 *
10 * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
11 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
12 */
13
14 /***************************************************************************/
15
16 #include <linux/kernel.h>
17 #include <linux/param.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <asm/machdep.h>
21 #include <asm/coldfire.h>
22 #include <asm/mcfsim.h>
23 #include <asm/mcfuart.h>
24 #include <asm/mcfclk.h>
25
26 /***************************************************************************/
27
28 DEFINE_CLK(pll, "pll.0", MCF_CLK);
29 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
30 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
31 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
32 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
33 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
34 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
35 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
36 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
37 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
38 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
39 DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
40 DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
41
42 struct clk *mcf_clks[] = {
43 &clk_pll,
44 &clk_sys,
45 &clk_mcfpit0,
46 &clk_mcfpit1,
47 &clk_mcfpit2,
48 &clk_mcfpit3,
49 &clk_mcfuart0,
50 &clk_mcfuart1,
51 &clk_mcfuart2,
52 &clk_mcfqspi0,
53 &clk_fec0,
54 &clk_fec1,
55 &clk_mcfi2c0,
56 NULL
57 };
58
59 /***************************************************************************/
60
m527x_qspi_init(void)61 static void __init m527x_qspi_init(void)
62 {
63 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
64 #if defined(CONFIG_M5271)
65 u16 par;
66
67 /* setup QSPS pins for QSPI with gpio CS control */
68 writeb(0x1f, MCFGPIO_PAR_QSPI);
69 /* and CS2 & CS3 as gpio */
70 par = readw(MCFGPIO_PAR_TIMER);
71 par &= 0x3f3f;
72 writew(par, MCFGPIO_PAR_TIMER);
73 #elif defined(CONFIG_M5275)
74 /* setup QSPS pins for QSPI with gpio CS control */
75 writew(0x003e, MCFGPIO_PAR_QSPI);
76 #endif
77 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
78 }
79
80 /***************************************************************************/
81
m527x_i2c_init(void)82 static void __init m527x_i2c_init(void)
83 {
84 #if IS_ENABLED(CONFIG_I2C_IMX)
85 #if defined(CONFIG_M5271)
86 u8 par;
87
88 /* setup Port FECI2C Pin Assignment Register for I2C */
89 /* set PAR_SCL to SCL and PAR_SDA to SDA */
90 par = readb(MCFGPIO_PAR_FECI2C);
91 par |= 0x0f;
92 writeb(par, MCFGPIO_PAR_FECI2C);
93 #elif defined(CONFIG_M5275)
94 u16 par;
95
96 /* setup Port FECI2C Pin Assignment Register for I2C */
97 /* set PAR_SCL to SCL and PAR_SDA to SDA */
98 par = readw(MCFGPIO_PAR_FECI2C);
99 par |= 0x0f;
100 writew(par, MCFGPIO_PAR_FECI2C);
101 #endif
102 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
103 }
104
105 /***************************************************************************/
106
m527x_uarts_init(void)107 static void __init m527x_uarts_init(void)
108 {
109 u16 sepmask;
110
111 /*
112 * External Pin Mask Setting & Enable External Pin for Interface
113 */
114 sepmask = readw(MCFGPIO_PAR_UART);
115 sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
116 writew(sepmask, MCFGPIO_PAR_UART);
117 }
118
119 /***************************************************************************/
120
m527x_fec_init(void)121 static void __init m527x_fec_init(void)
122 {
123 u8 v;
124
125 /* Set multi-function pins to ethernet mode for fec0 */
126 #if defined(CONFIG_M5271)
127 v = readb(MCFGPIO_PAR_FECI2C);
128 writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
129 #else
130 u16 par;
131
132 par = readw(MCFGPIO_PAR_FECI2C);
133 writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
134 v = readb(MCFGPIO_PAR_FEC0HL);
135 writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
136
137 /* Set multi-function pins to ethernet mode for fec1 */
138 par = readw(MCFGPIO_PAR_FECI2C);
139 writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
140 v = readb(MCFGPIO_PAR_FEC1HL);
141 writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
142 #endif
143 }
144
145 /***************************************************************************/
146
config_BSP(char * commandp,int size)147 void __init config_BSP(char *commandp, int size)
148 {
149 mach_sched_init = hw_timer_init;
150 m527x_uarts_init();
151 m527x_fec_init();
152 m527x_qspi_init();
153 m527x_i2c_init();
154 }
155
156 /***************************************************************************/
157