1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/ingenic,tcu.h> 3#include <dt-bindings/clock/x1830-cgu.h> 4#include <dt-bindings/dma/x1830-dma.h> 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "ingenic,x1830"; 10 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "ingenic,xburst-fpu2.0-mxu2.0"; 18 reg = <0>; 19 20 clocks = <&cgu X1830_CLK_CPU>; 21 clock-names = "cpu"; 22 }; 23 }; 24 25 cpuintc: interrupt-controller { 26 #address-cells = <0>; 27 #interrupt-cells = <1>; 28 interrupt-controller; 29 compatible = "mti,cpu-interrupt-controller"; 30 }; 31 32 intc: interrupt-controller@10001000 { 33 compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc"; 34 reg = <0x10001000 0x50>; 35 36 interrupt-controller; 37 #interrupt-cells = <1>; 38 39 interrupt-parent = <&cpuintc>; 40 interrupts = <2>; 41 }; 42 43 exclk: ext { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 }; 47 48 rtclk: rtc { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <32768>; 52 }; 53 54 cgu: x1830-cgu@10000000 { 55 compatible = "ingenic,x1830-cgu"; 56 reg = <0x10000000 0x100>; 57 58 #clock-cells = <1>; 59 60 clocks = <&exclk>, <&rtclk>; 61 clock-names = "ext", "rtc"; 62 }; 63 64 tcu: timer@10002000 { 65 compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd"; 66 reg = <0x10002000 0x1000>; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges = <0x0 0x10002000 0x1000>; 70 71 #clock-cells = <1>; 72 73 clocks = <&cgu X1830_CLK_RTCLK 74 &cgu X1830_CLK_EXCLK 75 &cgu X1830_CLK_PCLK>; 76 clock-names = "rtc", "ext", "pclk"; 77 78 interrupt-controller; 79 #interrupt-cells = <1>; 80 81 interrupt-parent = <&intc>; 82 interrupts = <27 26 25>; 83 84 wdt: watchdog@0 { 85 compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog"; 86 reg = <0x0 0x10>; 87 88 clocks = <&tcu TCU_CLK_WDT>; 89 clock-names = "wdt"; 90 }; 91 }; 92 93 rtc: rtc@10003000 { 94 compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc"; 95 reg = <0x10003000 0x4c>; 96 97 interrupt-parent = <&intc>; 98 interrupts = <32>; 99 100 clocks = <&cgu X1830_CLK_RTCLK>; 101 clock-names = "rtc"; 102 }; 103 104 pinctrl: pin-controller@10010000 { 105 compatible = "ingenic,x1830-pinctrl"; 106 reg = <0x10010000 0x800>; 107 #address-cells = <1>; 108 #size-cells = <0>; 109 110 gpa: gpio@0 { 111 compatible = "ingenic,x1830-gpio"; 112 reg = <0>; 113 114 gpio-controller; 115 gpio-ranges = <&pinctrl 0 0 32>; 116 #gpio-cells = <2>; 117 118 interrupt-controller; 119 #interrupt-cells = <2>; 120 121 interrupt-parent = <&intc>; 122 interrupts = <17>; 123 }; 124 125 gpb: gpio@1 { 126 compatible = "ingenic,x1830-gpio"; 127 reg = <1>; 128 129 gpio-controller; 130 gpio-ranges = <&pinctrl 0 32 32>; 131 #gpio-cells = <2>; 132 133 interrupt-controller; 134 #interrupt-cells = <2>; 135 136 interrupt-parent = <&intc>; 137 interrupts = <16>; 138 }; 139 140 gpc: gpio@2 { 141 compatible = "ingenic,x1830-gpio"; 142 reg = <2>; 143 144 gpio-controller; 145 gpio-ranges = <&pinctrl 0 64 32>; 146 #gpio-cells = <2>; 147 148 interrupt-controller; 149 #interrupt-cells = <2>; 150 151 interrupt-parent = <&intc>; 152 interrupts = <15>; 153 }; 154 155 gpd: gpio@3 { 156 compatible = "ingenic,x1830-gpio"; 157 reg = <3>; 158 159 gpio-controller; 160 gpio-ranges = <&pinctrl 0 96 32>; 161 #gpio-cells = <2>; 162 163 interrupt-controller; 164 #interrupt-cells = <2>; 165 166 interrupt-parent = <&intc>; 167 interrupts = <14>; 168 }; 169 }; 170 171 uart0: serial@10030000 { 172 compatible = "ingenic,x1830-uart", "ingenic,x1000-uart"; 173 reg = <0x10030000 0x100>; 174 175 interrupt-parent = <&intc>; 176 interrupts = <51>; 177 178 clocks = <&exclk>, <&cgu X1830_CLK_UART0>; 179 clock-names = "baud", "module"; 180 181 status = "disabled"; 182 }; 183 184 uart1: serial@10031000 { 185 compatible = "ingenic,x1830-uart", "ingenic,x1000-uart"; 186 reg = <0x10031000 0x100>; 187 188 interrupt-parent = <&intc>; 189 interrupts = <50>; 190 191 clocks = <&exclk>, <&cgu X1830_CLK_UART1>; 192 clock-names = "baud", "module"; 193 194 status = "disabled"; 195 }; 196 197 i2c0: i2c-controller@10050000 { 198 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; 199 reg = <0x10050000 0x1000>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 203 interrupt-parent = <&intc>; 204 interrupts = <60>; 205 206 clocks = <&cgu X1830_CLK_SMB0>; 207 208 status = "disabled"; 209 }; 210 211 i2c1: i2c-controller@10051000 { 212 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; 213 reg = <0x10051000 0x1000>; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 217 interrupt-parent = <&intc>; 218 interrupts = <59>; 219 220 clocks = <&cgu X1830_CLK_SMB1>; 221 222 status = "disabled"; 223 }; 224 225 i2c2: i2c-controller@10052000 { 226 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; 227 reg = <0x10052000 0x1000>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 231 interrupt-parent = <&intc>; 232 interrupts = <58>; 233 234 clocks = <&cgu X1830_CLK_SMB2>; 235 236 status = "disabled"; 237 }; 238 239 pdma: dma-controller@13420000 { 240 compatible = "ingenic,x1830-dma"; 241 reg = <0x13420000 0x400 242 0x13421000 0x40>; 243 #dma-cells = <2>; 244 245 interrupt-parent = <&intc>; 246 interrupts = <10>; 247 248 clocks = <&cgu X1830_CLK_PDMA>; 249 }; 250 251 msc0: mmc@13450000 { 252 compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc"; 253 reg = <0x13450000 0x1000>; 254 255 interrupt-parent = <&intc>; 256 interrupts = <37>; 257 258 clocks = <&cgu X1830_CLK_MSC0>; 259 clock-names = "mmc"; 260 261 cap-sd-highspeed; 262 cap-mmc-highspeed; 263 cap-sdio-irq; 264 265 dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>, 266 <&pdma X1830_DMA_MSC0_TX 0xffffffff>; 267 dma-names = "rx", "tx"; 268 269 status = "disabled"; 270 }; 271 272 msc1: mmc@13460000 { 273 compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc"; 274 reg = <0x13460000 0x1000>; 275 276 interrupt-parent = <&intc>; 277 interrupts = <36>; 278 279 clocks = <&cgu X1830_CLK_MSC1>; 280 clock-names = "mmc"; 281 282 cap-sd-highspeed; 283 cap-mmc-highspeed; 284 cap-sdio-irq; 285 286 dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>, 287 <&pdma X1830_DMA_MSC1_TX 0xffffffff>; 288 dma-names = "rx", "tx"; 289 290 status = "disabled"; 291 }; 292 293 mac: ethernet@134b0000 { 294 compatible = "ingenic,x1830-mac", "snps,dwmac"; 295 reg = <0x134b0000 0x2000>; 296 297 interrupt-parent = <&intc>; 298 interrupts = <55>; 299 interrupt-names = "macirq"; 300 301 clocks = <&cgu X1830_CLK_MAC>; 302 clock-names = "stmmaceth"; 303 304 status = "disabled"; 305 306 mdio: mdio { 307 compatible = "snps,dwmac-mdio"; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 311 status = "disabled"; 312 }; 313 }; 314}; 315