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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *
4  * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
5  * Copyright (C) 2011 Wind River Systems,
6  *   written by Ralf Baechle (ralf@linux-mips.org)
7  */
8 #include <linux/bug.h>
9 #include <linux/kernel.h>
10 #include <linux/mm.h>
11 #include <linux/memblock.h>
12 #include <linux/export.h>
13 #include <linux/init.h>
14 #include <linux/types.h>
15 #include <linux/pci.h>
16 #include <linux/of_address.h>
17 
18 #include <asm/cpu-info.h>
19 
20 /*
21  * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
22  * assignments.
23  */
24 
25 /*
26  * The PCI controller list.
27  */
28 static LIST_HEAD(controllers);
29 
30 static int pci_initialized;
31 
32 /*
33  * We need to avoid collisions with `mirrored' VGA ports
34  * and other strange ISA hardware, so we always want the
35  * addresses to be allocated in the 0x000-0x0ff region
36  * modulo 0x400.
37  *
38  * Why? Because some silly external IO cards only decode
39  * the low 10 bits of the IO address. The 0x00-0xff region
40  * is reserved for motherboard devices that decode all 16
41  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
42  * but we want to try to avoid allocating at 0x2900-0x2bff
43  * which might have be mirrored at 0x0100-0x03ff..
44  */
45 resource_size_t
pcibios_align_resource(void * data,const struct resource * res,resource_size_t size,resource_size_t align)46 pcibios_align_resource(void *data, const struct resource *res,
47 		       resource_size_t size, resource_size_t align)
48 {
49 	struct pci_dev *dev = data;
50 	struct pci_controller *hose = dev->sysdata;
51 	resource_size_t start = res->start;
52 
53 	if (res->flags & IORESOURCE_IO) {
54 		/* Make sure we start at our min on all hoses */
55 		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
56 			start = PCIBIOS_MIN_IO + hose->io_resource->start;
57 
58 		/*
59 		 * Put everything into 0x00-0xff region modulo 0x400
60 		 */
61 		if (start & 0x300)
62 			start = (start + 0x3ff) & ~0x3ff;
63 	} else if (res->flags & IORESOURCE_MEM) {
64 		/* Make sure we start at our min on all hoses */
65 		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
66 			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
67 	}
68 
69 	return start;
70 }
71 
pcibios_scanbus(struct pci_controller * hose)72 static void pcibios_scanbus(struct pci_controller *hose)
73 {
74 	static int next_busno;
75 	static int need_domain_info;
76 	LIST_HEAD(resources);
77 	struct pci_bus *bus;
78 	struct pci_host_bridge *bridge;
79 	int ret;
80 
81 	bridge = pci_alloc_host_bridge(0);
82 	if (!bridge)
83 		return;
84 
85 	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
86 		next_busno = (*hose->get_busno)();
87 
88 	pci_add_resource_offset(&resources,
89 				hose->mem_resource, hose->mem_offset);
90 	pci_add_resource_offset(&resources,
91 				hose->io_resource, hose->io_offset);
92 	pci_add_resource(&resources, hose->busn_resource);
93 	list_splice_init(&resources, &bridge->windows);
94 	bridge->dev.parent = NULL;
95 	bridge->sysdata = hose;
96 	bridge->busnr = next_busno;
97 	bridge->ops = hose->pci_ops;
98 	bridge->swizzle_irq = pci_common_swizzle;
99 	bridge->map_irq = pcibios_map_irq;
100 	ret = pci_scan_root_bus_bridge(bridge);
101 	if (ret) {
102 		pci_free_host_bridge(bridge);
103 		return;
104 	}
105 
106 	hose->bus = bus = bridge->bus;
107 
108 	need_domain_info = need_domain_info || pci_domain_nr(bus);
109 	set_pci_need_domain_info(hose, need_domain_info);
110 
111 	next_busno = bus->busn_res.end + 1;
112 	/* Don't allow 8-bit bus number overflow inside the hose -
113 	   reserve some space for bridges. */
114 	if (next_busno > 224) {
115 		next_busno = 0;
116 		need_domain_info = 1;
117 	}
118 
119 	/*
120 	 * We insert PCI resources into the iomem_resource and
121 	 * ioport_resource trees in either pci_bus_claim_resources()
122 	 * or pci_bus_assign_resources().
123 	 */
124 	if (pci_has_flag(PCI_PROBE_ONLY)) {
125 		pci_bus_claim_resources(bus);
126 	} else {
127 		struct pci_bus *child;
128 
129 		pci_bus_size_bridges(bus);
130 		pci_bus_assign_resources(bus);
131 		list_for_each_entry(child, &bus->children, node)
132 			pcie_bus_configure_settings(child);
133 	}
134 	pci_bus_add_devices(bus);
135 }
136 
137 #ifdef CONFIG_OF
pci_load_of_ranges(struct pci_controller * hose,struct device_node * node)138 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
139 {
140 	struct of_pci_range range;
141 	struct of_pci_range_parser parser;
142 
143 	pr_info("PCI host bridge %pOF ranges:\n", node);
144 	hose->of_node = node;
145 
146 	if (of_pci_range_parser_init(&parser, node))
147 		return;
148 
149 	for_each_of_pci_range(&parser, &range) {
150 		struct resource *res = NULL;
151 
152 		switch (range.flags & IORESOURCE_TYPE_BITS) {
153 		case IORESOURCE_IO:
154 			pr_info("  IO 0x%016llx..0x%016llx\n",
155 				range.cpu_addr,
156 				range.cpu_addr + range.size - 1);
157 			hose->io_map_base =
158 				(unsigned long)ioremap(range.cpu_addr,
159 						       range.size);
160 			res = hose->io_resource;
161 			break;
162 		case IORESOURCE_MEM:
163 			pr_info(" MEM 0x%016llx..0x%016llx\n",
164 				range.cpu_addr,
165 				range.cpu_addr + range.size - 1);
166 			res = hose->mem_resource;
167 			break;
168 		}
169 		if (res != NULL) {
170 			res->name = node->full_name;
171 			res->flags = range.flags;
172 			res->start = range.cpu_addr;
173 			res->end = range.cpu_addr + range.size - 1;
174 			res->parent = res->child = res->sibling = NULL;
175 		}
176 	}
177 }
178 
pcibios_get_phb_of_node(struct pci_bus * bus)179 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
180 {
181 	struct pci_controller *hose = bus->sysdata;
182 
183 	return of_node_get(hose->of_node);
184 }
185 #endif
186 
187 static DEFINE_MUTEX(pci_scan_mutex);
188 
register_pci_controller(struct pci_controller * hose)189 void register_pci_controller(struct pci_controller *hose)
190 {
191 	struct resource *parent;
192 
193 	parent = hose->mem_resource->parent;
194 	if (!parent)
195 		parent = &iomem_resource;
196 
197 	if (request_resource(parent, hose->mem_resource) < 0)
198 		goto out;
199 
200 	parent = hose->io_resource->parent;
201 	if (!parent)
202 		parent = &ioport_resource;
203 
204 	if (request_resource(parent, hose->io_resource) < 0) {
205 		release_resource(hose->mem_resource);
206 		goto out;
207 	}
208 
209 	INIT_LIST_HEAD(&hose->list);
210 	list_add_tail(&hose->list, &controllers);
211 
212 	/*
213 	 * Do not panic here but later - this might happen before console init.
214 	 */
215 	if (!hose->io_map_base) {
216 		printk(KERN_WARNING
217 		       "registering PCI controller with io_map_base unset\n");
218 	}
219 
220 	/*
221 	 * Scan the bus if it is register after the PCI subsystem
222 	 * initialization.
223 	 */
224 	if (pci_initialized) {
225 		mutex_lock(&pci_scan_mutex);
226 		pcibios_scanbus(hose);
227 		mutex_unlock(&pci_scan_mutex);
228 	}
229 
230 	return;
231 
232 out:
233 	printk(KERN_WARNING
234 	       "Skipping PCI bus scan due to resource conflict\n");
235 }
236 
pcibios_init(void)237 static int __init pcibios_init(void)
238 {
239 	struct pci_controller *hose;
240 
241 	/* Scan all of the recorded PCI controllers.  */
242 	list_for_each_entry(hose, &controllers, list)
243 		pcibios_scanbus(hose);
244 
245 	pci_initialized = 1;
246 
247 	return 0;
248 }
249 
250 subsys_initcall(pcibios_init);
251 
pcibios_enable_resources(struct pci_dev * dev,int mask)252 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
253 {
254 	u16 cmd, old_cmd;
255 	int idx;
256 	struct resource *r;
257 
258 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
259 	old_cmd = cmd;
260 	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
261 		/* Only set up the requested stuff */
262 		if (!(mask & (1<<idx)))
263 			continue;
264 
265 		r = &dev->resource[idx];
266 		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
267 			continue;
268 		if ((idx == PCI_ROM_RESOURCE) &&
269 				(!(r->flags & IORESOURCE_ROM_ENABLE)))
270 			continue;
271 		if (!r->start && r->end) {
272 			pci_err(dev,
273 				"can't enable device: resource collisions\n");
274 			return -EINVAL;
275 		}
276 		if (r->flags & IORESOURCE_IO)
277 			cmd |= PCI_COMMAND_IO;
278 		if (r->flags & IORESOURCE_MEM)
279 			cmd |= PCI_COMMAND_MEMORY;
280 	}
281 	if (cmd != old_cmd) {
282 		pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
283 		pci_write_config_word(dev, PCI_COMMAND, cmd);
284 	}
285 	return 0;
286 }
287 
pcibios_enable_device(struct pci_dev * dev,int mask)288 int pcibios_enable_device(struct pci_dev *dev, int mask)
289 {
290 	int err;
291 
292 	if ((err = pcibios_enable_resources(dev, mask)) < 0)
293 		return err;
294 
295 	return pcibios_plat_dev_init(dev);
296 }
297 
pcibios_fixup_bus(struct pci_bus * bus)298 void pcibios_fixup_bus(struct pci_bus *bus)
299 {
300 	struct pci_dev *dev = bus->self;
301 
302 	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
303 	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
304 		pci_read_bridge_bases(bus);
305 	}
306 }
307 
308 char * (*pcibios_plat_setup)(char *str) __initdata;
309 
pcibios_setup(char * str)310 char *__init pcibios_setup(char *str)
311 {
312 	if (pcibios_plat_setup)
313 		return pcibios_plat_setup(str);
314 	return str;
315 }
316