1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * This file contains the routines for initializing the MMU
4 * on the 4xx series of chips.
5 * -- paulus
6 *
7 * Derived from arch/ppc/mm/init.c:
8 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 *
10 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
11 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
12 * Copyright (C) 1996 Paul Mackerras
13 *
14 * Derived from "arch/i386/mm/init.c"
15 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
16 */
17
18 #include <linux/signal.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/types.h>
24 #include <linux/ptrace.h>
25 #include <linux/mman.h>
26 #include <linux/mm.h>
27 #include <linux/swap.h>
28 #include <linux/stddef.h>
29 #include <linux/vmalloc.h>
30 #include <linux/init.h>
31 #include <linux/delay.h>
32 #include <linux/highmem.h>
33 #include <linux/memblock.h>
34
35 #include <asm/prom.h>
36 #include <asm/io.h>
37 #include <asm/mmu_context.h>
38 #include <asm/mmu.h>
39 #include <linux/uaccess.h>
40 #include <asm/smp.h>
41 #include <asm/bootx.h>
42 #include <asm/machdep.h>
43 #include <asm/setup.h>
44
45 #include <mm/mmu_decl.h>
46
47 extern int __map_without_ltlbs;
48 /*
49 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
50 */
MMU_init_hw(void)51 void __init MMU_init_hw(void)
52 {
53 /*
54 * The Zone Protection Register (ZPR) defines how protection will
55 * be applied to every page which is a member of a given zone. At
56 * present, we utilize only two of the 4xx's zones.
57 * The zone index bits (of ZSEL) in the PTE are used for software
58 * indicators, except the LSB. For user access, zone 1 is used,
59 * for kernel access, zone 0 is used. We set all but zone 1
60 * to zero, allowing only kernel access as indicated in the PTE.
61 * For zone 1, we set a 01 binary (a value of 10 will not work)
62 * to allow user access as indicated in the PTE. This also allows
63 * kernel access as indicated in the PTE.
64 */
65
66 mtspr(SPRN_ZPR, 0x10000000);
67
68 flush_instruction_cache();
69
70 /*
71 * Set up the real-mode cache parameters for the exception vector
72 * handlers (which are run in real-mode).
73 */
74
75 mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */
76
77 /*
78 * Cache instruction and data space where the exception
79 * vectors and the kernel live in real-mode.
80 */
81
82 mtspr(SPRN_DCCR, 0xFFFF0000); /* 2GByte of data space at 0x0. */
83 mtspr(SPRN_ICCR, 0xFFFF0000); /* 2GByte of instr. space at 0x0. */
84 }
85
86 #define LARGE_PAGE_SIZE_16M (1<<24)
87 #define LARGE_PAGE_SIZE_4M (1<<22)
88
mmu_mapin_ram(unsigned long base,unsigned long top)89 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
90 {
91 unsigned long v, s, mapped;
92 phys_addr_t p;
93
94 v = KERNELBASE;
95 p = 0;
96 s = total_lowmem;
97
98 if (__map_without_ltlbs)
99 return 0;
100
101 while (s >= LARGE_PAGE_SIZE_16M) {
102 pmd_t *pmdp;
103 unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_RW;
104
105 pmdp = pmd_off_k(v);
106 *pmdp++ = __pmd(val);
107 *pmdp++ = __pmd(val);
108 *pmdp++ = __pmd(val);
109 *pmdp++ = __pmd(val);
110
111 v += LARGE_PAGE_SIZE_16M;
112 p += LARGE_PAGE_SIZE_16M;
113 s -= LARGE_PAGE_SIZE_16M;
114 }
115
116 while (s >= LARGE_PAGE_SIZE_4M) {
117 pmd_t *pmdp;
118 unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_RW;
119
120 pmdp = pmd_off_k(v);
121 *pmdp = __pmd(val);
122
123 v += LARGE_PAGE_SIZE_4M;
124 p += LARGE_PAGE_SIZE_4M;
125 s -= LARGE_PAGE_SIZE_4M;
126 }
127
128 mapped = total_lowmem - s;
129
130 /* If the size of RAM is not an exact power of two, we may not
131 * have covered RAM in its entirety with 16 and 4 MiB
132 * pages. Consequently, restrict the top end of RAM currently
133 * allocable so that calls to the MEMBLOCK to allocate PTEs for "tail"
134 * coverage with normal-sized pages (or other reasons) do not
135 * attempt to allocate outside the allowed range.
136 */
137 memblock_set_current_limit(mapped);
138
139 return mapped;
140 }
141
setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)142 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
143 phys_addr_t first_memblock_size)
144 {
145 /* We don't currently support the first MEMBLOCK not mapping 0
146 * physical on those processors
147 */
148 BUG_ON(first_memblock_base != 0);
149
150 /* 40x can only access 16MB at the moment (see head_40x.S) */
151 memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
152 }
153