1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC8610 HPCD board specific routines
4 *
5 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
6 * Recode: Jason Jin <jason.jin@freescale.com>
7 * York Sun <yorksun@freescale.com>
8 *
9 * Rewrite the interrupt routing. remove the 8259PIC support,
10 * All the integrated device in ULI use sideband interrupt.
11 *
12 * Copyright 2008 Freescale Semiconductor Inc.
13 */
14
15 #include <linux/stddef.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/interrupt.h>
19 #include <linux/kdev_t.h>
20 #include <linux/delay.h>
21 #include <linux/seq_file.h>
22 #include <linux/of.h>
23 #include <linux/fsl/guts.h>
24
25 #include <asm/time.h>
26 #include <asm/machdep.h>
27 #include <asm/pci-bridge.h>
28 #include <asm/prom.h>
29 #include <mm/mmu_decl.h>
30 #include <asm/udbg.h>
31
32 #include <asm/mpic.h>
33
34 #include <linux/of_platform.h>
35 #include <sysdev/fsl_pci.h>
36 #include <sysdev/fsl_soc.h>
37
38 #include "mpc86xx.h"
39
40 static struct device_node *pixis_node;
41 static unsigned char *pixis_bdcfg0, *pixis_arch;
42
43 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
44 #define CLKDVDR_PXCKEN 0x80000000
45 #define CLKDVDR_PXCKINV 0x10000000
46 #define CLKDVDR_PXCKDLY 0x06000000
47 #define CLKDVDR_PXCLK_MASK 0x001F0000
48
49 #ifdef CONFIG_SUSPEND
mpc8610_sw9_irq(int irq,void * data)50 static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
51 {
52 pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
53 return IRQ_HANDLED;
54 }
55
mpc8610_suspend_init(void)56 static void __init mpc8610_suspend_init(void)
57 {
58 int irq;
59 int ret;
60
61 if (!pixis_node)
62 return;
63
64 irq = irq_of_parse_and_map(pixis_node, 0);
65 if (!irq) {
66 pr_err("%s: can't map pixis event IRQ.\n", __func__);
67 return;
68 }
69
70 ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL);
71 if (ret) {
72 pr_err("%s: can't request pixis event IRQ: %d\n",
73 __func__, ret);
74 irq_dispose_mapping(irq);
75 }
76
77 enable_irq_wake(irq);
78 }
79 #else
mpc8610_suspend_init(void)80 static inline void mpc8610_suspend_init(void) { }
81 #endif /* CONFIG_SUSPEND */
82
83 static const struct of_device_id mpc8610_ids[] __initconst = {
84 { .compatible = "fsl,mpc8610-immr", },
85 { .compatible = "fsl,mpc8610-guts", },
86 /* So that the DMA channel nodes can be probed individually: */
87 { .compatible = "fsl,eloplus-dma", },
88 /* PCI controllers */
89 { .compatible = "fsl,mpc8610-pci", },
90 {}
91 };
92
mpc8610_declare_of_platform_devices(void)93 static int __init mpc8610_declare_of_platform_devices(void)
94 {
95 /* Enable wakeup on PIXIS' event IRQ. */
96 mpc8610_suspend_init();
97
98 mpc86xx_common_publish_devices();
99
100 /* Without this call, the SSI device driver won't get probed. */
101 of_platform_bus_probe(NULL, mpc8610_ids, NULL);
102
103 return 0;
104 }
105 machine_arch_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
106
107 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
108
109 /*
110 * DIU Area Descriptor
111 *
112 * The MPC8610 reference manual shows the bits of the AD register in
113 * little-endian order, which causes the BLUE_C field to be split into two
114 * parts. To simplify the definition of the MAKE_AD() macro, we define the
115 * fields in big-endian order and byte-swap the result.
116 *
117 * So even though the registers don't look like they're in the
118 * same bit positions as they are on the P1022, the same value is written to
119 * the AD register on the MPC8610 and on the P1022.
120 */
121 #define AD_BYTE_F 0x10000000
122 #define AD_ALPHA_C_MASK 0x0E000000
123 #define AD_ALPHA_C_SHIFT 25
124 #define AD_BLUE_C_MASK 0x01800000
125 #define AD_BLUE_C_SHIFT 23
126 #define AD_GREEN_C_MASK 0x00600000
127 #define AD_GREEN_C_SHIFT 21
128 #define AD_RED_C_MASK 0x00180000
129 #define AD_RED_C_SHIFT 19
130 #define AD_PALETTE 0x00040000
131 #define AD_PIXEL_S_MASK 0x00030000
132 #define AD_PIXEL_S_SHIFT 16
133 #define AD_COMP_3_MASK 0x0000F000
134 #define AD_COMP_3_SHIFT 12
135 #define AD_COMP_2_MASK 0x00000F00
136 #define AD_COMP_2_SHIFT 8
137 #define AD_COMP_1_MASK 0x000000F0
138 #define AD_COMP_1_SHIFT 4
139 #define AD_COMP_0_MASK 0x0000000F
140 #define AD_COMP_0_SHIFT 0
141
142 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
143 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
144 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
145 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
146 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
147 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
148
mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port,unsigned int bits_per_pixel)149 u32 mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port,
150 unsigned int bits_per_pixel)
151 {
152 static const u32 pixelformat[][3] = {
153 {
154 MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
155 MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
156 MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0)
157 },
158 {
159 MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8),
160 MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0),
161 MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0)
162 },
163 };
164 unsigned int arch_monitor;
165
166 /* The DVI port is mis-wired on revision 1 of this board. */
167 arch_monitor =
168 ((*pixis_arch == 0x01) && (port == FSL_DIU_PORT_DVI)) ? 0 : 1;
169
170 switch (bits_per_pixel) {
171 case 32:
172 return pixelformat[arch_monitor][0];
173 case 24:
174 return pixelformat[arch_monitor][1];
175 case 16:
176 return pixelformat[arch_monitor][2];
177 default:
178 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
179 return 0;
180 }
181 }
182
mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port,char * gamma_table_base)183 void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port,
184 char *gamma_table_base)
185 {
186 int i;
187 if (port == FSL_DIU_PORT_DLVDS) {
188 for (i = 0; i < 256*3; i++)
189 gamma_table_base[i] = (gamma_table_base[i] << 2) |
190 ((gamma_table_base[i] >> 6) & 0x03);
191 }
192 }
193
194 #define PX_BRDCFG0_DVISEL (1 << 3)
195 #define PX_BRDCFG0_DLINK (1 << 4)
196 #define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
197
mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)198 void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)
199 {
200 switch (port) {
201 case FSL_DIU_PORT_DVI:
202 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
203 PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK);
204 break;
205 case FSL_DIU_PORT_LVDS:
206 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
207 PX_BRDCFG0_DLINK);
208 break;
209 case FSL_DIU_PORT_DLVDS:
210 clrbits8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK);
211 break;
212 }
213 }
214
215 /**
216 * mpc8610hpcd_set_pixel_clock: program the DIU's clock
217 *
218 * @pixclock: the wavelength, in picoseconds, of the clock
219 */
mpc8610hpcd_set_pixel_clock(unsigned int pixclock)220 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
221 {
222 struct device_node *guts_np = NULL;
223 struct ccsr_guts __iomem *guts;
224 unsigned long freq;
225 u64 temp;
226 u32 pxclk;
227
228 /* Map the global utilities registers. */
229 guts_np = of_find_compatible_node(NULL, NULL, "fsl,mpc8610-guts");
230 if (!guts_np) {
231 pr_err("mpc8610hpcd: missing global utilities device node\n");
232 return;
233 }
234
235 guts = of_iomap(guts_np, 0);
236 of_node_put(guts_np);
237 if (!guts) {
238 pr_err("mpc8610hpcd: could not map global utilities device\n");
239 return;
240 }
241
242 /* Convert pixclock from a wavelength to a frequency */
243 temp = 1000000000000ULL;
244 do_div(temp, pixclock);
245 freq = temp;
246
247 /*
248 * 'pxclk' is the ratio of the platform clock to the pixel clock.
249 * On the MPC8610, the value programmed into CLKDVDR is the ratio
250 * minus one. The valid range of values is 2-31.
251 */
252 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq) - 1;
253 pxclk = clamp_t(u32, pxclk, 2, 31);
254
255 /* Disable the pixel clock, and set it to non-inverted and no delay */
256 clrbits32(&guts->clkdvdr,
257 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
258
259 /* Enable the clock and set the pxclk */
260 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
261
262 iounmap(guts);
263 }
264
265 enum fsl_diu_monitor_port
mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)266 mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
267 {
268 return port;
269 }
270
271 #endif
272
mpc86xx_hpcd_setup_arch(void)273 static void __init mpc86xx_hpcd_setup_arch(void)
274 {
275 struct resource r;
276 unsigned char *pixis;
277
278 if (ppc_md.progress)
279 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
280
281 fsl_pci_assign_primary();
282
283 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
284 diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
285 diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
286 diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
287 diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
288 diu_ops.valid_monitor_port = mpc8610hpcd_valid_monitor_port;
289 #endif
290
291 pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
292 if (pixis_node) {
293 of_address_to_resource(pixis_node, 0, &r);
294 of_node_put(pixis_node);
295 pixis = ioremap(r.start, 32);
296 if (!pixis) {
297 printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
298 return;
299 }
300 pixis_bdcfg0 = pixis + 8;
301 pixis_arch = pixis + 1;
302 } else
303 printk(KERN_ERR "Err: "
304 "can't find device node 'fsl,fpga-pixis'\n");
305
306 printk("MPC86xx HPCD board from Freescale Semiconductor\n");
307 }
308
309 /*
310 * Called very early, device-tree isn't unflattened
311 */
mpc86xx_hpcd_probe(void)312 static int __init mpc86xx_hpcd_probe(void)
313 {
314 if (of_machine_is_compatible("fsl,MPC8610HPCD"))
315 return 1; /* Looks good */
316
317 return 0;
318 }
319
define_machine(mpc86xx_hpcd)320 define_machine(mpc86xx_hpcd) {
321 .name = "MPC86xx HPCD",
322 .probe = mpc86xx_hpcd_probe,
323 .setup_arch = mpc86xx_hpcd_setup_arch,
324 .init_IRQ = mpc86xx_init_irq,
325 .get_irq = mpic_get_irq,
326 .time_init = mpc86xx_time_init,
327 .calibrate_decr = generic_calibrate_decr,
328 .progress = udbg_progress,
329 #ifdef CONFIG_PCI
330 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
331 #endif
332 };
333