1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright 2007, Olof Johansson, PA Semi
4 *
5 * Based on arch/powerpc/sysdev/mpic_u3msi.c:
6 *
7 * Copyright 2006, Segher Boessenkool, IBM Corporation.
8 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
9 */
10
11 #include <linux/irq.h>
12 #include <linux/msi.h>
13 #include <asm/mpic.h>
14 #include <asm/prom.h>
15 #include <asm/hw_irq.h>
16 #include <asm/ppc-pci.h>
17 #include <asm/msi_bitmap.h>
18
19 #include <sysdev/mpic.h>
20
21 /* Allocate 16 interrupts per device, to give an alignment of 16,
22 * since that's the size of the grouping w.r.t. affinity. If someone
23 * needs more than 32 MSI's down the road we'll have to rethink this,
24 * but it should be OK for now.
25 */
26 #define ALLOC_CHUNK 16
27
28 #define PASEMI_MSI_ADDR 0xfc080000
29
30 /* A bit ugly, can we get this from the pci_dev somehow? */
31 static struct mpic *msi_mpic;
32
33
mpic_pasemi_msi_mask_irq(struct irq_data * data)34 static void mpic_pasemi_msi_mask_irq(struct irq_data *data)
35 {
36 pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq);
37 pci_msi_mask_irq(data);
38 mpic_mask_irq(data);
39 }
40
mpic_pasemi_msi_unmask_irq(struct irq_data * data)41 static void mpic_pasemi_msi_unmask_irq(struct irq_data *data)
42 {
43 pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq);
44 mpic_unmask_irq(data);
45 pci_msi_unmask_irq(data);
46 }
47
48 static struct irq_chip mpic_pasemi_msi_chip = {
49 .irq_shutdown = mpic_pasemi_msi_mask_irq,
50 .irq_mask = mpic_pasemi_msi_mask_irq,
51 .irq_unmask = mpic_pasemi_msi_unmask_irq,
52 .irq_eoi = mpic_end_irq,
53 .irq_set_type = mpic_set_irq_type,
54 .irq_set_affinity = mpic_set_affinity,
55 .name = "PASEMI-MSI",
56 };
57
pasemi_msi_teardown_msi_irqs(struct pci_dev * pdev)58 static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
59 {
60 struct msi_desc *entry;
61 irq_hw_number_t hwirq;
62
63 pr_debug("pasemi_msi_teardown_msi_irqs, pdev %p\n", pdev);
64
65 for_each_pci_msi_entry(entry, pdev) {
66 if (!entry->irq)
67 continue;
68
69 hwirq = virq_to_hw(entry->irq);
70 irq_set_msi_desc(entry->irq, NULL);
71 irq_dispose_mapping(entry->irq);
72 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, ALLOC_CHUNK);
73 }
74
75 return;
76 }
77
pasemi_msi_setup_msi_irqs(struct pci_dev * pdev,int nvec,int type)78 static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
79 {
80 unsigned int virq;
81 struct msi_desc *entry;
82 struct msi_msg msg;
83 int hwirq;
84
85 if (type == PCI_CAP_ID_MSIX)
86 pr_debug("pasemi_msi: MSI-X untested, trying anyway\n");
87 pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n",
88 pdev, nvec, type);
89
90 msg.address_hi = 0;
91 msg.address_lo = PASEMI_MSI_ADDR;
92
93 for_each_pci_msi_entry(entry, pdev) {
94 /* Allocate 16 interrupts for now, since that's the grouping for
95 * affinity. This can be changed later if it turns out 32 is too
96 * few MSIs for someone, but restrictions will apply to how the
97 * sources can be changed independently.
98 */
99 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap,
100 ALLOC_CHUNK);
101 if (hwirq < 0) {
102 pr_debug("pasemi_msi: failed allocating hwirq\n");
103 return hwirq;
104 }
105
106 virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
107 if (!virq) {
108 pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n",
109 hwirq);
110 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq,
111 ALLOC_CHUNK);
112 return -ENOSPC;
113 }
114
115 /* Vector on MSI is really an offset, the hardware adds
116 * it to the value written at the magic address. So set
117 * it to 0 to remain sane.
118 */
119 mpic_set_vector(virq, 0);
120
121 irq_set_msi_desc(virq, entry);
122 irq_set_chip(virq, &mpic_pasemi_msi_chip);
123 irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
124
125 pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
126 "addr 0x%x\n", virq, hwirq, msg.address_lo);
127
128 /* Likewise, the device writes [0...511] into the target
129 * register to generate MSI [512...1023]
130 */
131 msg.data = hwirq-0x200;
132 pci_write_msi_msg(virq, &msg);
133 }
134
135 return 0;
136 }
137
mpic_pasemi_msi_init(struct mpic * mpic)138 int mpic_pasemi_msi_init(struct mpic *mpic)
139 {
140 int rc;
141 struct pci_controller *phb;
142 struct device_node *of_node;
143
144 of_node = irq_domain_get_of_node(mpic->irqhost);
145 if (!of_node ||
146 !of_device_is_compatible(of_node,
147 "pasemi,pwrficient-openpic"))
148 return -ENODEV;
149
150 rc = mpic_msi_init_allocator(mpic);
151 if (rc) {
152 pr_debug("pasemi_msi: Error allocating bitmap!\n");
153 return rc;
154 }
155
156 pr_debug("pasemi_msi: Registering PA Semi MPIC MSI callbacks\n");
157
158 msi_mpic = mpic;
159 list_for_each_entry(phb, &hose_list, list_node) {
160 WARN_ON(phb->controller_ops.setup_msi_irqs);
161 phb->controller_ops.setup_msi_irqs = pasemi_msi_setup_msi_irqs;
162 phb->controller_ops.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs;
163 }
164
165 return 0;
166 }
167