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1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_IO_APIC_H
3 #define _ASM_X86_IO_APIC_H
4 
5 #include <linux/types.h>
6 #include <asm/mpspec.h>
7 #include <asm/apicdef.h>
8 #include <asm/irq_vectors.h>
9 #include <asm/x86_init.h>
10 /*
11  * Intel IO-APIC support for SMP and UP systems.
12  *
13  * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
14  */
15 
16 /* I/O Unit Redirection Table */
17 #define IO_APIC_REDIR_VECTOR_MASK	0x000FF
18 #define IO_APIC_REDIR_DEST_LOGICAL	0x00800
19 #define IO_APIC_REDIR_DEST_PHYSICAL	0x00000
20 #define IO_APIC_REDIR_SEND_PENDING	(1 << 12)
21 #define IO_APIC_REDIR_REMOTE_IRR	(1 << 14)
22 #define IO_APIC_REDIR_LEVEL_TRIGGER	(1 << 15)
23 #define IO_APIC_REDIR_MASKED		(1 << 16)
24 
25 /*
26  * The structure of the IO-APIC:
27  */
28 union IO_APIC_reg_00 {
29 	u32	raw;
30 	struct {
31 		u32	__reserved_2	: 14,
32 			LTS		:  1,
33 			delivery_type	:  1,
34 			__reserved_1	:  8,
35 			ID		:  8;
36 	} __attribute__ ((packed)) bits;
37 };
38 
39 union IO_APIC_reg_01 {
40 	u32	raw;
41 	struct {
42 		u32	version		:  8,
43 			__reserved_2	:  7,
44 			PRQ		:  1,
45 			entries		:  8,
46 			__reserved_1	:  8;
47 	} __attribute__ ((packed)) bits;
48 };
49 
50 union IO_APIC_reg_02 {
51 	u32	raw;
52 	struct {
53 		u32	__reserved_2	: 24,
54 			arbitration	:  4,
55 			__reserved_1	:  4;
56 	} __attribute__ ((packed)) bits;
57 };
58 
59 union IO_APIC_reg_03 {
60 	u32	raw;
61 	struct {
62 		u32	boot_DT		:  1,
63 			__reserved_1	: 31;
64 	} __attribute__ ((packed)) bits;
65 };
66 
67 struct IO_APIC_route_entry {
68 	__u32	vector		:  8,
69 		delivery_mode	:  3,	/* 000: FIXED
70 					 * 001: lowest prio
71 					 * 111: ExtINT
72 					 */
73 		dest_mode	:  1,	/* 0: physical, 1: logical */
74 		delivery_status	:  1,
75 		polarity	:  1,
76 		irr		:  1,
77 		trigger		:  1,	/* 0: edge, 1: level */
78 		mask		:  1,	/* 0: enabled, 1: disabled */
79 		__reserved_2	: 15;
80 
81 	__u32	__reserved_3	: 24,
82 		dest		:  8;
83 } __attribute__ ((packed));
84 
85 struct IR_IO_APIC_route_entry {
86 	__u64	vector		: 8,
87 		zero		: 3,
88 		index2		: 1,
89 		delivery_status : 1,
90 		polarity	: 1,
91 		irr		: 1,
92 		trigger		: 1,
93 		mask		: 1,
94 		reserved	: 31,
95 		format		: 1,
96 		index		: 15;
97 } __attribute__ ((packed));
98 
99 struct irq_alloc_info;
100 struct ioapic_domain_cfg;
101 
102 #define IOAPIC_EDGE			0
103 #define IOAPIC_LEVEL			1
104 
105 #define IOAPIC_MASKED			1
106 #define IOAPIC_UNMASKED			0
107 
108 #define IOAPIC_POL_HIGH			0
109 #define IOAPIC_POL_LOW			1
110 
111 #define IOAPIC_DEST_MODE_PHYSICAL	0
112 #define IOAPIC_DEST_MODE_LOGICAL	1
113 
114 #define	IOAPIC_MAP_ALLOC		0x1
115 #define	IOAPIC_MAP_CHECK		0x2
116 
117 #ifdef CONFIG_X86_IO_APIC
118 
119 /*
120  * # of IO-APICs and # of IRQ routing registers
121  */
122 extern int nr_ioapics;
123 
124 extern int mpc_ioapic_id(int ioapic);
125 extern unsigned int mpc_ioapic_addr(int ioapic);
126 
127 /* # of MP IRQ source entries */
128 extern int mp_irq_entries;
129 
130 /* MP IRQ source entries */
131 extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
132 
133 /* 1 if "noapic" boot option passed */
134 extern int skip_ioapic_setup;
135 
136 /* 1 if "noapic" boot option passed */
137 extern int noioapicquirk;
138 
139 /* -1 if "noapic" boot option passed */
140 extern int noioapicreroute;
141 
142 extern u32 gsi_top;
143 
144 extern unsigned long io_apic_irqs;
145 
146 #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))
147 
148 /*
149  * If we use the IO-APIC for IRQ routing, disable automatic
150  * assignment of PCI IRQ's.
151  */
152 #define io_apic_assign_pci_irqs \
153 	(mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
154 
155 struct irq_cfg;
156 extern void ioapic_insert_resources(void);
157 extern int arch_early_ioapic_init(void);
158 
159 extern int save_ioapic_entries(void);
160 extern void mask_ioapic_entries(void);
161 extern int restore_ioapic_entries(void);
162 
163 extern void setup_ioapic_ids_from_mpc(void);
164 extern void setup_ioapic_ids_from_mpc_nocheck(void);
165 
166 extern int mp_find_ioapic(u32 gsi);
167 extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
168 extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
169 			     struct irq_alloc_info *info);
170 extern void mp_unmap_irq(int irq);
171 extern int mp_register_ioapic(int id, u32 address, u32 gsi_base,
172 			      struct ioapic_domain_cfg *cfg);
173 extern int mp_unregister_ioapic(u32 gsi_base);
174 extern int mp_ioapic_registered(u32 gsi_base);
175 
176 extern void ioapic_set_alloc_attr(struct irq_alloc_info *info,
177 				  int node, int trigger, int polarity);
178 
179 extern void mp_save_irq(struct mpc_intsrc *m);
180 
181 extern void disable_ioapic_support(void);
182 
183 extern void __init io_apic_init_mappings(void);
184 extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
185 extern void native_restore_boot_irq_mode(void);
186 
io_apic_read(unsigned int apic,unsigned int reg)187 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
188 {
189 	return x86_apic_ops.io_apic_read(apic, reg);
190 }
191 
192 extern void setup_IO_APIC(void);
193 extern void enable_IO_APIC(void);
194 extern void clear_IO_APIC(void);
195 extern void restore_boot_irq_mode(void);
196 extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin);
197 extern void print_IO_APICs(void);
198 #else  /* !CONFIG_X86_IO_APIC */
199 
200 #define IO_APIC_IRQ(x)		0
201 #define io_apic_assign_pci_irqs 0
202 #define setup_ioapic_ids_from_mpc x86_init_noop
ioapic_insert_resources(void)203 static inline void ioapic_insert_resources(void) { }
arch_early_ioapic_init(void)204 static inline int arch_early_ioapic_init(void) { return 0; }
print_IO_APICs(void)205 static inline void print_IO_APICs(void) {}
206 #define gsi_top (NR_IRQS_LEGACY)
mp_find_ioapic(u32 gsi)207 static inline int mp_find_ioapic(u32 gsi) { return 0; }
mp_map_gsi_to_irq(u32 gsi,unsigned int flags,struct irq_alloc_info * info)208 static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
209 				    struct irq_alloc_info *info)
210 {
211 	return gsi;
212 }
213 
mp_unmap_irq(int irq)214 static inline void mp_unmap_irq(int irq) { }
215 
save_ioapic_entries(void)216 static inline int save_ioapic_entries(void)
217 {
218 	return -ENOMEM;
219 }
220 
mask_ioapic_entries(void)221 static inline void mask_ioapic_entries(void) { }
restore_ioapic_entries(void)222 static inline int restore_ioapic_entries(void)
223 {
224 	return -ENOMEM;
225 }
226 
mp_save_irq(struct mpc_intsrc * m)227 static inline void mp_save_irq(struct mpc_intsrc *m) { }
disable_ioapic_support(void)228 static inline void disable_ioapic_support(void) { }
io_apic_init_mappings(void)229 static inline void io_apic_init_mappings(void) { }
230 #define native_io_apic_read		NULL
231 #define native_restore_boot_irq_mode	NULL
232 
setup_IO_APIC(void)233 static inline void setup_IO_APIC(void) { }
enable_IO_APIC(void)234 static inline void enable_IO_APIC(void) { }
restore_boot_irq_mode(void)235 static inline void restore_boot_irq_mode(void) { }
236 
237 #endif
238 
239 #endif /* _ASM_X86_IO_APIC_H */
240