1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10 #include <linux/reset-controller.h>
11
12 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
13
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap-divider.h"
18 #include "common.h"
19 #include "gdsc.h"
20 #include "reset.h"
21
22 enum {
23 P_BI_TCXO,
24 P_CHIP_SLEEP_CLK,
25 P_CORE_BI_PLL_TEST_SE,
26 P_DISP_CC_PLL0_OUT_MAIN,
27 P_DISP_CC_PLL1_OUT_EVEN,
28 P_DISP_CC_PLL1_OUT_MAIN,
29 P_DP_PHY_PLL_LINK_CLK,
30 P_DP_PHY_PLL_VCO_DIV_CLK,
31 P_DPTX1_PHY_PLL_LINK_CLK,
32 P_DPTX1_PHY_PLL_VCO_DIV_CLK,
33 P_DPTX2_PHY_PLL_LINK_CLK,
34 P_DPTX2_PHY_PLL_VCO_DIV_CLK,
35 P_DSI0_PHY_PLL_OUT_BYTECLK,
36 P_DSI0_PHY_PLL_OUT_DSICLK,
37 P_DSI1_PHY_PLL_OUT_BYTECLK,
38 P_DSI1_PHY_PLL_OUT_DSICLK,
39 P_EDP_PHY_PLL_LINK_CLK,
40 P_EDP_PHY_PLL_VCO_DIV_CLK,
41 };
42
43 static struct pll_vco vco_table[] = {
44 { 249600000, 2000000000, 0 },
45 };
46
47 static struct alpha_pll_config disp_cc_pll0_config = {
48 .l = 0x47,
49 .alpha = 0xE000,
50 .config_ctl_val = 0x20485699,
51 .config_ctl_hi_val = 0x00002261,
52 .config_ctl_hi1_val = 0x329A699C,
53 .user_ctl_val = 0x00000000,
54 .user_ctl_hi_val = 0x00000805,
55 .user_ctl_hi1_val = 0x00000000,
56 };
57
58 static struct clk_init_data disp_cc_pll0_init = {
59 .name = "disp_cc_pll0",
60 .parent_data = &(const struct clk_parent_data){
61 .fw_name = "bi_tcxo",
62 },
63 .num_parents = 1,
64 .ops = &clk_alpha_pll_lucid_ops,
65 };
66
67 static struct clk_alpha_pll disp_cc_pll0 = {
68 .offset = 0x0,
69 .vco_table = vco_table,
70 .num_vco = ARRAY_SIZE(vco_table),
71 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
72 .clkr.hw.init = &disp_cc_pll0_init
73 };
74
75 static struct alpha_pll_config disp_cc_pll1_config = {
76 .l = 0x1F,
77 .alpha = 0x4000,
78 .config_ctl_val = 0x20485699,
79 .config_ctl_hi_val = 0x00002261,
80 .config_ctl_hi1_val = 0x329A699C,
81 .user_ctl_val = 0x00000000,
82 .user_ctl_hi_val = 0x00000805,
83 .user_ctl_hi1_val = 0x00000000,
84 };
85
86 static struct clk_init_data disp_cc_pll1_init = {
87 .name = "disp_cc_pll1",
88 .parent_data = &(const struct clk_parent_data){
89 .fw_name = "bi_tcxo",
90 },
91 .num_parents = 1,
92 .ops = &clk_alpha_pll_lucid_ops,
93 };
94
95 static struct clk_alpha_pll disp_cc_pll1 = {
96 .offset = 0x1000,
97 .vco_table = vco_table,
98 .num_vco = ARRAY_SIZE(vco_table),
99 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
100 .clkr.hw.init = &disp_cc_pll1_init
101 };
102
103 static const struct parent_map disp_cc_parent_map_0[] = {
104 { P_BI_TCXO, 0 },
105 { P_DP_PHY_PLL_LINK_CLK, 1 },
106 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
107 };
108
109 static const struct clk_parent_data disp_cc_parent_data_0[] = {
110 { .fw_name = "bi_tcxo" },
111 { .fw_name = "dp_phy_pll_link_clk" },
112 { .fw_name = "dp_phy_pll_vco_div_clk" },
113 };
114
115 static const struct parent_map disp_cc_parent_map_1[] = {
116 { P_BI_TCXO, 0 },
117 };
118
119 static const struct clk_parent_data disp_cc_parent_data_1[] = {
120 { .fw_name = "bi_tcxo" },
121 };
122
123 static const struct parent_map disp_cc_parent_map_2[] = {
124 { P_BI_TCXO, 0 },
125 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
126 { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
127 };
128
129 static const struct clk_parent_data disp_cc_parent_data_2[] = {
130 { .fw_name = "bi_tcxo" },
131 { .fw_name = "dsi0_phy_pll_out_byteclk" },
132 { .fw_name = "dsi1_phy_pll_out_byteclk" },
133 };
134
135 static const struct parent_map disp_cc_parent_map_3[] = {
136 { P_BI_TCXO, 0 },
137 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
138 };
139
140 static const struct clk_parent_data disp_cc_parent_data_3[] = {
141 { .fw_name = "bi_tcxo" },
142 { .hw = &disp_cc_pll1.clkr.hw },
143 };
144
145 static const struct parent_map disp_cc_parent_map_5[] = {
146 { P_BI_TCXO, 0 },
147 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
148 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
149 };
150
151 static const struct clk_parent_data disp_cc_parent_data_5[] = {
152 { .fw_name = "bi_tcxo" },
153 { .hw = &disp_cc_pll0.clkr.hw },
154 { .hw = &disp_cc_pll1.clkr.hw },
155 };
156
157 static const struct parent_map disp_cc_parent_map_6[] = {
158 { P_BI_TCXO, 0 },
159 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
160 { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
161 };
162
163 static const struct clk_parent_data disp_cc_parent_data_6[] = {
164 { .fw_name = "bi_tcxo" },
165 { .fw_name = "dsi0_phy_pll_out_dsiclk" },
166 { .fw_name = "dsi1_phy_pll_out_dsiclk" },
167 };
168
169 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
170 F(19200000, P_BI_TCXO, 1, 0, 0),
171 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
172 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
173 { }
174 };
175
176 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
177 .cmd_rcgr = 0x22bc,
178 .mnd_width = 0,
179 .hid_width = 5,
180 .parent_map = disp_cc_parent_map_3,
181 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
182 .clkr.hw.init = &(struct clk_init_data){
183 .name = "disp_cc_mdss_ahb_clk_src",
184 .parent_data = disp_cc_parent_data_3,
185 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
186 .flags = CLK_SET_RATE_PARENT,
187 .ops = &clk_rcg2_shared_ops,
188 },
189 };
190
191 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
192 F(19200000, P_BI_TCXO, 1, 0, 0),
193 { }
194 };
195
196 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
197 .cmd_rcgr = 0x2110,
198 .mnd_width = 0,
199 .hid_width = 5,
200 .parent_map = disp_cc_parent_map_2,
201 .clkr.hw.init = &(struct clk_init_data){
202 .name = "disp_cc_mdss_byte0_clk_src",
203 .parent_data = disp_cc_parent_data_2,
204 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
205 .flags = CLK_SET_RATE_PARENT,
206 .ops = &clk_byte2_ops,
207 },
208 };
209
210 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
211 .cmd_rcgr = 0x212c,
212 .mnd_width = 0,
213 .hid_width = 5,
214 .parent_map = disp_cc_parent_map_2,
215 .clkr.hw.init = &(struct clk_init_data){
216 .name = "disp_cc_mdss_byte1_clk_src",
217 .parent_data = disp_cc_parent_data_2,
218 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
219 .flags = CLK_SET_RATE_PARENT,
220 .ops = &clk_byte2_ops,
221 },
222 };
223
224 static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
225 .cmd_rcgr = 0x2240,
226 .mnd_width = 0,
227 .hid_width = 5,
228 .parent_map = disp_cc_parent_map_1,
229 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
230 .clkr.hw.init = &(struct clk_init_data){
231 .name = "disp_cc_mdss_dp_aux1_clk_src",
232 .parent_data = disp_cc_parent_data_1,
233 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
234 .flags = CLK_SET_RATE_PARENT,
235 .ops = &clk_rcg2_ops,
236 },
237 };
238
239 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
240 .cmd_rcgr = 0x21dc,
241 .mnd_width = 0,
242 .hid_width = 5,
243 .parent_map = disp_cc_parent_map_1,
244 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
245 .clkr.hw.init = &(struct clk_init_data){
246 .name = "disp_cc_mdss_dp_aux_clk_src",
247 .parent_data = disp_cc_parent_data_1,
248 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
249 .flags = CLK_SET_RATE_PARENT,
250 .ops = &clk_rcg2_ops,
251 },
252 };
253
254 static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = {
255 F(162000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
256 F(270000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
257 F(540000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
258 F(810000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
259 { }
260 };
261
262 static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
263 .cmd_rcgr = 0x220c,
264 .mnd_width = 0,
265 .hid_width = 5,
266 .parent_map = disp_cc_parent_map_0,
267 .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src,
268 .clkr.hw.init = &(struct clk_init_data){
269 .name = "disp_cc_mdss_dp_link1_clk_src",
270 .parent_data = disp_cc_parent_data_0,
271 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
272 .ops = &clk_rcg2_ops,
273 },
274 };
275
276 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
277 .cmd_rcgr = 0x2178,
278 .mnd_width = 0,
279 .hid_width = 5,
280 .parent_map = disp_cc_parent_map_0,
281 .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src,
282 .clkr.hw.init = &(struct clk_init_data){
283 .name = "disp_cc_mdss_dp_link_clk_src",
284 .parent_data = disp_cc_parent_data_0,
285 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
286 .ops = &clk_rcg2_ops,
287 },
288 };
289
290 static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
291 .cmd_rcgr = 0x21c4,
292 .mnd_width = 16,
293 .hid_width = 5,
294 .parent_map = disp_cc_parent_map_0,
295 .clkr.hw.init = &(struct clk_init_data){
296 .name = "disp_cc_mdss_dp_pixel1_clk_src",
297 .parent_data = disp_cc_parent_data_0,
298 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
299 .ops = &clk_dp_ops,
300 },
301 };
302
303 static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
304 .cmd_rcgr = 0x21f4,
305 .mnd_width = 16,
306 .hid_width = 5,
307 .parent_map = disp_cc_parent_map_0,
308 .clkr.hw.init = &(struct clk_init_data){
309 .name = "disp_cc_mdss_dp_pixel2_clk_src",
310 .parent_data = disp_cc_parent_data_0,
311 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
312 .ops = &clk_dp_ops,
313 },
314 };
315
316 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
317 .cmd_rcgr = 0x21ac,
318 .mnd_width = 16,
319 .hid_width = 5,
320 .parent_map = disp_cc_parent_map_0,
321 .clkr.hw.init = &(struct clk_init_data){
322 .name = "disp_cc_mdss_dp_pixel_clk_src",
323 .parent_data = disp_cc_parent_data_0,
324 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
325 .ops = &clk_dp_ops,
326 },
327 };
328
329 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
330 .cmd_rcgr = 0x2148,
331 .mnd_width = 0,
332 .hid_width = 5,
333 .parent_map = disp_cc_parent_map_2,
334 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
335 .clkr.hw.init = &(struct clk_init_data){
336 .name = "disp_cc_mdss_esc0_clk_src",
337 .parent_data = disp_cc_parent_data_2,
338 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
339 .flags = CLK_SET_RATE_PARENT,
340 .ops = &clk_rcg2_ops,
341 },
342 };
343
344 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
345 .cmd_rcgr = 0x2160,
346 .mnd_width = 0,
347 .hid_width = 5,
348 .parent_map = disp_cc_parent_map_2,
349 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
350 .clkr.hw.init = &(struct clk_init_data){
351 .name = "disp_cc_mdss_esc1_clk_src",
352 .parent_data = disp_cc_parent_data_2,
353 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
354 .flags = CLK_SET_RATE_PARENT,
355 .ops = &clk_rcg2_ops,
356 },
357 };
358
359 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
360 F(19200000, P_BI_TCXO, 1, 0, 0),
361 F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0),
362 F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0),
363 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
364 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
365 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
366 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
367 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
368 { }
369 };
370
371 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
372 .cmd_rcgr = 0x20c8,
373 .mnd_width = 0,
374 .hid_width = 5,
375 .parent_map = disp_cc_parent_map_5,
376 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
377 .clkr.hw.init = &(struct clk_init_data){
378 .name = "disp_cc_mdss_mdp_clk_src",
379 .parent_data = disp_cc_parent_data_5,
380 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
381 .flags = CLK_SET_RATE_PARENT,
382 .ops = &clk_rcg2_shared_ops,
383 },
384 };
385
386 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
387 .cmd_rcgr = 0x2098,
388 .mnd_width = 8,
389 .hid_width = 5,
390 .parent_map = disp_cc_parent_map_6,
391 .clkr.hw.init = &(struct clk_init_data){
392 .name = "disp_cc_mdss_pclk0_clk_src",
393 .parent_data = disp_cc_parent_data_6,
394 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
395 .flags = CLK_SET_RATE_PARENT,
396 .ops = &clk_pixel_ops,
397 },
398 };
399
400 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
401 .cmd_rcgr = 0x20b0,
402 .mnd_width = 8,
403 .hid_width = 5,
404 .parent_map = disp_cc_parent_map_6,
405 .clkr.hw.init = &(struct clk_init_data){
406 .name = "disp_cc_mdss_pclk1_clk_src",
407 .parent_data = disp_cc_parent_data_6,
408 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
409 .flags = CLK_SET_RATE_PARENT,
410 .ops = &clk_pixel_ops,
411 },
412 };
413
414 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
415 F(19200000, P_BI_TCXO, 1, 0, 0),
416 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
417 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
418 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
419 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
420 { }
421 };
422
423 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
424 .cmd_rcgr = 0x20e0,
425 .mnd_width = 0,
426 .hid_width = 5,
427 .parent_map = disp_cc_parent_map_5,
428 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
429 .clkr.hw.init = &(struct clk_init_data){
430 .name = "disp_cc_mdss_rot_clk_src",
431 .parent_data = disp_cc_parent_data_5,
432 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
433 .flags = CLK_SET_RATE_PARENT,
434 .ops = &clk_rcg2_shared_ops,
435 },
436 };
437
438 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
439 .cmd_rcgr = 0x20f8,
440 .mnd_width = 0,
441 .hid_width = 5,
442 .parent_map = disp_cc_parent_map_1,
443 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
444 .clkr.hw.init = &(struct clk_init_data){
445 .name = "disp_cc_mdss_vsync_clk_src",
446 .parent_data = disp_cc_parent_data_1,
447 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
448 .flags = CLK_SET_RATE_PARENT,
449 .ops = &clk_rcg2_ops,
450 },
451 };
452
453 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
454 .reg = 0x2128,
455 .shift = 0,
456 .width = 2,
457 .clkr.hw.init = &(struct clk_init_data) {
458 .name = "disp_cc_mdss_byte0_div_clk_src",
459 .parent_data = &(const struct clk_parent_data){
460 .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
461 },
462 .num_parents = 1,
463 .ops = &clk_regmap_div_ops,
464 },
465 };
466
467
468 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
469 .reg = 0x2144,
470 .shift = 0,
471 .width = 2,
472 .clkr.hw.init = &(struct clk_init_data) {
473 .name = "disp_cc_mdss_byte1_div_clk_src",
474 .parent_data = &(const struct clk_parent_data){
475 .hw = &disp_cc_mdss_byte1_clk_src.clkr.hw,
476 },
477 .num_parents = 1,
478 .ops = &clk_regmap_div_ops,
479 },
480 };
481
482
483 static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = {
484 .reg = 0x2224,
485 .shift = 0,
486 .width = 2,
487 .clkr.hw.init = &(struct clk_init_data) {
488 .name = "disp_cc_mdss_dp_link1_div_clk_src",
489 .parent_data = &(const struct clk_parent_data){
490 .hw = &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
491 },
492 .num_parents = 1,
493 .ops = &clk_regmap_div_ro_ops,
494 },
495 };
496
497
498 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
499 .reg = 0x2190,
500 .shift = 0,
501 .width = 2,
502 .clkr.hw.init = &(struct clk_init_data) {
503 .name = "disp_cc_mdss_dp_link_div_clk_src",
504 .parent_data = &(const struct clk_parent_data){
505 .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
506 },
507 .num_parents = 1,
508 .ops = &clk_regmap_div_ro_ops,
509 },
510 };
511
512 static struct clk_branch disp_cc_mdss_ahb_clk = {
513 .halt_reg = 0x2080,
514 .halt_check = BRANCH_HALT,
515 .clkr = {
516 .enable_reg = 0x2080,
517 .enable_mask = BIT(0),
518 .hw.init = &(struct clk_init_data){
519 .name = "disp_cc_mdss_ahb_clk",
520 .parent_data = &(const struct clk_parent_data){
521 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
522 },
523 .num_parents = 1,
524 .flags = CLK_SET_RATE_PARENT,
525 .ops = &clk_branch2_ops,
526 },
527 },
528 };
529
530 static struct clk_branch disp_cc_mdss_byte0_clk = {
531 .halt_reg = 0x2028,
532 .halt_check = BRANCH_HALT,
533 .clkr = {
534 .enable_reg = 0x2028,
535 .enable_mask = BIT(0),
536 .hw.init = &(struct clk_init_data){
537 .name = "disp_cc_mdss_byte0_clk",
538 .parent_data = &(const struct clk_parent_data){
539 .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
540 },
541 .num_parents = 1,
542 .flags = CLK_SET_RATE_PARENT,
543 .ops = &clk_branch2_ops,
544 },
545 },
546 };
547
548 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
549 .halt_reg = 0x202c,
550 .halt_check = BRANCH_HALT,
551 .clkr = {
552 .enable_reg = 0x202c,
553 .enable_mask = BIT(0),
554 .hw.init = &(struct clk_init_data){
555 .name = "disp_cc_mdss_byte0_intf_clk",
556 .parent_data = &(const struct clk_parent_data){
557 .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
558 },
559 .num_parents = 1,
560 .flags = CLK_SET_RATE_PARENT,
561 .ops = &clk_branch2_ops,
562 },
563 },
564 };
565
566 static struct clk_branch disp_cc_mdss_byte1_clk = {
567 .halt_reg = 0x2030,
568 .halt_check = BRANCH_HALT,
569 .clkr = {
570 .enable_reg = 0x2030,
571 .enable_mask = BIT(0),
572 .hw.init = &(struct clk_init_data){
573 .name = "disp_cc_mdss_byte1_clk",
574 .parent_data = &(const struct clk_parent_data){
575 .hw = &disp_cc_mdss_byte1_clk_src.clkr.hw,
576 },
577 .num_parents = 1,
578 .flags = CLK_SET_RATE_PARENT,
579 .ops = &clk_branch2_ops,
580 },
581 },
582 };
583
584 static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
585 .halt_reg = 0x2034,
586 .halt_check = BRANCH_HALT,
587 .clkr = {
588 .enable_reg = 0x2034,
589 .enable_mask = BIT(0),
590 .hw.init = &(struct clk_init_data){
591 .name = "disp_cc_mdss_byte1_intf_clk",
592 .parent_data = &(const struct clk_parent_data){
593 .hw = &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
594 },
595 .num_parents = 1,
596 .flags = CLK_SET_RATE_PARENT,
597 .ops = &clk_branch2_ops,
598 },
599 },
600 };
601
602 static struct clk_branch disp_cc_mdss_dp_aux1_clk = {
603 .halt_reg = 0x2068,
604 .halt_check = BRANCH_HALT,
605 .clkr = {
606 .enable_reg = 0x2068,
607 .enable_mask = BIT(0),
608 .hw.init = &(struct clk_init_data){
609 .name = "disp_cc_mdss_dp_aux1_clk",
610 .parent_data = &(const struct clk_parent_data){
611 .hw = &disp_cc_mdss_dp_aux1_clk_src.clkr.hw,
612 },
613 .num_parents = 1,
614 .flags = CLK_SET_RATE_PARENT,
615 .ops = &clk_branch2_ops,
616 },
617 },
618 };
619
620 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
621 .halt_reg = 0x2054,
622 .halt_check = BRANCH_HALT,
623 .clkr = {
624 .enable_reg = 0x2054,
625 .enable_mask = BIT(0),
626 .hw.init = &(struct clk_init_data){
627 .name = "disp_cc_mdss_dp_aux_clk",
628 .parent_data = &(const struct clk_parent_data){
629 .hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
630 },
631 .num_parents = 1,
632 .flags = CLK_SET_RATE_PARENT,
633 .ops = &clk_branch2_ops,
634 },
635 },
636 };
637
638 static struct clk_branch disp_cc_mdss_dp_link1_clk = {
639 .halt_reg = 0x205c,
640 .halt_check = BRANCH_HALT,
641 .clkr = {
642 .enable_reg = 0x205c,
643 .enable_mask = BIT(0),
644 .hw.init = &(struct clk_init_data){
645 .name = "disp_cc_mdss_dp_link1_clk",
646 .parent_data = &(const struct clk_parent_data){
647 .hw = &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
648 },
649 .num_parents = 1,
650 .flags = CLK_SET_RATE_PARENT,
651 .ops = &clk_branch2_ops,
652 },
653 },
654 };
655
656 static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = {
657 .halt_reg = 0x2060,
658 .halt_check = BRANCH_HALT,
659 .clkr = {
660 .enable_reg = 0x2060,
661 .enable_mask = BIT(0),
662 .hw.init = &(struct clk_init_data){
663 .name = "disp_cc_mdss_dp_link1_intf_clk",
664 .parent_data = &(const struct clk_parent_data){
665 .hw = &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw,
666 },
667 .num_parents = 1,
668 .ops = &clk_branch2_ops,
669 },
670 },
671 };
672
673 static struct clk_branch disp_cc_mdss_dp_link_clk = {
674 .halt_reg = 0x2040,
675 .halt_check = BRANCH_HALT,
676 .clkr = {
677 .enable_reg = 0x2040,
678 .enable_mask = BIT(0),
679 .hw.init = &(struct clk_init_data){
680 .name = "disp_cc_mdss_dp_link_clk",
681 .parent_data = &(const struct clk_parent_data){
682 .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
683 },
684 .num_parents = 1,
685 .flags = CLK_SET_RATE_PARENT,
686 .ops = &clk_branch2_ops,
687 },
688 },
689 };
690
691 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
692 .halt_reg = 0x2044,
693 .halt_check = BRANCH_HALT,
694 .clkr = {
695 .enable_reg = 0x2044,
696 .enable_mask = BIT(0),
697 .hw.init = &(struct clk_init_data){
698 .name = "disp_cc_mdss_dp_link_intf_clk",
699 .parent_data = &(const struct clk_parent_data){
700 .hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
701 },
702 .num_parents = 1,
703 .ops = &clk_branch2_ops,
704 },
705 },
706 };
707
708 static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
709 .halt_reg = 0x2050,
710 .halt_check = BRANCH_HALT,
711 .clkr = {
712 .enable_reg = 0x2050,
713 .enable_mask = BIT(0),
714 .hw.init = &(struct clk_init_data){
715 .name = "disp_cc_mdss_dp_pixel1_clk",
716 .parent_data = &(const struct clk_parent_data){
717 .hw = &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
718 },
719 .num_parents = 1,
720 .flags = CLK_SET_RATE_PARENT,
721 .ops = &clk_branch2_ops,
722 },
723 },
724 };
725
726 static struct clk_branch disp_cc_mdss_dp_pixel2_clk = {
727 .halt_reg = 0x2058,
728 .halt_check = BRANCH_HALT,
729 .clkr = {
730 .enable_reg = 0x2058,
731 .enable_mask = BIT(0),
732 .hw.init = &(struct clk_init_data){
733 .name = "disp_cc_mdss_dp_pixel2_clk",
734 .parent_data = &(const struct clk_parent_data){
735 .hw = &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw,
736 },
737 .num_parents = 1,
738 .flags = CLK_SET_RATE_PARENT,
739 .ops = &clk_branch2_ops,
740 },
741 },
742 };
743
744 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
745 .halt_reg = 0x204c,
746 .halt_check = BRANCH_HALT,
747 .clkr = {
748 .enable_reg = 0x204c,
749 .enable_mask = BIT(0),
750 .hw.init = &(struct clk_init_data){
751 .name = "disp_cc_mdss_dp_pixel_clk",
752 .parent_data = &(const struct clk_parent_data){
753 .hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
754 },
755 .num_parents = 1,
756 .flags = CLK_SET_RATE_PARENT,
757 .ops = &clk_branch2_ops,
758 },
759 },
760 };
761
762 static struct clk_branch disp_cc_mdss_esc0_clk = {
763 .halt_reg = 0x2038,
764 .halt_check = BRANCH_HALT,
765 .clkr = {
766 .enable_reg = 0x2038,
767 .enable_mask = BIT(0),
768 .hw.init = &(struct clk_init_data){
769 .name = "disp_cc_mdss_esc0_clk",
770 .parent_data = &(const struct clk_parent_data){
771 .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw,
772 },
773 .num_parents = 1,
774 .flags = CLK_SET_RATE_PARENT,
775 .ops = &clk_branch2_ops,
776 },
777 },
778 };
779
780 static struct clk_branch disp_cc_mdss_esc1_clk = {
781 .halt_reg = 0x203c,
782 .halt_check = BRANCH_HALT,
783 .clkr = {
784 .enable_reg = 0x203c,
785 .enable_mask = BIT(0),
786 .hw.init = &(struct clk_init_data){
787 .name = "disp_cc_mdss_esc1_clk",
788 .parent_data = &(const struct clk_parent_data){
789 .hw = &disp_cc_mdss_esc1_clk_src.clkr.hw,
790 },
791 .num_parents = 1,
792 .flags = CLK_SET_RATE_PARENT,
793 .ops = &clk_branch2_ops,
794 },
795 },
796 };
797
798 static struct clk_branch disp_cc_mdss_mdp_clk = {
799 .halt_reg = 0x200c,
800 .halt_check = BRANCH_HALT,
801 .clkr = {
802 .enable_reg = 0x200c,
803 .enable_mask = BIT(0),
804 .hw.init = &(struct clk_init_data){
805 .name = "disp_cc_mdss_mdp_clk",
806 .parent_data = &(const struct clk_parent_data){
807 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
808 },
809 .num_parents = 1,
810 .flags = CLK_SET_RATE_PARENT,
811 .ops = &clk_branch2_ops,
812 },
813 },
814 };
815
816 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
817 .halt_reg = 0x201c,
818 .halt_check = BRANCH_VOTED,
819 .clkr = {
820 .enable_reg = 0x201c,
821 .enable_mask = BIT(0),
822 .hw.init = &(struct clk_init_data){
823 .name = "disp_cc_mdss_mdp_lut_clk",
824 .parent_data = &(const struct clk_parent_data){
825 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
826 },
827 .num_parents = 1,
828 .ops = &clk_branch2_ops,
829 },
830 },
831 };
832
833 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
834 .halt_reg = 0x4004,
835 .halt_check = BRANCH_VOTED,
836 .clkr = {
837 .enable_reg = 0x4004,
838 .enable_mask = BIT(0),
839 .hw.init = &(struct clk_init_data){
840 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
841 .parent_data = &(const struct clk_parent_data){
842 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
843 },
844 .num_parents = 1,
845 .flags = CLK_SET_RATE_PARENT,
846 .ops = &clk_branch2_ops,
847 },
848 },
849 };
850
851 static struct clk_branch disp_cc_mdss_pclk0_clk = {
852 .halt_reg = 0x2004,
853 .halt_check = BRANCH_HALT,
854 .clkr = {
855 .enable_reg = 0x2004,
856 .enable_mask = BIT(0),
857 .hw.init = &(struct clk_init_data){
858 .name = "disp_cc_mdss_pclk0_clk",
859 .parent_data = &(const struct clk_parent_data){
860 .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw,
861 },
862 .num_parents = 1,
863 .flags = CLK_SET_RATE_PARENT,
864 .ops = &clk_branch2_ops,
865 },
866 },
867 };
868
869 static struct clk_branch disp_cc_mdss_pclk1_clk = {
870 .halt_reg = 0x2008,
871 .halt_check = BRANCH_HALT,
872 .clkr = {
873 .enable_reg = 0x2008,
874 .enable_mask = BIT(0),
875 .hw.init = &(struct clk_init_data){
876 .name = "disp_cc_mdss_pclk1_clk",
877 .parent_data = &(const struct clk_parent_data){
878 .hw = &disp_cc_mdss_pclk1_clk_src.clkr.hw,
879 },
880 .num_parents = 1,
881 .flags = CLK_SET_RATE_PARENT,
882 .ops = &clk_branch2_ops,
883 },
884 },
885 };
886
887 static struct clk_branch disp_cc_mdss_rot_clk = {
888 .halt_reg = 0x2014,
889 .halt_check = BRANCH_HALT,
890 .clkr = {
891 .enable_reg = 0x2014,
892 .enable_mask = BIT(0),
893 .hw.init = &(struct clk_init_data){
894 .name = "disp_cc_mdss_rot_clk",
895 .parent_data = &(const struct clk_parent_data){
896 .hw = &disp_cc_mdss_rot_clk_src.clkr.hw,
897 },
898 .num_parents = 1,
899 .flags = CLK_SET_RATE_PARENT,
900 .ops = &clk_branch2_ops,
901 },
902 },
903 };
904
905 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
906 .halt_reg = 0x400c,
907 .halt_check = BRANCH_HALT,
908 .clkr = {
909 .enable_reg = 0x400c,
910 .enable_mask = BIT(0),
911 .hw.init = &(struct clk_init_data){
912 .name = "disp_cc_mdss_rscc_ahb_clk",
913 .parent_data = &(const struct clk_parent_data){
914 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
915 },
916 .num_parents = 1,
917 .flags = CLK_SET_RATE_PARENT,
918 .ops = &clk_branch2_ops,
919 },
920 },
921 };
922
923 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
924 .halt_reg = 0x4008,
925 .halt_check = BRANCH_HALT,
926 .clkr = {
927 .enable_reg = 0x4008,
928 .enable_mask = BIT(0),
929 .hw.init = &(struct clk_init_data){
930 .name = "disp_cc_mdss_rscc_vsync_clk",
931 .parent_data = &(const struct clk_parent_data){
932 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
933 },
934 .num_parents = 1,
935 .flags = CLK_SET_RATE_PARENT,
936 .ops = &clk_branch2_ops,
937 },
938 },
939 };
940
941 static struct clk_branch disp_cc_mdss_vsync_clk = {
942 .halt_reg = 0x2024,
943 .halt_check = BRANCH_HALT,
944 .clkr = {
945 .enable_reg = 0x2024,
946 .enable_mask = BIT(0),
947 .hw.init = &(struct clk_init_data){
948 .name = "disp_cc_mdss_vsync_clk",
949 .parent_data = &(const struct clk_parent_data){
950 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
951 },
952 .num_parents = 1,
953 .flags = CLK_SET_RATE_PARENT,
954 .ops = &clk_branch2_ops,
955 },
956 },
957 };
958
959 static struct gdsc mdss_gdsc = {
960 .gdscr = 0x3000,
961 .pd = {
962 .name = "mdss_gdsc",
963 },
964 .pwrsts = PWRSTS_OFF_ON,
965 .flags = HW_CTRL,
966 };
967
968 static struct clk_regmap *disp_cc_sm8250_clocks[] = {
969 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
970 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
971 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
972 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
973 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
974 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
975 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
976 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
977 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
978 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
979 [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr,
980 [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr,
981 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
982 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
983 [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr,
984 [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr,
985 [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr,
986 [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr,
987 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
988 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
989 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr,
990 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
991 [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
992 [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr,
993 [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr,
994 [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr,
995 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
996 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
997 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
998 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
999 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1000 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1001 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1002 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1003 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1004 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1005 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1006 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1007 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1008 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1009 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
1010 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
1011 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1012 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1013 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1014 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1015 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1016 [DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1017 };
1018
1019 static const struct qcom_reset_map disp_cc_sm8250_resets[] = {
1020 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
1021 [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
1022 };
1023
1024 static struct gdsc *disp_cc_sm8250_gdscs[] = {
1025 [MDSS_GDSC] = &mdss_gdsc,
1026 };
1027
1028 static const struct regmap_config disp_cc_sm8250_regmap_config = {
1029 .reg_bits = 32,
1030 .reg_stride = 4,
1031 .val_bits = 32,
1032 .max_register = 0x10000,
1033 .fast_io = true,
1034 };
1035
1036 static const struct qcom_cc_desc disp_cc_sm8250_desc = {
1037 .config = &disp_cc_sm8250_regmap_config,
1038 .clks = disp_cc_sm8250_clocks,
1039 .num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks),
1040 .resets = disp_cc_sm8250_resets,
1041 .num_resets = ARRAY_SIZE(disp_cc_sm8250_resets),
1042 .gdscs = disp_cc_sm8250_gdscs,
1043 .num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs),
1044 };
1045
1046 static const struct of_device_id disp_cc_sm8250_match_table[] = {
1047 { .compatible = "qcom,sm8150-dispcc" },
1048 { .compatible = "qcom,sm8250-dispcc" },
1049 { }
1050 };
1051 MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
1052
disp_cc_sm8250_probe(struct platform_device * pdev)1053 static int disp_cc_sm8250_probe(struct platform_device *pdev)
1054 {
1055 struct regmap *regmap;
1056
1057 regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc);
1058 if (IS_ERR(regmap))
1059 return PTR_ERR(regmap);
1060
1061 /* note: trion == lucid, except for the prepare() op */
1062 BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
1063 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
1064 disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
1065 disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
1066 disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
1067 disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
1068 disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
1069 disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
1070 disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
1071 disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
1072 }
1073
1074 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1075 clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1076
1077 /* Enable clock gating for MDP clocks */
1078 regmap_update_bits(regmap, 0x8000, 0x10, 0x10);
1079
1080 /* DISP_CC_XO_CLK always-on */
1081 regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0));
1082
1083 return qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap);
1084 }
1085
1086 static struct platform_driver disp_cc_sm8250_driver = {
1087 .probe = disp_cc_sm8250_probe,
1088 .driver = {
1089 .name = "disp_cc-sm8250",
1090 .of_match_table = disp_cc_sm8250_match_table,
1091 },
1092 };
1093
disp_cc_sm8250_init(void)1094 static int __init disp_cc_sm8250_init(void)
1095 {
1096 return platform_driver_register(&disp_cc_sm8250_driver);
1097 }
1098 subsys_initcall(disp_cc_sm8250_init);
1099
disp_cc_sm8250_exit(void)1100 static void __exit disp_cc_sm8250_exit(void)
1101 {
1102 platform_driver_unregister(&disp_cc_sm8250_driver);
1103 }
1104 module_exit(disp_cc_sm8250_exit);
1105
1106 MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver");
1107 MODULE_LICENSE("GPL v2");
1108