1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019, Intel Corporation
4 */
5 #include <linux/slab.h>
6 #include <linux/clk-provider.h>
7 #include <linux/of_device.h>
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10
11 #include <dt-bindings/clock/agilex-clock.h>
12
13 #include "stratix10-clk.h"
14
15 static const struct clk_parent_data pll_mux[] = {
16 { .fw_name = "osc1",
17 .name = "osc1", },
18 { .fw_name = "cb-intosc-hs-div2-clk",
19 .name = "cb-intosc-hs-div2-clk", },
20 { .fw_name = "f2s-free-clk",
21 .name = "f2s-free-clk", },
22 };
23
24 static const struct clk_parent_data boot_mux[] = {
25 { .fw_name = "osc1",
26 .name = "osc1", },
27 { .fw_name = "cb-intosc-hs-div2-clk",
28 .name = "cb-intosc-hs-div2-clk", },
29 };
30
31 static const struct clk_parent_data mpu_free_mux[] = {
32 { .fw_name = "main_pll_c0",
33 .name = "main_pll_c0", },
34 { .fw_name = "peri_pll_c0",
35 .name = "peri_pll_c0", },
36 { .fw_name = "osc1",
37 .name = "osc1", },
38 { .fw_name = "cb-intosc-hs-div2-clk",
39 .name = "cb-intosc-hs-div2-clk", },
40 { .fw_name = "f2s-free-clk",
41 .name = "f2s-free-clk", },
42 };
43
44 static const struct clk_parent_data noc_free_mux[] = {
45 { .fw_name = "main_pll_c1",
46 .name = "main_pll_c1", },
47 { .fw_name = "peri_pll_c1",
48 .name = "peri_pll_c1", },
49 { .fw_name = "osc1",
50 .name = "osc1", },
51 { .fw_name = "cb-intosc-hs-div2-clk",
52 .name = "cb-intosc-hs-div2-clk", },
53 { .fw_name = "f2s-free-clk",
54 .name = "f2s-free-clk", },
55 };
56
57 static const struct clk_parent_data emaca_free_mux[] = {
58 { .fw_name = "main_pll_c2",
59 .name = "main_pll_c2", },
60 { .fw_name = "peri_pll_c2",
61 .name = "peri_pll_c2", },
62 { .fw_name = "osc1",
63 .name = "osc1", },
64 { .fw_name = "cb-intosc-hs-div2-clk",
65 .name = "cb-intosc-hs-div2-clk", },
66 { .fw_name = "f2s-free-clk",
67 .name = "f2s-free-clk", },
68 };
69
70 static const struct clk_parent_data emacb_free_mux[] = {
71 { .fw_name = "main_pll_c3",
72 .name = "main_pll_c3", },
73 { .fw_name = "peri_pll_c3",
74 .name = "peri_pll_c3", },
75 { .fw_name = "osc1",
76 .name = "osc1", },
77 { .fw_name = "cb-intosc-hs-div2-clk",
78 .name = "cb-intosc-hs-div2-clk", },
79 { .fw_name = "f2s-free-clk",
80 .name = "f2s-free-clk", },
81 };
82
83 static const struct clk_parent_data emac_ptp_free_mux[] = {
84 { .fw_name = "main_pll_c3",
85 .name = "main_pll_c3", },
86 { .fw_name = "peri_pll_c3",
87 .name = "peri_pll_c3", },
88 { .fw_name = "osc1",
89 .name = "osc1", },
90 { .fw_name = "cb-intosc-hs-div2-clk",
91 .name = "cb-intosc-hs-div2-clk", },
92 { .fw_name = "f2s-free-clk",
93 .name = "f2s-free-clk", },
94 };
95
96 static const struct clk_parent_data gpio_db_free_mux[] = {
97 { .fw_name = "main_pll_c3",
98 .name = "main_pll_c3", },
99 { .fw_name = "peri_pll_c3",
100 .name = "peri_pll_c3", },
101 { .fw_name = "osc1",
102 .name = "osc1", },
103 { .fw_name = "cb-intosc-hs-div2-clk",
104 .name = "cb-intosc-hs-div2-clk", },
105 { .fw_name = "f2s-free-clk",
106 .name = "f2s-free-clk", },
107 };
108
109 static const struct clk_parent_data psi_ref_free_mux[] = {
110 { .fw_name = "main_pll_c2",
111 .name = "main_pll_c2", },
112 { .fw_name = "peri_pll_c2",
113 .name = "peri_pll_c2", },
114 { .fw_name = "osc1",
115 .name = "osc1", },
116 { .fw_name = "cb-intosc-hs-div2-clk",
117 .name = "cb-intosc-hs-div2-clk", },
118 { .fw_name = "f2s-free-clk",
119 .name = "f2s-free-clk", },
120 };
121
122 static const struct clk_parent_data sdmmc_free_mux[] = {
123 { .fw_name = "main_pll_c3",
124 .name = "main_pll_c3", },
125 { .fw_name = "peri_pll_c3",
126 .name = "peri_pll_c3", },
127 { .fw_name = "osc1",
128 .name = "osc1", },
129 { .fw_name = "cb-intosc-hs-div2-clk",
130 .name = "cb-intosc-hs-div2-clk", },
131 { .fw_name = "f2s-free-clk",
132 .name = "f2s-free-clk", },
133 };
134
135 static const struct clk_parent_data s2f_usr0_free_mux[] = {
136 { .fw_name = "main_pll_c2",
137 .name = "main_pll_c2", },
138 { .fw_name = "peri_pll_c2",
139 .name = "peri_pll_c2", },
140 { .fw_name = "osc1",
141 .name = "osc1", },
142 { .fw_name = "cb-intosc-hs-div2-clk",
143 .name = "cb-intosc-hs-div2-clk", },
144 { .fw_name = "f2s-free-clk",
145 .name = "f2s-free-clk", },
146 };
147
148 static const struct clk_parent_data s2f_usr1_free_mux[] = {
149 { .fw_name = "main_pll_c2",
150 .name = "main_pll_c2", },
151 { .fw_name = "peri_pll_c2",
152 .name = "peri_pll_c2", },
153 { .fw_name = "osc1",
154 .name = "osc1", },
155 { .fw_name = "cb-intosc-hs-div2-clk",
156 .name = "cb-intosc-hs-div2-clk", },
157 { .fw_name = "f2s-free-clk",
158 .name = "f2s-free-clk", },
159 };
160
161 static const struct clk_parent_data mpu_mux[] = {
162 { .fw_name = "mpu_free_clk",
163 .name = "mpu_free_clk", },
164 { .fw_name = "boot_clk",
165 .name = "boot_clk", },
166 };
167
168 static const struct clk_parent_data emac_mux[] = {
169 { .fw_name = "emaca_free_clk",
170 .name = "emaca_free_clk", },
171 { .fw_name = "emacb_free_clk",
172 .name = "emacb_free_clk", },
173 };
174
175 static const struct clk_parent_data noc_mux[] = {
176 { .fw_name = "noc_free_clk",
177 .name = "noc_free_clk", },
178 { .fw_name = "boot_clk",
179 .name = "boot_clk", },
180 };
181
182 static const struct clk_parent_data sdmmc_mux[] = {
183 { .fw_name = "sdmmc_free_clk",
184 .name = "sdmmc_free_clk", },
185 { .fw_name = "boot_clk",
186 .name = "boot_clk", },
187 };
188
189 static const struct clk_parent_data s2f_user0_mux[] = {
190 { .fw_name = "s2f_user0_free_clk",
191 .name = "s2f_user0_free_clk", },
192 { .fw_name = "boot_clk",
193 .name = "boot_clk", },
194 };
195
196 static const struct clk_parent_data s2f_user1_mux[] = {
197 { .fw_name = "s2f_user1_free_clk",
198 .name = "s2f_user1_free_clk", },
199 { .fw_name = "boot_clk",
200 .name = "boot_clk", },
201 };
202
203 static const struct clk_parent_data psi_mux[] = {
204 { .fw_name = "psi_ref_free_clk",
205 .name = "psi_ref_free_clk", },
206 { .fw_name = "boot_clk",
207 .name = "boot_clk", },
208 };
209
210 static const struct clk_parent_data gpio_db_mux[] = {
211 { .fw_name = "gpio_db_free_clk",
212 .name = "gpio_db_free_clk", },
213 { .fw_name = "boot_clk",
214 .name = "boot_clk", },
215 };
216
217 static const struct clk_parent_data emac_ptp_mux[] = {
218 { .fw_name = "emac_ptp_free_clk",
219 .name = "emac_ptp_free_clk", },
220 { .fw_name = "boot_clk",
221 .name = "boot_clk", },
222 };
223
224 /* clocks in AO (always on) controller */
225 static const struct stratix10_pll_clock agilex_pll_clks[] = {
226 { AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
227 0x0},
228 { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
229 0, 0x48},
230 { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
231 0, 0x9c},
232 };
233
234 static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
235 { AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
236 { AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
237 { AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x64},
238 { AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x68},
239 { AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xAC},
240 { AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xB0},
241 { AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xB8},
242 { AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xBC},
243 };
244
245 static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
246 { AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
247 0, 0x3C, 0, 0, 0},
248 { AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
249 0, 0x40, 0, 0, 0},
250 { AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
251 0, 4, 0x30, 1},
252 { AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
253 0, 0xD4, 0, 0x88, 0},
254 { AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
255 0, 0xD8, 0, 0x88, 1},
256 { AGILEX_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
257 ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2},
258 { AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
259 ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3},
260 { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
261 ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0, 0},
262 { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
263 ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30, 2},
264 { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
265 ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5},
266 { AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
267 ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6},
268 };
269
270 static const struct stratix10_gate_clock agilex_gate_clks[] = {
271 { AGILEX_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x24,
272 0, 0, 0, 0, 0x30, 0, 0},
273 { AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24,
274 0, 0, 0, 0, 0, 0, 4},
275 { AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24,
276 0, 0, 0, 0, 0, 0, 2},
277 { AGILEX_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
278 1, 0x44, 0, 2, 0x30, 1, 0},
279 { AGILEX_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
280 2, 0x44, 8, 2, 0x30, 1, 0},
281 /*
282 * The l4_sp_clk feeds a 100 MHz clock to various peripherals, one of them
283 * being the SP timers, thus cannot get gated.
284 */
285 { AGILEX_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x24,
286 3, 0x44, 16, 2, 0x30, 1, 0},
287 { AGILEX_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
288 4, 0x44, 24, 2, 0x30, 1, 0},
289 { AGILEX_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
290 4, 0x44, 26, 2, 0x30, 1, 0},
291 { AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24,
292 4, 0x44, 28, 1, 0, 0, 0},
293 { AGILEX_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
294 5, 0, 0, 0, 0x30, 1, 0},
295 { AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
296 0, 0, 0, 0, 0x94, 26, 0},
297 { AGILEX_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
298 1, 0, 0, 0, 0x94, 27, 0},
299 { AGILEX_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
300 2, 0, 0, 0, 0x94, 28, 0},
301 { AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, ARRAY_SIZE(emac_ptp_mux), 0, 0x7C,
302 3, 0, 0, 0, 0x88, 2, 0},
303 { AGILEX_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, ARRAY_SIZE(gpio_db_mux), 0, 0x7C,
304 4, 0x98, 0, 16, 0x88, 3, 0},
305 { AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C,
306 5, 0, 0, 0, 0x88, 4, 4},
307 { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, ARRAY_SIZE(s2f_user0_mux), 0, 0x24,
308 6, 0, 0, 0, 0x30, 2, 0},
309 { AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C,
310 6, 0, 0, 0, 0x88, 5, 0},
311 { AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C,
312 7, 0, 0, 0, 0x88, 6, 0},
313 { AGILEX_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
314 8, 0, 0, 0, 0, 0, 0},
315 { AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
316 9, 0, 0, 0, 0, 0, 0},
317 { AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
318 10, 0, 0, 0, 0, 0, 0},
319 { AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
320 10, 0, 0, 0, 0, 0, 4},
321 { AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
322 10, 0, 0, 0, 0, 0, 4},
323 };
324
agilex_clk_register_c_perip(const struct stratix10_perip_c_clock * clks,int nums,struct stratix10_clock_data * data)325 static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
326 int nums, struct stratix10_clock_data *data)
327 {
328 struct clk *clk;
329 void __iomem *base = data->base;
330 int i;
331
332 for (i = 0; i < nums; i++) {
333 clk = s10_register_periph(&clks[i], base);
334 if (IS_ERR(clk)) {
335 pr_err("%s: failed to register clock %s\n",
336 __func__, clks[i].name);
337 continue;
338 }
339 data->clk_data.clks[clks[i].id] = clk;
340 }
341 return 0;
342 }
343
agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock * clks,int nums,struct stratix10_clock_data * data)344 static int agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
345 int nums, struct stratix10_clock_data *data)
346 {
347 struct clk *clk;
348 void __iomem *base = data->base;
349 int i;
350
351 for (i = 0; i < nums; i++) {
352 clk = s10_register_cnt_periph(&clks[i], base);
353 if (IS_ERR(clk)) {
354 pr_err("%s: failed to register clock %s\n",
355 __func__, clks[i].name);
356 continue;
357 }
358 data->clk_data.clks[clks[i].id] = clk;
359 }
360
361 return 0;
362 }
363
agilex_clk_register_gate(const struct stratix10_gate_clock * clks,int nums,struct stratix10_clock_data * data)364 static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks, int nums, struct stratix10_clock_data *data)
365 {
366 struct clk *clk;
367 void __iomem *base = data->base;
368 int i;
369
370 for (i = 0; i < nums; i++) {
371 clk = s10_register_gate(&clks[i], base);
372 if (IS_ERR(clk)) {
373 pr_err("%s: failed to register clock %s\n",
374 __func__, clks[i].name);
375 continue;
376 }
377 data->clk_data.clks[clks[i].id] = clk;
378 }
379
380 return 0;
381 }
382
agilex_clk_register_pll(const struct stratix10_pll_clock * clks,int nums,struct stratix10_clock_data * data)383 static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
384 int nums, struct stratix10_clock_data *data)
385 {
386 struct clk *clk;
387 void __iomem *base = data->base;
388 int i;
389
390 for (i = 0; i < nums; i++) {
391 clk = agilex_register_pll(&clks[i], base);
392 if (IS_ERR(clk)) {
393 pr_err("%s: failed to register clock %s\n",
394 __func__, clks[i].name);
395 continue;
396 }
397 data->clk_data.clks[clks[i].id] = clk;
398 }
399
400 return 0;
401 }
402
__socfpga_agilex_clk_init(struct platform_device * pdev,int nr_clks)403 static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_device *pdev,
404 int nr_clks)
405 {
406 struct device_node *np = pdev->dev.of_node;
407 struct device *dev = &pdev->dev;
408 struct stratix10_clock_data *clk_data;
409 struct clk **clk_table;
410 struct resource *res;
411 void __iomem *base;
412 int ret;
413
414 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
415 base = devm_ioremap_resource(dev, res);
416 if (IS_ERR(base))
417 return ERR_CAST(base);
418
419 clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
420 if (!clk_data)
421 return ERR_PTR(-ENOMEM);
422
423 clk_data->base = base;
424 clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
425 if (!clk_table)
426 return ERR_PTR(-ENOMEM);
427
428 clk_data->clk_data.clks = clk_table;
429 clk_data->clk_data.clk_num = nr_clks;
430 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
431 if (ret)
432 return ERR_PTR(ret);
433
434 return clk_data;
435 }
436
agilex_clkmgr_probe(struct platform_device * pdev)437 static int agilex_clkmgr_probe(struct platform_device *pdev)
438 {
439 struct stratix10_clock_data *clk_data;
440
441 clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
442 if (IS_ERR(clk_data))
443 return PTR_ERR(clk_data);
444
445 agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
446
447 agilex_clk_register_c_perip(agilex_main_perip_c_clks,
448 ARRAY_SIZE(agilex_main_perip_c_clks), clk_data);
449
450 agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
451 ARRAY_SIZE(agilex_main_perip_cnt_clks),
452 clk_data);
453
454 agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
455 clk_data);
456 return 0;
457 }
458
459 static const struct of_device_id agilex_clkmgr_match_table[] = {
460 { .compatible = "intel,agilex-clkmgr",
461 .data = agilex_clkmgr_probe },
462 { }
463 };
464
465 static struct platform_driver agilex_clkmgr_driver = {
466 .probe = agilex_clkmgr_probe,
467 .driver = {
468 .name = "agilex-clkmgr",
469 .suppress_bind_attrs = true,
470 .of_match_table = agilex_clkmgr_match_table,
471 },
472 };
473
agilex_clk_init(void)474 static int __init agilex_clk_init(void)
475 {
476 return platform_driver_register(&agilex_clkmgr_driver);
477 }
478 core_initcall(agilex_clk_init);
479