1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2015 - 2020 Intel Corporation */
3 #include <linux/workqueue.h>
4 #include <linux/pci.h>
5 #include <linux/device.h>
6 #include <linux/iommu.h>
7 #include "adf_common_drv.h"
8 #include "adf_cfg.h"
9 #include "adf_pf2vf_msg.h"
10
11 static struct workqueue_struct *pf2vf_resp_wq;
12
13 #define ME2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190)
14 #define ME2FUNCTION_MAP_A_NUM_REGS 96
15
16 #define ME2FUNCTION_MAP_B_OFFSET (0x3A400 + 0x310)
17 #define ME2FUNCTION_MAP_B_NUM_REGS 12
18
19 #define ME2FUNCTION_MAP_REG_SIZE 4
20 #define ME2FUNCTION_MAP_VALID BIT(7)
21
22 #define READ_CSR_ME2FUNCTION_MAP_A(pmisc_bar_addr, index) \
23 ADF_CSR_RD(pmisc_bar_addr, ME2FUNCTION_MAP_A_OFFSET + \
24 ME2FUNCTION_MAP_REG_SIZE * index)
25
26 #define WRITE_CSR_ME2FUNCTION_MAP_A(pmisc_bar_addr, index, value) \
27 ADF_CSR_WR(pmisc_bar_addr, ME2FUNCTION_MAP_A_OFFSET + \
28 ME2FUNCTION_MAP_REG_SIZE * index, value)
29
30 #define READ_CSR_ME2FUNCTION_MAP_B(pmisc_bar_addr, index) \
31 ADF_CSR_RD(pmisc_bar_addr, ME2FUNCTION_MAP_B_OFFSET + \
32 ME2FUNCTION_MAP_REG_SIZE * index)
33
34 #define WRITE_CSR_ME2FUNCTION_MAP_B(pmisc_bar_addr, index, value) \
35 ADF_CSR_WR(pmisc_bar_addr, ME2FUNCTION_MAP_B_OFFSET + \
36 ME2FUNCTION_MAP_REG_SIZE * index, value)
37
38 struct adf_pf2vf_resp {
39 struct work_struct pf2vf_resp_work;
40 struct adf_accel_vf_info *vf_info;
41 };
42
adf_iov_send_resp(struct work_struct * work)43 static void adf_iov_send_resp(struct work_struct *work)
44 {
45 struct adf_pf2vf_resp *pf2vf_resp =
46 container_of(work, struct adf_pf2vf_resp, pf2vf_resp_work);
47
48 adf_vf2pf_req_hndl(pf2vf_resp->vf_info);
49 kfree(pf2vf_resp);
50 }
51
adf_vf2pf_bh_handler(void * data)52 static void adf_vf2pf_bh_handler(void *data)
53 {
54 struct adf_accel_vf_info *vf_info = (struct adf_accel_vf_info *)data;
55 struct adf_pf2vf_resp *pf2vf_resp;
56
57 pf2vf_resp = kzalloc(sizeof(*pf2vf_resp), GFP_ATOMIC);
58 if (!pf2vf_resp)
59 return;
60
61 pf2vf_resp->vf_info = vf_info;
62 INIT_WORK(&pf2vf_resp->pf2vf_resp_work, adf_iov_send_resp);
63 queue_work(pf2vf_resp_wq, &pf2vf_resp->pf2vf_resp_work);
64 }
65
adf_enable_sriov(struct adf_accel_dev * accel_dev)66 static int adf_enable_sriov(struct adf_accel_dev *accel_dev)
67 {
68 struct pci_dev *pdev = accel_to_pci_dev(accel_dev);
69 int totalvfs = pci_sriov_get_totalvfs(pdev);
70 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
71 struct adf_bar *pmisc =
72 &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
73 void __iomem *pmisc_addr = pmisc->virt_addr;
74 struct adf_accel_vf_info *vf_info;
75 int i;
76 u32 reg;
77
78 for (i = 0, vf_info = accel_dev->pf.vf_info; i < totalvfs;
79 i++, vf_info++) {
80 /* This ptr will be populated when VFs will be created */
81 vf_info->accel_dev = accel_dev;
82 vf_info->vf_nr = i;
83
84 tasklet_init(&vf_info->vf2pf_bh_tasklet,
85 (void *)adf_vf2pf_bh_handler,
86 (unsigned long)vf_info);
87 mutex_init(&vf_info->pf2vf_lock);
88 ratelimit_state_init(&vf_info->vf2pf_ratelimit,
89 DEFAULT_RATELIMIT_INTERVAL,
90 DEFAULT_RATELIMIT_BURST);
91 }
92
93 /* Set Valid bits in ME Thread to PCIe Function Mapping Group A */
94 for (i = 0; i < ME2FUNCTION_MAP_A_NUM_REGS; i++) {
95 reg = READ_CSR_ME2FUNCTION_MAP_A(pmisc_addr, i);
96 reg |= ME2FUNCTION_MAP_VALID;
97 WRITE_CSR_ME2FUNCTION_MAP_A(pmisc_addr, i, reg);
98 }
99
100 /* Set Valid bits in ME Thread to PCIe Function Mapping Group B */
101 for (i = 0; i < ME2FUNCTION_MAP_B_NUM_REGS; i++) {
102 reg = READ_CSR_ME2FUNCTION_MAP_B(pmisc_addr, i);
103 reg |= ME2FUNCTION_MAP_VALID;
104 WRITE_CSR_ME2FUNCTION_MAP_B(pmisc_addr, i, reg);
105 }
106
107 /* Enable VF to PF interrupts for all VFs */
108 adf_enable_vf2pf_interrupts(accel_dev, GENMASK_ULL(totalvfs - 1, 0));
109
110 /*
111 * Due to the hardware design, when SR-IOV and the ring arbiter
112 * are enabled all the VFs supported in hardware must be enabled in
113 * order for all the hardware resources (i.e. bundles) to be usable.
114 * When SR-IOV is enabled, each of the VFs will own one bundle.
115 */
116 return pci_enable_sriov(pdev, totalvfs);
117 }
118
119 /**
120 * adf_disable_sriov() - Disable SRIOV for the device
121 * @accel_dev: Pointer to accel device.
122 *
123 * Function disables SRIOV for the accel device.
124 *
125 * Return: 0 on success, error code otherwise.
126 */
adf_disable_sriov(struct adf_accel_dev * accel_dev)127 void adf_disable_sriov(struct adf_accel_dev *accel_dev)
128 {
129 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
130 struct adf_bar *pmisc =
131 &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
132 void __iomem *pmisc_addr = pmisc->virt_addr;
133 int totalvfs = pci_sriov_get_totalvfs(accel_to_pci_dev(accel_dev));
134 struct adf_accel_vf_info *vf;
135 u32 reg;
136 int i;
137
138 if (!accel_dev->pf.vf_info)
139 return;
140
141 adf_pf2vf_notify_restarting(accel_dev);
142
143 pci_disable_sriov(accel_to_pci_dev(accel_dev));
144
145 /* Disable VF to PF interrupts */
146 adf_disable_vf2pf_interrupts(accel_dev, 0xFFFFFFFF);
147
148 /* Clear Valid bits in ME Thread to PCIe Function Mapping Group A */
149 for (i = 0; i < ME2FUNCTION_MAP_A_NUM_REGS; i++) {
150 reg = READ_CSR_ME2FUNCTION_MAP_A(pmisc_addr, i);
151 reg &= ~ME2FUNCTION_MAP_VALID;
152 WRITE_CSR_ME2FUNCTION_MAP_A(pmisc_addr, i, reg);
153 }
154
155 /* Clear Valid bits in ME Thread to PCIe Function Mapping Group B */
156 for (i = 0; i < ME2FUNCTION_MAP_B_NUM_REGS; i++) {
157 reg = READ_CSR_ME2FUNCTION_MAP_B(pmisc_addr, i);
158 reg &= ~ME2FUNCTION_MAP_VALID;
159 WRITE_CSR_ME2FUNCTION_MAP_B(pmisc_addr, i, reg);
160 }
161
162 for (i = 0, vf = accel_dev->pf.vf_info; i < totalvfs; i++, vf++) {
163 tasklet_disable(&vf->vf2pf_bh_tasklet);
164 tasklet_kill(&vf->vf2pf_bh_tasklet);
165 mutex_destroy(&vf->pf2vf_lock);
166 }
167
168 kfree(accel_dev->pf.vf_info);
169 accel_dev->pf.vf_info = NULL;
170 }
171 EXPORT_SYMBOL_GPL(adf_disable_sriov);
172
173 /**
174 * adf_sriov_configure() - Enable SRIOV for the device
175 * @pdev: Pointer to pci device.
176 * @numvfs: Number of virtual functions (VFs) to enable.
177 *
178 * Note that the @numvfs parameter is ignored and all VFs supported by the
179 * device are enabled due to the design of the hardware.
180 *
181 * Function enables SRIOV for the pci device.
182 *
183 * Return: number of VFs enabled on success, error code otherwise.
184 */
adf_sriov_configure(struct pci_dev * pdev,int numvfs)185 int adf_sriov_configure(struct pci_dev *pdev, int numvfs)
186 {
187 struct adf_accel_dev *accel_dev = adf_devmgr_pci_to_accel_dev(pdev);
188 int totalvfs = pci_sriov_get_totalvfs(pdev);
189 unsigned long val;
190 int ret;
191
192 if (!accel_dev) {
193 dev_err(&pdev->dev, "Failed to find accel_dev\n");
194 return -EFAULT;
195 }
196
197 if (!iommu_present(&pci_bus_type))
198 dev_warn(&pdev->dev, "IOMMU should be enabled for SR-IOV to work correctly\n");
199
200 if (accel_dev->pf.vf_info) {
201 dev_info(&pdev->dev, "Already enabled for this device\n");
202 return -EINVAL;
203 }
204
205 if (adf_dev_started(accel_dev)) {
206 if (adf_devmgr_in_reset(accel_dev) ||
207 adf_dev_in_use(accel_dev)) {
208 dev_err(&GET_DEV(accel_dev), "Device busy\n");
209 return -EBUSY;
210 }
211
212 adf_dev_stop(accel_dev);
213 adf_dev_shutdown(accel_dev);
214 }
215
216 if (adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC))
217 return -EFAULT;
218 val = 0;
219 if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
220 ADF_NUM_CY, (void *)&val, ADF_DEC))
221 return -EFAULT;
222
223 set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status);
224
225 /* Allocate memory for VF info structs */
226 accel_dev->pf.vf_info = kcalloc(totalvfs,
227 sizeof(struct adf_accel_vf_info),
228 GFP_KERNEL);
229 if (!accel_dev->pf.vf_info)
230 return -ENOMEM;
231
232 if (adf_dev_init(accel_dev)) {
233 dev_err(&GET_DEV(accel_dev), "Failed to init qat_dev%d\n",
234 accel_dev->accel_id);
235 return -EFAULT;
236 }
237
238 if (adf_dev_start(accel_dev)) {
239 dev_err(&GET_DEV(accel_dev), "Failed to start qat_dev%d\n",
240 accel_dev->accel_id);
241 return -EFAULT;
242 }
243
244 ret = adf_enable_sriov(accel_dev);
245 if (ret)
246 return ret;
247
248 return numvfs;
249 }
250 EXPORT_SYMBOL_GPL(adf_sriov_configure);
251
adf_init_pf_wq(void)252 int __init adf_init_pf_wq(void)
253 {
254 /* Workqueue for PF2VF responses */
255 pf2vf_resp_wq = alloc_workqueue("qat_pf2vf_resp_wq", WQ_MEM_RECLAIM, 0);
256
257 return !pf2vf_resp_wq ? -ENOMEM : 0;
258 }
259
adf_exit_pf_wq(void)260 void adf_exit_pf_wq(void)
261 {
262 if (pf2vf_resp_wq) {
263 destroy_workqueue(pf2vf_resp_wq);
264 pf2vf_resp_wq = NULL;
265 }
266 }
267