1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Intel(R) 10nm server memory controller.
4 * Copyright (c) 2019, Intel Corporation.
5 *
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/io.h>
10 #include <asm/cpu_device_id.h>
11 #include <asm/intel-family.h>
12 #include <asm/mce.h>
13 #include "edac_module.h"
14 #include "skx_common.h"
15
16 #define I10NM_REVISION "v0.0.3"
17 #define EDAC_MOD_STR "i10nm_edac"
18
19 /* Debug macros */
20 #define i10nm_printk(level, fmt, arg...) \
21 edac_printk(level, "i10nm", fmt, ##arg)
22
23 #define I10NM_GET_SCK_BAR(d, reg) \
24 pci_read_config_dword((d)->uracu, 0xd0, &(reg))
25 #define I10NM_GET_IMC_BAR(d, i, reg) \
26 pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))
27 #define I10NM_GET_DIMMMTR(m, i, j) \
28 readl((m)->mbase + 0x2080c + (i) * 0x4000 + (j) * 4)
29 #define I10NM_GET_MCDDRTCFG(m, i) \
30 readl((m)->mbase + 0x20970 + (i) * 0x4000)
31 #define I10NM_GET_MCMTR(m, i) \
32 readl((m)->mbase + 0x20ef8 + (i) * 0x4000)
33
34 #define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23)
35 #define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12)
36 #define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \
37 GET_BITFIELD(reg, 0, 10) + 1) << 12)
38
39 static struct list_head *i10nm_edac_list;
40
pci_get_dev_wrapper(int dom,unsigned int bus,unsigned int dev,unsigned int fun)41 static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus,
42 unsigned int dev, unsigned int fun)
43 {
44 struct pci_dev *pdev;
45
46 pdev = pci_get_domain_bus_and_slot(dom, bus, PCI_DEVFN(dev, fun));
47 if (!pdev) {
48 edac_dbg(2, "No device %02x:%02x.%x\n",
49 bus, dev, fun);
50 return NULL;
51 }
52
53 if (unlikely(pci_enable_device(pdev) < 0)) {
54 edac_dbg(2, "Failed to enable device %02x:%02x.%x\n",
55 bus, dev, fun);
56 return NULL;
57 }
58
59 pci_dev_get(pdev);
60
61 return pdev;
62 }
63
i10nm_get_all_munits(void)64 static int i10nm_get_all_munits(void)
65 {
66 struct pci_dev *mdev;
67 void __iomem *mbase;
68 unsigned long size;
69 struct skx_dev *d;
70 int i, j = 0;
71 u32 reg, off;
72 u64 base;
73
74 list_for_each_entry(d, i10nm_edac_list, list) {
75 d->util_all = pci_get_dev_wrapper(d->seg, d->bus[1], 29, 1);
76 if (!d->util_all)
77 return -ENODEV;
78
79 d->uracu = pci_get_dev_wrapper(d->seg, d->bus[0], 0, 1);
80 if (!d->uracu)
81 return -ENODEV;
82
83 if (I10NM_GET_SCK_BAR(d, reg)) {
84 i10nm_printk(KERN_ERR, "Failed to socket bar\n");
85 return -ENODEV;
86 }
87
88 base = I10NM_GET_SCK_MMIO_BASE(reg);
89 edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n",
90 j++, base, reg);
91
92 for (i = 0; i < I10NM_NUM_IMC; i++) {
93 mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
94 12 + i, 0);
95 if (i == 0 && !mdev) {
96 i10nm_printk(KERN_ERR, "No IMC found\n");
97 return -ENODEV;
98 }
99 if (!mdev)
100 continue;
101
102 d->imc[i].mdev = mdev;
103
104 if (I10NM_GET_IMC_BAR(d, i, reg)) {
105 i10nm_printk(KERN_ERR, "Failed to get mc bar\n");
106 return -ENODEV;
107 }
108
109 off = I10NM_GET_IMC_MMIO_OFFSET(reg);
110 size = I10NM_GET_IMC_MMIO_SIZE(reg);
111 edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n",
112 i, base + off, size, reg);
113
114 mbase = ioremap(base + off, size);
115 if (!mbase) {
116 i10nm_printk(KERN_ERR, "Failed to ioremap 0x%llx\n",
117 base + off);
118 return -ENODEV;
119 }
120
121 d->imc[i].mbase = mbase;
122 }
123 }
124
125 return 0;
126 }
127
128 static struct res_config i10nm_cfg0 = {
129 .type = I10NM,
130 .decs_did = 0x3452,
131 .busno_cfg_offset = 0xcc,
132 };
133
134 static struct res_config i10nm_cfg1 = {
135 .type = I10NM,
136 .decs_did = 0x3452,
137 .busno_cfg_offset = 0xd0,
138 };
139
140 static const struct x86_cpu_id i10nm_cpuids[] = {
141 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
142 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
143 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
144 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
145 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D, X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
146 {}
147 };
148 MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
149
i10nm_check_ecc(struct skx_imc * imc,int chan)150 static bool i10nm_check_ecc(struct skx_imc *imc, int chan)
151 {
152 u32 mcmtr;
153
154 mcmtr = I10NM_GET_MCMTR(imc, chan);
155 edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr);
156
157 return !!GET_BITFIELD(mcmtr, 2, 2);
158 }
159
i10nm_get_dimm_config(struct mem_ctl_info * mci)160 static int i10nm_get_dimm_config(struct mem_ctl_info *mci)
161 {
162 struct skx_pvt *pvt = mci->pvt_info;
163 struct skx_imc *imc = pvt->imc;
164 struct dimm_info *dimm;
165 u32 mtr, mcddrtcfg;
166 int i, j, ndimms;
167
168 for (i = 0; i < I10NM_NUM_CHANNELS; i++) {
169 if (!imc->mbase)
170 continue;
171
172 ndimms = 0;
173 mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
174 for (j = 0; j < I10NM_NUM_DIMMS; j++) {
175 dimm = edac_get_dimm(mci, i, j, 0);
176 mtr = I10NM_GET_DIMMMTR(imc, i, j);
177 edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n",
178 mtr, mcddrtcfg, imc->mc, i, j);
179
180 if (IS_DIMM_PRESENT(mtr))
181 ndimms += skx_get_dimm_info(mtr, 0, 0, dimm,
182 imc, i, j);
183 else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
184 ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
185 EDAC_MOD_STR);
186 }
187 if (ndimms && !i10nm_check_ecc(imc, i)) {
188 i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",
189 imc->mc, i);
190 return -ENODEV;
191 }
192 }
193
194 return 0;
195 }
196
197 static struct notifier_block i10nm_mce_dec = {
198 .notifier_call = skx_mce_check_error,
199 .priority = MCE_PRIO_EDAC,
200 };
201
202 #ifdef CONFIG_EDAC_DEBUG
203 /*
204 * Debug feature.
205 * Exercise the address decode logic by writing an address to
206 * /sys/kernel/debug/edac/i10nm_test/addr.
207 */
208 static struct dentry *i10nm_test;
209
debugfs_u64_set(void * data,u64 val)210 static int debugfs_u64_set(void *data, u64 val)
211 {
212 struct mce m;
213
214 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
215
216 memset(&m, 0, sizeof(m));
217 /* ADDRV + MemRd + Unknown channel */
218 m.status = MCI_STATUS_ADDRV + 0x90;
219 /* One corrected error */
220 m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
221 m.addr = val;
222 skx_mce_check_error(NULL, 0, &m);
223
224 return 0;
225 }
226 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
227
setup_i10nm_debug(void)228 static void setup_i10nm_debug(void)
229 {
230 i10nm_test = edac_debugfs_create_dir("i10nm_test");
231 if (!i10nm_test)
232 return;
233
234 if (!edac_debugfs_create_file("addr", 0200, i10nm_test,
235 NULL, &fops_u64_wo)) {
236 debugfs_remove(i10nm_test);
237 i10nm_test = NULL;
238 }
239 }
240
teardown_i10nm_debug(void)241 static void teardown_i10nm_debug(void)
242 {
243 debugfs_remove_recursive(i10nm_test);
244 }
245 #else
setup_i10nm_debug(void)246 static inline void setup_i10nm_debug(void) {}
teardown_i10nm_debug(void)247 static inline void teardown_i10nm_debug(void) {}
248 #endif /*CONFIG_EDAC_DEBUG*/
249
i10nm_init(void)250 static int __init i10nm_init(void)
251 {
252 u8 mc = 0, src_id = 0, node_id = 0;
253 const struct x86_cpu_id *id;
254 struct res_config *cfg;
255 const char *owner;
256 struct skx_dev *d;
257 int rc, i, off[3] = {0xd0, 0xc8, 0xcc};
258 u64 tolm, tohm;
259
260 edac_dbg(2, "\n");
261
262 owner = edac_get_owner();
263 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
264 return -EBUSY;
265
266 if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
267 return -ENODEV;
268
269 id = x86_match_cpu(i10nm_cpuids);
270 if (!id)
271 return -ENODEV;
272
273 cfg = (struct res_config *)id->driver_data;
274
275 rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm);
276 if (rc)
277 return rc;
278
279 rc = skx_get_all_bus_mappings(cfg, &i10nm_edac_list);
280 if (rc < 0)
281 goto fail;
282 if (rc == 0) {
283 i10nm_printk(KERN_ERR, "No memory controllers found\n");
284 return -ENODEV;
285 }
286
287 rc = i10nm_get_all_munits();
288 if (rc < 0)
289 goto fail;
290
291 list_for_each_entry(d, i10nm_edac_list, list) {
292 rc = skx_get_src_id(d, 0xf8, &src_id);
293 if (rc < 0)
294 goto fail;
295
296 rc = skx_get_node_id(d, &node_id);
297 if (rc < 0)
298 goto fail;
299
300 edac_dbg(2, "src_id = %d node_id = %d\n", src_id, node_id);
301 for (i = 0; i < I10NM_NUM_IMC; i++) {
302 if (!d->imc[i].mdev)
303 continue;
304
305 d->imc[i].mc = mc++;
306 d->imc[i].lmc = i;
307 d->imc[i].src_id = src_id;
308 d->imc[i].node_id = node_id;
309
310 rc = skx_register_mci(&d->imc[i], d->imc[i].mdev,
311 "Intel_10nm Socket", EDAC_MOD_STR,
312 i10nm_get_dimm_config);
313 if (rc < 0)
314 goto fail;
315 }
316 }
317
318 rc = skx_adxl_get();
319 if (rc)
320 goto fail;
321
322 opstate_init();
323 mce_register_decode_chain(&i10nm_mce_dec);
324 setup_i10nm_debug();
325
326 i10nm_printk(KERN_INFO, "%s\n", I10NM_REVISION);
327
328 return 0;
329 fail:
330 skx_remove();
331 return rc;
332 }
333
i10nm_exit(void)334 static void __exit i10nm_exit(void)
335 {
336 edac_dbg(2, "\n");
337 teardown_i10nm_debug();
338 mce_unregister_decode_chain(&i10nm_mce_dec);
339 skx_adxl_put();
340 skx_remove();
341 }
342
343 module_init(i10nm_init);
344 module_exit(i10nm_exit);
345
346 MODULE_LICENSE("GPL v2");
347 MODULE_DESCRIPTION("MC Driver for Intel 10nm server processors");
348