1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 */
5
6 #include "dsi_cfg.h"
7
8 static const char * const dsi_v2_bus_clk_names[] = {
9 "core_mmss", "iface", "bus",
10 };
11
12 static const struct msm_dsi_config apq8064_dsi_cfg = {
13 .io_offset = 0,
14 .reg_cfg = {
15 .num = 3,
16 .regs = {
17 {"vdda", 100000, 100}, /* 1.2 V */
18 {"avdd", 10000, 100}, /* 3.0 V */
19 {"vddio", 100000, 100}, /* 1.8 V */
20 },
21 },
22 .bus_clk_names = dsi_v2_bus_clk_names,
23 .num_bus_clks = ARRAY_SIZE(dsi_v2_bus_clk_names),
24 .io_start = { 0x4700000, 0x5800000 },
25 .num_dsi = 2,
26 };
27
28 static const char * const dsi_6g_bus_clk_names[] = {
29 "mdp_core", "iface", "bus", "core_mmss",
30 };
31
32 static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = {
33 .io_offset = DSI_6G_REG_SHIFT,
34 .reg_cfg = {
35 .num = 4,
36 .regs = {
37 {"gdsc", -1, -1},
38 {"vdd", 150000, 100}, /* 3.0 V */
39 {"vdda", 100000, 100}, /* 1.2 V */
40 {"vddio", 100000, 100}, /* 1.8 V */
41 },
42 },
43 .bus_clk_names = dsi_6g_bus_clk_names,
44 .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
45 .io_start = { 0xfd922800, 0xfd922b00 },
46 .num_dsi = 2,
47 };
48
49 static const char * const dsi_8916_bus_clk_names[] = {
50 "mdp_core", "iface", "bus",
51 };
52
53 static const struct msm_dsi_config msm8916_dsi_cfg = {
54 .io_offset = DSI_6G_REG_SHIFT,
55 .reg_cfg = {
56 .num = 3,
57 .regs = {
58 {"gdsc", -1, -1},
59 {"vdda", 100000, 100}, /* 1.2 V */
60 {"vddio", 100000, 100}, /* 1.8 V */
61 },
62 },
63 .bus_clk_names = dsi_8916_bus_clk_names,
64 .num_bus_clks = ARRAY_SIZE(dsi_8916_bus_clk_names),
65 .io_start = { 0x1a98000 },
66 .num_dsi = 1,
67 };
68
69 static const char * const dsi_8976_bus_clk_names[] = {
70 "mdp_core", "iface", "bus",
71 };
72
73 static const struct msm_dsi_config msm8976_dsi_cfg = {
74 .io_offset = DSI_6G_REG_SHIFT,
75 .reg_cfg = {
76 .num = 3,
77 .regs = {
78 {"gdsc", -1, -1},
79 {"vdda", 100000, 100}, /* 1.2 V */
80 {"vddio", 100000, 100}, /* 1.8 V */
81 },
82 },
83 .bus_clk_names = dsi_8976_bus_clk_names,
84 .num_bus_clks = ARRAY_SIZE(dsi_8976_bus_clk_names),
85 .io_start = { 0x1a94000, 0x1a96000 },
86 .num_dsi = 2,
87 };
88
89 static const struct msm_dsi_config msm8994_dsi_cfg = {
90 .io_offset = DSI_6G_REG_SHIFT,
91 .reg_cfg = {
92 .num = 7,
93 .regs = {
94 {"gdsc", -1, -1},
95 {"vdda", 100000, 100}, /* 1.25 V */
96 {"vddio", 100000, 100}, /* 1.8 V */
97 {"vcca", 10000, 100}, /* 1.0 V */
98 {"vdd", 100000, 100}, /* 1.8 V */
99 {"lab_reg", -1, -1},
100 {"ibb_reg", -1, -1},
101 },
102 },
103 .bus_clk_names = dsi_6g_bus_clk_names,
104 .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
105 .io_start = { 0xfd998000, 0xfd9a0000 },
106 .num_dsi = 2,
107 };
108
109 /*
110 * TODO: core_mmss_clk fails to enable for some reason, but things work fine
111 * without it too. Figure out why it doesn't enable and uncomment below
112 */
113 static const char * const dsi_8996_bus_clk_names[] = {
114 "mdp_core", "iface", "bus", /* "core_mmss", */
115 };
116
117 static const struct msm_dsi_config msm8996_dsi_cfg = {
118 .io_offset = DSI_6G_REG_SHIFT,
119 .reg_cfg = {
120 .num = 2,
121 .regs = {
122 {"vdda", 18160, 1 }, /* 1.25 V */
123 {"vcca", 17000, 32 }, /* 0.925 V */
124 {"vddio", 100000, 100 },/* 1.8 V */
125 },
126 },
127 .bus_clk_names = dsi_8996_bus_clk_names,
128 .num_bus_clks = ARRAY_SIZE(dsi_8996_bus_clk_names),
129 .io_start = { 0x994000, 0x996000 },
130 .num_dsi = 2,
131 };
132
133 static const char * const dsi_msm8998_bus_clk_names[] = {
134 "iface", "bus", "core",
135 };
136
137 static const struct msm_dsi_config msm8998_dsi_cfg = {
138 .io_offset = DSI_6G_REG_SHIFT,
139 .reg_cfg = {
140 .num = 2,
141 .regs = {
142 {"vdd", 367000, 16 }, /* 0.9 V */
143 {"vdda", 62800, 2 }, /* 1.2 V */
144 },
145 },
146 .bus_clk_names = dsi_msm8998_bus_clk_names,
147 .num_bus_clks = ARRAY_SIZE(dsi_msm8998_bus_clk_names),
148 .io_start = { 0xc994000, 0xc996000 },
149 .num_dsi = 2,
150 };
151
152 static const char * const dsi_sdm660_bus_clk_names[] = {
153 "iface", "bus", "core", "core_mmss",
154 };
155
156 static const struct msm_dsi_config sdm660_dsi_cfg = {
157 .io_offset = DSI_6G_REG_SHIFT,
158 .reg_cfg = {
159 .num = 2,
160 .regs = {
161 {"vdda", 12560, 4 }, /* 1.2 V */
162 },
163 },
164 .bus_clk_names = dsi_sdm660_bus_clk_names,
165 .num_bus_clks = ARRAY_SIZE(dsi_sdm660_bus_clk_names),
166 .io_start = { 0xc994000, 0xc996000 },
167 .num_dsi = 2,
168 };
169
170 static const char * const dsi_sdm845_bus_clk_names[] = {
171 "iface", "bus",
172 };
173
174 static const char * const dsi_sc7180_bus_clk_names[] = {
175 "iface", "bus",
176 };
177
178 static const struct msm_dsi_config sdm845_dsi_cfg = {
179 .io_offset = DSI_6G_REG_SHIFT,
180 .reg_cfg = {
181 .num = 1,
182 .regs = {
183 {"vdda", 21800, 4 }, /* 1.2 V */
184 },
185 },
186 .bus_clk_names = dsi_sdm845_bus_clk_names,
187 .num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names),
188 .io_start = { 0xae94000, 0xae96000 },
189 .num_dsi = 2,
190 };
191
192 static const struct msm_dsi_config sc7180_dsi_cfg = {
193 .io_offset = DSI_6G_REG_SHIFT,
194 .reg_cfg = {
195 .num = 1,
196 .regs = {
197 {"vdda", 21800, 4 }, /* 1.2 V */
198 },
199 },
200 .bus_clk_names = dsi_sc7180_bus_clk_names,
201 .num_bus_clks = ARRAY_SIZE(dsi_sc7180_bus_clk_names),
202 .io_start = { 0xae94000 },
203 .num_dsi = 1,
204 };
205
206 static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
207 .link_clk_set_rate = dsi_link_clk_set_rate_v2,
208 .link_clk_enable = dsi_link_clk_enable_v2,
209 .link_clk_disable = dsi_link_clk_disable_v2,
210 .clk_init_ver = dsi_clk_init_v2,
211 .tx_buf_alloc = dsi_tx_buf_alloc_v2,
212 .tx_buf_get = dsi_tx_buf_get_v2,
213 .tx_buf_put = NULL,
214 .dma_base_get = dsi_dma_base_get_v2,
215 .calc_clk_rate = dsi_calc_clk_rate_v2,
216 };
217
218 static const struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
219 .link_clk_set_rate = dsi_link_clk_set_rate_6g,
220 .link_clk_enable = dsi_link_clk_enable_6g,
221 .link_clk_disable = dsi_link_clk_disable_6g,
222 .clk_init_ver = NULL,
223 .tx_buf_alloc = dsi_tx_buf_alloc_6g,
224 .tx_buf_get = dsi_tx_buf_get_6g,
225 .tx_buf_put = dsi_tx_buf_put_6g,
226 .dma_base_get = dsi_dma_base_get_6g,
227 .calc_clk_rate = dsi_calc_clk_rate_6g,
228 };
229
230 static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
231 .link_clk_set_rate = dsi_link_clk_set_rate_6g,
232 .link_clk_enable = dsi_link_clk_enable_6g,
233 .link_clk_disable = dsi_link_clk_disable_6g,
234 .clk_init_ver = dsi_clk_init_6g_v2,
235 .tx_buf_alloc = dsi_tx_buf_alloc_6g,
236 .tx_buf_get = dsi_tx_buf_get_6g,
237 .tx_buf_put = dsi_tx_buf_put_6g,
238 .dma_base_get = dsi_dma_base_get_6g,
239 .calc_clk_rate = dsi_calc_clk_rate_6g,
240 };
241
242 static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
243 {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
244 &apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
245 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0,
246 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
247 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1,
248 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
249 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1,
250 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
251 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_2,
252 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
253 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3,
254 &msm8994_dsi_cfg, &msm_dsi_6g_host_ops},
255 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1,
256 &msm8916_dsi_cfg, &msm_dsi_6g_host_ops},
257 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1,
258 &msm8996_dsi_cfg, &msm_dsi_6g_host_ops},
259 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_2,
260 &msm8976_dsi_cfg, &msm_dsi_6g_host_ops},
261 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_1_0,
262 &sdm660_dsi_cfg, &msm_dsi_6g_v2_host_ops},
263 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_0,
264 &msm8998_dsi_cfg, &msm_dsi_6g_v2_host_ops},
265 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
266 &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
267 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0,
268 &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
269 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0,
270 &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
271 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1,
272 &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops},
273 };
274
msm_dsi_cfg_get(u32 major,u32 minor)275 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
276 {
277 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
278 int i;
279
280 for (i = ARRAY_SIZE(dsi_cfg_handlers) - 1; i >= 0; i--) {
281 if ((dsi_cfg_handlers[i].major == major) &&
282 (dsi_cfg_handlers[i].minor == minor)) {
283 cfg_hnd = &dsi_cfg_handlers[i];
284 break;
285 }
286 }
287
288 return cfg_hnd;
289 }
290
291