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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * rcar_du_kms.c  --  R-Car Display Unit Mode Setting
4  *
5  * Copyright (C) 2013-2015 Renesas Electronics Corporation
6  *
7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8  */
9 
10 #include <drm/drm_atomic.h>
11 #include <drm/drm_atomic_helper.h>
12 #include <drm/drm_crtc.h>
13 #include <drm/drm_device.h>
14 #include <drm/drm_fb_cma_helper.h>
15 #include <drm/drm_gem_cma_helper.h>
16 #include <drm/drm_gem_framebuffer_helper.h>
17 #include <drm/drm_probe_helper.h>
18 #include <drm/drm_vblank.h>
19 
20 #include <linux/device.h>
21 #include <linux/of_graph.h>
22 #include <linux/of_platform.h>
23 #include <linux/wait.h>
24 
25 #include "rcar_du_crtc.h"
26 #include "rcar_du_drv.h"
27 #include "rcar_du_encoder.h"
28 #include "rcar_du_kms.h"
29 #include "rcar_du_regs.h"
30 #include "rcar_du_vsp.h"
31 #include "rcar_du_writeback.h"
32 
33 /* -----------------------------------------------------------------------------
34  * Format helpers
35  */
36 
37 static const struct rcar_du_format_info rcar_du_format_infos[] = {
38 	{
39 		.fourcc = DRM_FORMAT_RGB565,
40 		.v4l2 = V4L2_PIX_FMT_RGB565,
41 		.bpp = 16,
42 		.planes = 1,
43 		.hsub = 1,
44 		.pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
45 		.edf = PnDDCR4_EDF_NONE,
46 	}, {
47 		.fourcc = DRM_FORMAT_ARGB1555,
48 		.v4l2 = V4L2_PIX_FMT_ARGB555,
49 		.bpp = 16,
50 		.planes = 1,
51 		.hsub = 1,
52 		.pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
53 		.edf = PnDDCR4_EDF_NONE,
54 	}, {
55 		.fourcc = DRM_FORMAT_XRGB1555,
56 		.v4l2 = V4L2_PIX_FMT_XRGB555,
57 		.bpp = 16,
58 		.planes = 1,
59 		.pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
60 		.edf = PnDDCR4_EDF_NONE,
61 	}, {
62 		.fourcc = DRM_FORMAT_XRGB8888,
63 		.v4l2 = V4L2_PIX_FMT_XBGR32,
64 		.bpp = 32,
65 		.planes = 1,
66 		.hsub = 1,
67 		.pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
68 		.edf = PnDDCR4_EDF_RGB888,
69 	}, {
70 		.fourcc = DRM_FORMAT_ARGB8888,
71 		.v4l2 = V4L2_PIX_FMT_ABGR32,
72 		.bpp = 32,
73 		.planes = 1,
74 		.hsub = 1,
75 		.pnmr = PnMR_SPIM_ALP | PnMR_DDDF_16BPP,
76 		.edf = PnDDCR4_EDF_ARGB8888,
77 	}, {
78 		.fourcc = DRM_FORMAT_UYVY,
79 		.v4l2 = V4L2_PIX_FMT_UYVY,
80 		.bpp = 16,
81 		.planes = 1,
82 		.hsub = 2,
83 		.pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
84 		.edf = PnDDCR4_EDF_NONE,
85 	}, {
86 		.fourcc = DRM_FORMAT_YUYV,
87 		.v4l2 = V4L2_PIX_FMT_YUYV,
88 		.bpp = 16,
89 		.planes = 1,
90 		.hsub = 2,
91 		.pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
92 		.edf = PnDDCR4_EDF_NONE,
93 	}, {
94 		.fourcc = DRM_FORMAT_NV12,
95 		.v4l2 = V4L2_PIX_FMT_NV12M,
96 		.bpp = 12,
97 		.planes = 2,
98 		.hsub = 2,
99 		.pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
100 		.edf = PnDDCR4_EDF_NONE,
101 	}, {
102 		.fourcc = DRM_FORMAT_NV21,
103 		.v4l2 = V4L2_PIX_FMT_NV21M,
104 		.bpp = 12,
105 		.planes = 2,
106 		.hsub = 2,
107 		.pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
108 		.edf = PnDDCR4_EDF_NONE,
109 	}, {
110 		.fourcc = DRM_FORMAT_NV16,
111 		.v4l2 = V4L2_PIX_FMT_NV16M,
112 		.bpp = 16,
113 		.planes = 2,
114 		.hsub = 2,
115 		.pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
116 		.edf = PnDDCR4_EDF_NONE,
117 	},
118 	/*
119 	 * The following formats are not supported on Gen2 and thus have no
120 	 * associated .pnmr or .edf settings.
121 	 */
122 	{
123 		.fourcc = DRM_FORMAT_RGB332,
124 		.v4l2 = V4L2_PIX_FMT_RGB332,
125 		.bpp = 8,
126 		.planes = 1,
127 		.hsub = 1,
128 	}, {
129 		.fourcc = DRM_FORMAT_ARGB4444,
130 		.v4l2 = V4L2_PIX_FMT_ARGB444,
131 		.bpp = 16,
132 		.planes = 1,
133 		.hsub = 1,
134 	}, {
135 		.fourcc = DRM_FORMAT_XRGB4444,
136 		.v4l2 = V4L2_PIX_FMT_XRGB444,
137 		.bpp = 16,
138 		.planes = 1,
139 		.hsub = 1,
140 	}, {
141 		.fourcc = DRM_FORMAT_RGBA4444,
142 		.v4l2 = V4L2_PIX_FMT_RGBA444,
143 		.bpp = 16,
144 		.planes = 1,
145 		.hsub = 1,
146 	}, {
147 		.fourcc = DRM_FORMAT_RGBX4444,
148 		.v4l2 = V4L2_PIX_FMT_RGBX444,
149 		.bpp = 16,
150 		.planes = 1,
151 		.hsub = 1,
152 	}, {
153 		.fourcc = DRM_FORMAT_ABGR4444,
154 		.v4l2 = V4L2_PIX_FMT_ABGR444,
155 		.bpp = 16,
156 		.planes = 1,
157 		.hsub = 1,
158 	}, {
159 		.fourcc = DRM_FORMAT_XBGR4444,
160 		.v4l2 = V4L2_PIX_FMT_XBGR444,
161 		.bpp = 16,
162 		.planes = 1,
163 		.hsub = 1,
164 	}, {
165 		.fourcc = DRM_FORMAT_BGRA4444,
166 		.v4l2 = V4L2_PIX_FMT_BGRA444,
167 		.bpp = 16,
168 		.planes = 1,
169 		.hsub = 1,
170 	}, {
171 		.fourcc = DRM_FORMAT_BGRX4444,
172 		.v4l2 = V4L2_PIX_FMT_BGRX444,
173 		.bpp = 16,
174 		.planes = 1,
175 		.hsub = 1,
176 	}, {
177 		.fourcc = DRM_FORMAT_RGBA5551,
178 		.v4l2 = V4L2_PIX_FMT_RGBA555,
179 		.bpp = 16,
180 		.planes = 1,
181 		.hsub = 1,
182 	}, {
183 		.fourcc = DRM_FORMAT_RGBX5551,
184 		.v4l2 = V4L2_PIX_FMT_RGBX555,
185 		.bpp = 16,
186 		.planes = 1,
187 		.hsub = 1,
188 	}, {
189 		.fourcc = DRM_FORMAT_ABGR1555,
190 		.v4l2 = V4L2_PIX_FMT_ABGR555,
191 		.bpp = 16,
192 		.planes = 1,
193 		.hsub = 1,
194 	}, {
195 		.fourcc = DRM_FORMAT_XBGR1555,
196 		.v4l2 = V4L2_PIX_FMT_XBGR555,
197 		.bpp = 16,
198 		.planes = 1,
199 		.hsub = 1,
200 	}, {
201 		.fourcc = DRM_FORMAT_BGRA5551,
202 		.v4l2 = V4L2_PIX_FMT_BGRA555,
203 		.bpp = 16,
204 		.planes = 1,
205 		.hsub = 1,
206 	}, {
207 		.fourcc = DRM_FORMAT_BGRX5551,
208 		.v4l2 = V4L2_PIX_FMT_BGRX555,
209 		.bpp = 16,
210 		.planes = 1,
211 		.hsub = 1,
212 	}, {
213 		.fourcc = DRM_FORMAT_BGR888,
214 		.v4l2 = V4L2_PIX_FMT_RGB24,
215 		.bpp = 24,
216 		.planes = 1,
217 		.hsub = 1,
218 	}, {
219 		.fourcc = DRM_FORMAT_RGB888,
220 		.v4l2 = V4L2_PIX_FMT_BGR24,
221 		.bpp = 24,
222 		.planes = 1,
223 		.hsub = 1,
224 	}, {
225 		.fourcc = DRM_FORMAT_RGBA8888,
226 		.v4l2 = V4L2_PIX_FMT_BGRA32,
227 		.bpp = 32,
228 		.planes = 1,
229 		.hsub = 1,
230 	}, {
231 		.fourcc = DRM_FORMAT_RGBX8888,
232 		.v4l2 = V4L2_PIX_FMT_BGRX32,
233 		.bpp = 32,
234 		.planes = 1,
235 		.hsub = 1,
236 	}, {
237 		.fourcc = DRM_FORMAT_ABGR8888,
238 		.v4l2 = V4L2_PIX_FMT_RGBA32,
239 		.bpp = 32,
240 		.planes = 1,
241 		.hsub = 1,
242 	}, {
243 		.fourcc = DRM_FORMAT_XBGR8888,
244 		.v4l2 = V4L2_PIX_FMT_RGBX32,
245 		.bpp = 32,
246 		.planes = 1,
247 		.hsub = 1,
248 	}, {
249 		.fourcc = DRM_FORMAT_BGRA8888,
250 		.v4l2 = V4L2_PIX_FMT_ARGB32,
251 		.bpp = 32,
252 		.planes = 1,
253 		.hsub = 1,
254 	}, {
255 		.fourcc = DRM_FORMAT_BGRX8888,
256 		.v4l2 = V4L2_PIX_FMT_XRGB32,
257 		.bpp = 32,
258 		.planes = 1,
259 		.hsub = 1,
260 	}, {
261 		.fourcc = DRM_FORMAT_YVYU,
262 		.v4l2 = V4L2_PIX_FMT_YVYU,
263 		.bpp = 16,
264 		.planes = 1,
265 		.hsub = 2,
266 	}, {
267 		.fourcc = DRM_FORMAT_NV61,
268 		.v4l2 = V4L2_PIX_FMT_NV61M,
269 		.bpp = 16,
270 		.planes = 2,
271 		.hsub = 2,
272 	}, {
273 		.fourcc = DRM_FORMAT_YUV420,
274 		.v4l2 = V4L2_PIX_FMT_YUV420M,
275 		.bpp = 12,
276 		.planes = 3,
277 		.hsub = 2,
278 	}, {
279 		.fourcc = DRM_FORMAT_YVU420,
280 		.v4l2 = V4L2_PIX_FMT_YVU420M,
281 		.bpp = 12,
282 		.planes = 3,
283 		.hsub = 2,
284 	}, {
285 		.fourcc = DRM_FORMAT_YUV422,
286 		.v4l2 = V4L2_PIX_FMT_YUV422M,
287 		.bpp = 16,
288 		.planes = 3,
289 		.hsub = 2,
290 	}, {
291 		.fourcc = DRM_FORMAT_YVU422,
292 		.v4l2 = V4L2_PIX_FMT_YVU422M,
293 		.bpp = 16,
294 		.planes = 3,
295 		.hsub = 2,
296 	}, {
297 		.fourcc = DRM_FORMAT_YUV444,
298 		.v4l2 = V4L2_PIX_FMT_YUV444M,
299 		.bpp = 24,
300 		.planes = 3,
301 		.hsub = 1,
302 	}, {
303 		.fourcc = DRM_FORMAT_YVU444,
304 		.v4l2 = V4L2_PIX_FMT_YVU444M,
305 		.bpp = 24,
306 		.planes = 3,
307 		.hsub = 1,
308 	},
309 };
310 
rcar_du_format_info(u32 fourcc)311 const struct rcar_du_format_info *rcar_du_format_info(u32 fourcc)
312 {
313 	unsigned int i;
314 
315 	for (i = 0; i < ARRAY_SIZE(rcar_du_format_infos); ++i) {
316 		if (rcar_du_format_infos[i].fourcc == fourcc)
317 			return &rcar_du_format_infos[i];
318 	}
319 
320 	return NULL;
321 }
322 
323 /* -----------------------------------------------------------------------------
324  * Frame buffer
325  */
326 
rcar_du_dumb_create(struct drm_file * file,struct drm_device * dev,struct drm_mode_create_dumb * args)327 int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
328 			struct drm_mode_create_dumb *args)
329 {
330 	struct rcar_du_device *rcdu = dev->dev_private;
331 	unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
332 	unsigned int align;
333 
334 	/*
335 	 * The R8A7779 DU requires a 16 pixels pitch alignment as documented,
336 	 * but the R8A7790 DU seems to require a 128 bytes pitch alignment.
337 	 */
338 	if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
339 		align = 128;
340 	else
341 		align = 16 * args->bpp / 8;
342 
343 	args->pitch = roundup(min_pitch, align);
344 
345 	return drm_gem_cma_dumb_create_internal(file, dev, args);
346 }
347 
348 static struct drm_framebuffer *
rcar_du_fb_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd)349 rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
350 		  const struct drm_mode_fb_cmd2 *mode_cmd)
351 {
352 	struct rcar_du_device *rcdu = dev->dev_private;
353 	const struct rcar_du_format_info *format;
354 	unsigned int chroma_pitch;
355 	unsigned int max_pitch;
356 	unsigned int align;
357 	unsigned int i;
358 
359 	format = rcar_du_format_info(mode_cmd->pixel_format);
360 	if (format == NULL) {
361 		dev_dbg(dev->dev, "unsupported pixel format %08x\n",
362 			mode_cmd->pixel_format);
363 		return ERR_PTR(-EINVAL);
364 	}
365 
366 	if (rcdu->info->gen < 3) {
367 		/*
368 		 * On Gen2 the DU limits the pitch to 4095 pixels and requires
369 		 * buffers to be aligned to a 16 pixels boundary (or 128 bytes
370 		 * on some platforms).
371 		 */
372 		unsigned int bpp = format->planes == 1 ? format->bpp / 8 : 1;
373 
374 		max_pitch = 4095 * bpp;
375 
376 		if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
377 			align = 128;
378 		else
379 			align = 16 * bpp;
380 	} else {
381 		/*
382 		 * On Gen3 the memory interface is handled by the VSP that
383 		 * limits the pitch to 65535 bytes and has no alignment
384 		 * constraint.
385 		 */
386 		max_pitch = 65535;
387 		align = 1;
388 	}
389 
390 	if (mode_cmd->pitches[0] & (align - 1) ||
391 	    mode_cmd->pitches[0] > max_pitch) {
392 		dev_dbg(dev->dev, "invalid pitch value %u\n",
393 			mode_cmd->pitches[0]);
394 		return ERR_PTR(-EINVAL);
395 	}
396 
397 	/*
398 	 * Calculate the chroma plane(s) pitch using the horizontal subsampling
399 	 * factor. For semi-planar formats, the U and V planes are combined, the
400 	 * pitch must thus be doubled.
401 	 */
402 	chroma_pitch = mode_cmd->pitches[0] / format->hsub;
403 	if (format->planes == 2)
404 		chroma_pitch *= 2;
405 
406 	for (i = 1; i < format->planes; ++i) {
407 		if (mode_cmd->pitches[i] != chroma_pitch) {
408 			dev_dbg(dev->dev,
409 				"luma and chroma pitches are not compatible\n");
410 			return ERR_PTR(-EINVAL);
411 		}
412 	}
413 
414 	return drm_gem_fb_create(dev, file_priv, mode_cmd);
415 }
416 
417 /* -----------------------------------------------------------------------------
418  * Atomic Check and Update
419  */
420 
rcar_du_atomic_check(struct drm_device * dev,struct drm_atomic_state * state)421 static int rcar_du_atomic_check(struct drm_device *dev,
422 				struct drm_atomic_state *state)
423 {
424 	struct rcar_du_device *rcdu = dev->dev_private;
425 	int ret;
426 
427 	ret = drm_atomic_helper_check(dev, state);
428 	if (ret)
429 		return ret;
430 
431 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
432 		return 0;
433 
434 	return rcar_du_atomic_check_planes(dev, state);
435 }
436 
rcar_du_atomic_commit_tail(struct drm_atomic_state * old_state)437 static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
438 {
439 	struct drm_device *dev = old_state->dev;
440 	struct rcar_du_device *rcdu = dev->dev_private;
441 	struct drm_crtc_state *crtc_state;
442 	struct drm_crtc *crtc;
443 	unsigned int i;
444 
445 	/*
446 	 * Store RGB routing to DPAD0 and DPAD1, the hardware will be configured
447 	 * when starting the CRTCs.
448 	 */
449 	rcdu->dpad1_source = -1;
450 
451 	for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) {
452 		struct rcar_du_crtc_state *rcrtc_state =
453 			to_rcar_crtc_state(crtc_state);
454 		struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
455 
456 		if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD0))
457 			rcdu->dpad0_source = rcrtc->index;
458 
459 		if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
460 			rcdu->dpad1_source = rcrtc->index;
461 	}
462 
463 	/* Apply the atomic update. */
464 	drm_atomic_helper_commit_modeset_disables(dev, old_state);
465 	drm_atomic_helper_commit_planes(dev, old_state,
466 					DRM_PLANE_COMMIT_ACTIVE_ONLY);
467 	drm_atomic_helper_commit_modeset_enables(dev, old_state);
468 
469 	drm_atomic_helper_commit_hw_done(old_state);
470 	drm_atomic_helper_wait_for_flip_done(dev, old_state);
471 
472 	drm_atomic_helper_cleanup_planes(dev, old_state);
473 }
474 
475 /* -----------------------------------------------------------------------------
476  * Initialization
477  */
478 
479 static const struct drm_mode_config_helper_funcs rcar_du_mode_config_helper = {
480 	.atomic_commit_tail = rcar_du_atomic_commit_tail,
481 };
482 
483 static const struct drm_mode_config_funcs rcar_du_mode_config_funcs = {
484 	.fb_create = rcar_du_fb_create,
485 	.atomic_check = rcar_du_atomic_check,
486 	.atomic_commit = drm_atomic_helper_commit,
487 };
488 
rcar_du_encoders_init_one(struct rcar_du_device * rcdu,enum rcar_du_output output,struct of_endpoint * ep)489 static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
490 				     enum rcar_du_output output,
491 				     struct of_endpoint *ep)
492 {
493 	struct device_node *entity;
494 	int ret;
495 
496 	/* Locate the connected entity and initialize the encoder. */
497 	entity = of_graph_get_remote_port_parent(ep->local_node);
498 	if (!entity) {
499 		dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
500 			ep->local_node);
501 		return -ENODEV;
502 	}
503 
504 	if (!of_device_is_available(entity)) {
505 		dev_dbg(rcdu->dev,
506 			"connected entity %pOF is disabled, skipping\n",
507 			entity);
508 		of_node_put(entity);
509 		return -ENODEV;
510 	}
511 
512 	ret = rcar_du_encoder_init(rcdu, output, entity);
513 	if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK)
514 		dev_warn(rcdu->dev,
515 			 "failed to initialize encoder %pOF on output %u (%d), skipping\n",
516 			 entity, output, ret);
517 
518 	of_node_put(entity);
519 
520 	return ret;
521 }
522 
rcar_du_encoders_init(struct rcar_du_device * rcdu)523 static int rcar_du_encoders_init(struct rcar_du_device *rcdu)
524 {
525 	struct device_node *np = rcdu->dev->of_node;
526 	struct device_node *ep_node;
527 	unsigned int num_encoders = 0;
528 
529 	/*
530 	 * Iterate over the endpoints and create one encoder for each output
531 	 * pipeline.
532 	 */
533 	for_each_endpoint_of_node(np, ep_node) {
534 		enum rcar_du_output output;
535 		struct of_endpoint ep;
536 		unsigned int i;
537 		int ret;
538 
539 		ret = of_graph_parse_endpoint(ep_node, &ep);
540 		if (ret < 0) {
541 			of_node_put(ep_node);
542 			return ret;
543 		}
544 
545 		/* Find the output route corresponding to the port number. */
546 		for (i = 0; i < RCAR_DU_OUTPUT_MAX; ++i) {
547 			if (rcdu->info->routes[i].possible_crtcs &&
548 			    rcdu->info->routes[i].port == ep.port) {
549 				output = i;
550 				break;
551 			}
552 		}
553 
554 		if (i == RCAR_DU_OUTPUT_MAX) {
555 			dev_warn(rcdu->dev,
556 				 "port %u references unexisting output, skipping\n",
557 				 ep.port);
558 			continue;
559 		}
560 
561 		/* Process the output pipeline. */
562 		ret = rcar_du_encoders_init_one(rcdu, output, &ep);
563 		if (ret < 0) {
564 			if (ret == -EPROBE_DEFER) {
565 				of_node_put(ep_node);
566 				return ret;
567 			}
568 
569 			continue;
570 		}
571 
572 		num_encoders++;
573 	}
574 
575 	return num_encoders;
576 }
577 
rcar_du_properties_init(struct rcar_du_device * rcdu)578 static int rcar_du_properties_init(struct rcar_du_device *rcdu)
579 {
580 	/*
581 	 * The color key is expressed as an RGB888 triplet stored in a 32-bit
582 	 * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0)
583 	 * or enable source color keying (1).
584 	 */
585 	rcdu->props.colorkey =
586 		drm_property_create_range(rcdu->ddev, 0, "colorkey",
587 					  0, 0x01ffffff);
588 	if (rcdu->props.colorkey == NULL)
589 		return -ENOMEM;
590 
591 	return 0;
592 }
593 
rcar_du_vsps_init(struct rcar_du_device * rcdu)594 static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
595 {
596 	const struct device_node *np = rcdu->dev->of_node;
597 	const char *vsps_prop_name = "renesas,vsps";
598 	struct of_phandle_args args;
599 	struct {
600 		struct device_node *np;
601 		unsigned int crtcs_mask;
602 	} vsps[RCAR_DU_MAX_VSPS] = { { NULL, }, };
603 	unsigned int vsps_count = 0;
604 	unsigned int cells;
605 	unsigned int i;
606 	int ret;
607 
608 	/*
609 	 * First parse the DT vsps property to populate the list of VSPs. Each
610 	 * entry contains a pointer to the VSP DT node and a bitmask of the
611 	 * connected DU CRTCs.
612 	 */
613 	ret = of_property_count_u32_elems(np, vsps_prop_name);
614 	if (ret < 0) {
615 		/* Backward compatibility with old DTBs. */
616 		vsps_prop_name = "vsps";
617 		ret = of_property_count_u32_elems(np, vsps_prop_name);
618 	}
619 	cells = ret / rcdu->num_crtcs - 1;
620 	if (cells > 1)
621 		return -EINVAL;
622 
623 	for (i = 0; i < rcdu->num_crtcs; ++i) {
624 		unsigned int j;
625 
626 		ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name,
627 						       cells, i, &args);
628 		if (ret < 0)
629 			goto error;
630 
631 		/*
632 		 * Add the VSP to the list or update the corresponding existing
633 		 * entry if the VSP has already been added.
634 		 */
635 		for (j = 0; j < vsps_count; ++j) {
636 			if (vsps[j].np == args.np)
637 				break;
638 		}
639 
640 		if (j < vsps_count)
641 			of_node_put(args.np);
642 		else
643 			vsps[vsps_count++].np = args.np;
644 
645 		vsps[j].crtcs_mask |= BIT(i);
646 
647 		/*
648 		 * Store the VSP pointer and pipe index in the CRTC. If the
649 		 * second cell of the 'renesas,vsps' specifier isn't present,
650 		 * default to 0 to remain compatible with older DT bindings.
651 		 */
652 		rcdu->crtcs[i].vsp = &rcdu->vsps[j];
653 		rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
654 	}
655 
656 	/*
657 	 * Then initialize all the VSPs from the node pointers and CRTCs bitmask
658 	 * computed previously.
659 	 */
660 	for (i = 0; i < vsps_count; ++i) {
661 		struct rcar_du_vsp *vsp = &rcdu->vsps[i];
662 
663 		vsp->index = i;
664 		vsp->dev = rcdu;
665 
666 		ret = rcar_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);
667 		if (ret < 0)
668 			goto error;
669 	}
670 
671 	return 0;
672 
673 error:
674 	for (i = 0; i < ARRAY_SIZE(vsps); ++i)
675 		of_node_put(vsps[i].np);
676 
677 	return ret;
678 }
679 
rcar_du_cmm_init(struct rcar_du_device * rcdu)680 static int rcar_du_cmm_init(struct rcar_du_device *rcdu)
681 {
682 	const struct device_node *np = rcdu->dev->of_node;
683 	unsigned int i;
684 	int cells;
685 
686 	cells = of_property_count_u32_elems(np, "renesas,cmms");
687 	if (cells == -EINVAL)
688 		return 0;
689 
690 	if (cells > rcdu->num_crtcs) {
691 		dev_err(rcdu->dev,
692 			"Invalid number of entries in 'renesas,cmms'\n");
693 		return -EINVAL;
694 	}
695 
696 	for (i = 0; i < cells; ++i) {
697 		struct platform_device *pdev;
698 		struct device_link *link;
699 		struct device_node *cmm;
700 		int ret;
701 
702 		cmm = of_parse_phandle(np, "renesas,cmms", i);
703 		if (!cmm) {
704 			dev_err(rcdu->dev,
705 				"Failed to parse 'renesas,cmms' property\n");
706 			return -EINVAL;
707 		}
708 
709 		if (!of_device_is_available(cmm)) {
710 			/* It's fine to have a phandle to a non-enabled CMM. */
711 			of_node_put(cmm);
712 			continue;
713 		}
714 
715 		pdev = of_find_device_by_node(cmm);
716 		if (!pdev) {
717 			dev_err(rcdu->dev, "No device found for CMM%u\n", i);
718 			of_node_put(cmm);
719 			return -EINVAL;
720 		}
721 
722 		of_node_put(cmm);
723 
724 		/*
725 		 * -ENODEV is used to report that the CMM config option is
726 		 * disabled: return 0 and let the DU continue probing.
727 		 */
728 		ret = rcar_cmm_init(pdev);
729 		if (ret)
730 			return ret == -ENODEV ? 0 : ret;
731 
732 		/*
733 		 * Enforce suspend/resume ordering by making the CMM a provider
734 		 * of the DU: CMM is suspended after and resumed before the DU.
735 		 */
736 		link = device_link_add(rcdu->dev, &pdev->dev, DL_FLAG_STATELESS);
737 		if (!link) {
738 			dev_err(rcdu->dev,
739 				"Failed to create device link to CMM%u\n", i);
740 			return -EINVAL;
741 		}
742 
743 		rcdu->cmms[i] = pdev;
744 	}
745 
746 	return 0;
747 }
748 
rcar_du_modeset_init(struct rcar_du_device * rcdu)749 int rcar_du_modeset_init(struct rcar_du_device *rcdu)
750 {
751 	static const unsigned int mmio_offsets[] = {
752 		DU0_REG_OFFSET, DU2_REG_OFFSET
753 	};
754 
755 	struct drm_device *dev = rcdu->ddev;
756 	struct drm_encoder *encoder;
757 	unsigned int dpad0_sources;
758 	unsigned int num_encoders;
759 	unsigned int num_groups;
760 	unsigned int swindex;
761 	unsigned int hwindex;
762 	unsigned int i;
763 	int ret;
764 
765 	ret = drmm_mode_config_init(dev);
766 	if (ret)
767 		return ret;
768 
769 	dev->mode_config.min_width = 0;
770 	dev->mode_config.min_height = 0;
771 	dev->mode_config.normalize_zpos = true;
772 	dev->mode_config.funcs = &rcar_du_mode_config_funcs;
773 	dev->mode_config.helper_private = &rcar_du_mode_config_helper;
774 
775 	if (rcdu->info->gen < 3) {
776 		dev->mode_config.max_width = 4095;
777 		dev->mode_config.max_height = 2047;
778 	} else {
779 		/*
780 		 * The Gen3 DU uses the VSP1 for memory access, and is limited
781 		 * to frame sizes of 8190x8190.
782 		 */
783 		dev->mode_config.max_width = 8190;
784 		dev->mode_config.max_height = 8190;
785 	}
786 
787 	rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
788 
789 	ret = rcar_du_properties_init(rcdu);
790 	if (ret < 0)
791 		return ret;
792 
793 	/*
794 	 * Initialize vertical blanking interrupts handling. Start with vblank
795 	 * disabled for all CRTCs.
796 	 */
797 	ret = drm_vblank_init(dev, rcdu->num_crtcs);
798 	if (ret < 0)
799 		return ret;
800 
801 	/* Initialize the groups. */
802 	num_groups = DIV_ROUND_UP(rcdu->num_crtcs, 2);
803 
804 	for (i = 0; i < num_groups; ++i) {
805 		struct rcar_du_group *rgrp = &rcdu->groups[i];
806 
807 		mutex_init(&rgrp->lock);
808 
809 		rgrp->dev = rcdu;
810 		rgrp->mmio_offset = mmio_offsets[i];
811 		rgrp->index = i;
812 		/* Extract the channel mask for this group only. */
813 		rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i))
814 				   & GENMASK(1, 0);
815 		rgrp->num_crtcs = hweight8(rgrp->channels_mask);
816 
817 		/*
818 		 * If we have more than one CRTCs in this group pre-associate
819 		 * the low-order planes with CRTC 0 and the high-order planes
820 		 * with CRTC 1 to minimize flicker occurring when the
821 		 * association is changed.
822 		 */
823 		rgrp->dptsr_planes = rgrp->num_crtcs > 1
824 				   ? (rcdu->info->gen >= 3 ? 0x04 : 0xf0)
825 				   : 0;
826 
827 		if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
828 			ret = rcar_du_planes_init(rgrp);
829 			if (ret < 0)
830 				return ret;
831 		}
832 	}
833 
834 	/* Initialize the compositors. */
835 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
836 		ret = rcar_du_vsps_init(rcdu);
837 		if (ret < 0)
838 			return ret;
839 	}
840 
841 	/* Initialize the Color Management Modules. */
842 	ret = rcar_du_cmm_init(rcdu);
843 	if (ret)
844 		return ret;
845 
846 	/* Create the CRTCs. */
847 	for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) {
848 		struct rcar_du_group *rgrp;
849 
850 		/* Skip unpopulated DU channels. */
851 		if (!(rcdu->info->channels_mask & BIT(hwindex)))
852 			continue;
853 
854 		rgrp = &rcdu->groups[hwindex / 2];
855 
856 		ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
857 		if (ret < 0)
858 			return ret;
859 	}
860 
861 	/* Initialize the encoders. */
862 	ret = rcar_du_encoders_init(rcdu);
863 	if (ret < 0)
864 		return ret;
865 
866 	if (ret == 0) {
867 		dev_err(rcdu->dev, "error: no encoder could be initialized\n");
868 		return -EINVAL;
869 	}
870 
871 	num_encoders = ret;
872 
873 	/*
874 	 * Set the possible CRTCs and possible clones. There's always at least
875 	 * one way for all encoders to clone each other, set all bits in the
876 	 * possible clones field.
877 	 */
878 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
879 		struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
880 		const struct rcar_du_output_routing *route =
881 			&rcdu->info->routes[renc->output];
882 
883 		encoder->possible_crtcs = route->possible_crtcs;
884 		encoder->possible_clones = (1 << num_encoders) - 1;
885 	}
886 
887 	/* Create the writeback connectors. */
888 	if (rcdu->info->gen >= 3) {
889 		for (i = 0; i < rcdu->num_crtcs; ++i) {
890 			struct rcar_du_crtc *rcrtc = &rcdu->crtcs[i];
891 
892 			ret = rcar_du_writeback_init(rcdu, rcrtc);
893 			if (ret < 0)
894 				return ret;
895 		}
896 	}
897 
898 	/*
899 	 * Initialize the default DPAD0 source to the index of the first DU
900 	 * channel that can be connected to DPAD0. The exact value doesn't
901 	 * matter as it should be overwritten by mode setting for the RGB
902 	 * output, but it is nonetheless required to ensure a valid initial
903 	 * hardware configuration on Gen3 where DU0 can't always be connected to
904 	 * DPAD0.
905 	 */
906 	dpad0_sources = rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
907 	rcdu->dpad0_source = ffs(dpad0_sources) - 1;
908 
909 	drm_mode_config_reset(dev);
910 
911 	drm_kms_helper_poll_init(dev);
912 
913 	return 0;
914 }
915