1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
4 */
5
6 #ifndef _SUN8I_MIXER_H_
7 #define _SUN8I_MIXER_H_
8
9 #include <linux/clk.h>
10 #include <linux/regmap.h>
11 #include <linux/reset.h>
12
13 #include "sunxi_engine.h"
14
15 #define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
16 #define SUN8I_MIXER_COORD(x, y) ((y) << 16 | (x))
17
18 #define SUN8I_MIXER_GLOBAL_CTL 0x0
19 #define SUN8I_MIXER_GLOBAL_STATUS 0x4
20 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8
21 #define SUN8I_MIXER_GLOBAL_SIZE 0xc
22
23 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
24
25 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
26
27 #define DE2_MIXER_UNIT_SIZE 0x6000
28 #define DE3_MIXER_UNIT_SIZE 0x3000
29
30 #define DE2_BLD_BASE 0x1000
31 #define DE2_CH_BASE 0x2000
32 #define DE2_CH_SIZE 0x1000
33
34 #define DE3_BLD_BASE 0x0800
35 #define DE3_CH_BASE 0x1000
36 #define DE3_CH_SIZE 0x0800
37
38 #define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0)
39 #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x))
40 #define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x))
41 #define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x))
42 #define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80)
43 #define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84)
44 #define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88)
45 #define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c)
46 #define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x))
47 #define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0)
48 #define SUN8I_MIXER_BLEND_CK_CFG(base) ((base) + 0xb4)
49 #define SUN8I_MIXER_BLEND_CK_MAX(base, x) ((base) + 0xc0 + 0x04 * (x))
50 #define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x))
51 #define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc)
52 #define SUN50I_MIXER_BLEND_CSC_CTL(base) ((base) + 0x100)
53 #define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x, y) \
54 ((base) + 0x110 + (layer) * 0x30 + (x) * 0x10 + 4 * (y))
55 #define SUN50I_MIXER_BLEND_CSC_CONST(base, layer, i) \
56 ((base) + 0x110 + (layer) * 0x30 + (i) * 0x10 + 0x0c)
57
58 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8)
59 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)
60 #define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe)
61
62 /* colors are always in AARRGGBB format */
63 #define SUN8I_MIXER_BLEND_COLOR_BLACK 0xff000000
64 /* The following numbers are some still unknown magic numbers */
65 #define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301
66
67 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2))
68 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2)
69
70 #define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
71
72 #define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch) BIT(ch)
73 #define SUN50I_MIXER_BLEND_CSC_CONST_VAL(d, c) (((d) << 16) | ((c) & 0xffff))
74
75 #define SUN8I_MIXER_FBFMT_ARGB8888 0
76 #define SUN8I_MIXER_FBFMT_ABGR8888 1
77 #define SUN8I_MIXER_FBFMT_RGBA8888 2
78 #define SUN8I_MIXER_FBFMT_BGRA8888 3
79 #define SUN8I_MIXER_FBFMT_XRGB8888 4
80 #define SUN8I_MIXER_FBFMT_XBGR8888 5
81 #define SUN8I_MIXER_FBFMT_RGBX8888 6
82 #define SUN8I_MIXER_FBFMT_BGRX8888 7
83 #define SUN8I_MIXER_FBFMT_RGB888 8
84 #define SUN8I_MIXER_FBFMT_BGR888 9
85 #define SUN8I_MIXER_FBFMT_RGB565 10
86 #define SUN8I_MIXER_FBFMT_BGR565 11
87 #define SUN8I_MIXER_FBFMT_ARGB4444 12
88 #define SUN8I_MIXER_FBFMT_ABGR4444 13
89 #define SUN8I_MIXER_FBFMT_RGBA4444 14
90 #define SUN8I_MIXER_FBFMT_BGRA4444 15
91 #define SUN8I_MIXER_FBFMT_ARGB1555 16
92 #define SUN8I_MIXER_FBFMT_ABGR1555 17
93 #define SUN8I_MIXER_FBFMT_RGBA5551 18
94 #define SUN8I_MIXER_FBFMT_BGRA5551 19
95 #define SUN8I_MIXER_FBFMT_ARGB2101010 20
96 #define SUN8I_MIXER_FBFMT_ABGR2101010 21
97 #define SUN8I_MIXER_FBFMT_RGBA1010102 22
98 #define SUN8I_MIXER_FBFMT_BGRA1010102 23
99
100 #define SUN8I_MIXER_FBFMT_YUYV 0
101 #define SUN8I_MIXER_FBFMT_UYVY 1
102 #define SUN8I_MIXER_FBFMT_YVYU 2
103 #define SUN8I_MIXER_FBFMT_VYUY 3
104 #define SUN8I_MIXER_FBFMT_NV16 4
105 #define SUN8I_MIXER_FBFMT_NV61 5
106 #define SUN8I_MIXER_FBFMT_YUV422 6
107 /* format 7 doesn't exist */
108 #define SUN8I_MIXER_FBFMT_NV12 8
109 #define SUN8I_MIXER_FBFMT_NV21 9
110 #define SUN8I_MIXER_FBFMT_YUV420 10
111 /* format 11 doesn't exist */
112 /* format 12 is semi-planar YUV411 UVUV */
113 /* format 13 is semi-planar YUV411 VUVU */
114 #define SUN8I_MIXER_FBFMT_YUV411 14
115 /* format 15 doesn't exist */
116 /* format 16 is P010 YVU */
117 #define SUN8I_MIXER_FBFMT_P010_YUV 17
118 /* format 18 is P210 YVU */
119 #define SUN8I_MIXER_FBFMT_P210_YUV 19
120 /* format 20 is packed YVU444 10-bit */
121 /* format 21 is packed YUV444 10-bit */
122
123 /*
124 * Sub-engines listed bellow are unused for now. The EN registers are here only
125 * to be used to disable these sub-engines.
126 */
127 #define SUN8I_MIXER_FCE_EN 0xa0000
128 #define SUN8I_MIXER_BWS_EN 0xa2000
129 #define SUN8I_MIXER_LTI_EN 0xa4000
130 #define SUN8I_MIXER_PEAK_EN 0xa6000
131 #define SUN8I_MIXER_ASE_EN 0xa8000
132 #define SUN8I_MIXER_FCC_EN 0xaa000
133 #define SUN8I_MIXER_DCSC_EN 0xb0000
134
135 #define SUN50I_MIXER_FCE_EN 0x70000
136 #define SUN50I_MIXER_PEAK_EN 0x70800
137 #define SUN50I_MIXER_LCTI_EN 0x71000
138 #define SUN50I_MIXER_BLS_EN 0x71800
139 #define SUN50I_MIXER_FCC_EN 0x72000
140 #define SUN50I_MIXER_DNS_EN 0x80000
141 #define SUN50I_MIXER_DRC_EN 0xa0000
142 #define SUN50I_MIXER_FMT_EN 0xa8000
143 #define SUN50I_MIXER_CDC0_EN 0xd0000
144 #define SUN50I_MIXER_CDC1_EN 0xd8000
145
146 /**
147 * struct sun8i_mixer_cfg - mixer HW configuration
148 * @vi_num: number of VI channels
149 * @ui_num: number of UI channels
150 * @scaler_mask: bitmask which tells which channel supports scaling
151 * First, scaler supports for VI channels is defined and after that, scaler
152 * support for UI channels. For example, if mixer has 2 VI channels without
153 * scaler and 2 UI channels with scaler, bitmask would be 0xC.
154 * @ccsc: select set of CCSC base addresses
155 * Set value to 0 if this is first mixer or second mixer with VEP support.
156 * Set value to 1 if this is second mixer without VEP support. Other values
157 * are invalid.
158 * @mod_rate: module clock rate that needs to be set in order to have
159 * a functional block.
160 * @is_de3: true, if this is next gen display engine 3.0, false otherwise.
161 * @scaline_yuv: size of a scanline for VI scaler for YUV formats.
162 */
163 struct sun8i_mixer_cfg {
164 int vi_num;
165 int ui_num;
166 int scaler_mask;
167 int ccsc;
168 unsigned long mod_rate;
169 unsigned int is_de3 : 1;
170 unsigned int scanline_yuv;
171 };
172
173 struct sun8i_mixer {
174 struct sunxi_engine engine;
175
176 const struct sun8i_mixer_cfg *cfg;
177
178 struct reset_control *reset;
179
180 struct clk *bus_clk;
181 struct clk *mod_clk;
182 };
183
184 static inline struct sun8i_mixer *
engine_to_sun8i_mixer(struct sunxi_engine * engine)185 engine_to_sun8i_mixer(struct sunxi_engine *engine)
186 {
187 return container_of(engine, struct sun8i_mixer, engine);
188 }
189
190 static inline u32
sun8i_blender_base(struct sun8i_mixer * mixer)191 sun8i_blender_base(struct sun8i_mixer *mixer)
192 {
193 return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
194 }
195
196 static inline u32
sun8i_channel_base(struct sun8i_mixer * mixer,int channel)197 sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
198 {
199 if (mixer->cfg->is_de3)
200 return DE3_CH_BASE + channel * DE3_CH_SIZE;
201 else
202 return DE2_CH_BASE + channel * DE2_CH_SIZE;
203 }
204
205 int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format);
206 #endif /* _SUN8I_MIXER_H_ */
207