1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9 /**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_probe_helper.h>
37 #include <drm/drm_simple_kms_helper.h>
38 #include <linux/clk.h>
39 #include <linux/component.h>
40 #include <linux/i2c.h>
41 #include <linux/of_address.h>
42 #include <linux/of_gpio.h>
43 #include <linux/of_platform.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/rational.h>
46 #include <linux/reset.h>
47 #include <sound/dmaengine_pcm.h>
48 #include <sound/pcm_drm_eld.h>
49 #include <sound/pcm_params.h>
50 #include <sound/soc.h>
51 #include "media/cec.h"
52 #include "vc4_drv.h"
53 #include "vc4_hdmi.h"
54 #include "vc4_hdmi_regs.h"
55 #include "vc4_regs.h"
56
57 #define VC5_HDMI_HORZA_HFP_SHIFT 16
58 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
59 #define VC5_HDMI_HORZA_VPOS BIT(15)
60 #define VC5_HDMI_HORZA_HPOS BIT(14)
61 #define VC5_HDMI_HORZA_HAP_SHIFT 0
62 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
63
64 #define VC5_HDMI_HORZB_HBP_SHIFT 16
65 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
66 #define VC5_HDMI_HORZB_HSP_SHIFT 0
67 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
68
69 #define VC5_HDMI_VERTA_VSP_SHIFT 24
70 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
71 #define VC5_HDMI_VERTA_VFP_SHIFT 16
72 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
73 #define VC5_HDMI_VERTA_VAL_SHIFT 0
74 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
75
76 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
77 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
78
79 # define VC4_HD_M_SW_RST BIT(2)
80 # define VC4_HD_M_ENABLE BIT(0)
81
82 #define HSM_MIN_CLOCK_FREQ 120000000
83 #define CEC_CLOCK_FREQ 40000
84 #define VC4_HSM_MID_CLOCK 149985000
85
vc4_hdmi_debugfs_regs(struct seq_file * m,void * unused)86 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
87 {
88 struct drm_info_node *node = (struct drm_info_node *)m->private;
89 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
90 struct drm_printer p = drm_seq_file_printer(m);
91
92 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
93 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
94
95 return 0;
96 }
97
vc4_hdmi_reset(struct vc4_hdmi * vc4_hdmi)98 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
99 {
100 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
101 udelay(1);
102 HDMI_WRITE(HDMI_M_CTL, 0);
103
104 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
105
106 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
107 VC4_HDMI_SW_RESET_HDMI |
108 VC4_HDMI_SW_RESET_FORMAT_DETECT);
109
110 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
111 }
112
vc5_hdmi_reset(struct vc4_hdmi * vc4_hdmi)113 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
114 {
115 reset_control_reset(vc4_hdmi->reset);
116
117 HDMI_WRITE(HDMI_DVP_CTL, 0);
118
119 HDMI_WRITE(HDMI_CLOCK_STOP,
120 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
121 }
122
123 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)124 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
125 {
126 u16 clk_cnt;
127 u32 value;
128
129 value = HDMI_READ(HDMI_CEC_CNTRL_1);
130 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
131
132 /*
133 * Set the clock divider: the hsm_clock rate and this divider
134 * setting will give a 40 kHz CEC clock.
135 */
136 clk_cnt = clk_get_rate(vc4_hdmi->hsm_clock) / CEC_CLOCK_FREQ;
137 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
138 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
139 }
140 #else
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)141 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
142 #endif
143
144 static enum drm_connector_status
vc4_hdmi_connector_detect(struct drm_connector * connector,bool force)145 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
146 {
147 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
148 bool connected = false;
149
150 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
151
152 if (vc4_hdmi->hpd_gpio) {
153 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
154 vc4_hdmi->hpd_active_low)
155 connected = true;
156 } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
157 connected = true;
158 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
159 connected = true;
160 }
161
162 if (connected) {
163 if (connector->status != connector_status_connected) {
164 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
165
166 if (edid) {
167 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
168 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
169 kfree(edid);
170 }
171 }
172
173 pm_runtime_put(&vc4_hdmi->pdev->dev);
174 return connector_status_connected;
175 }
176
177 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
178 pm_runtime_put(&vc4_hdmi->pdev->dev);
179 return connector_status_disconnected;
180 }
181
vc4_hdmi_connector_destroy(struct drm_connector * connector)182 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
183 {
184 drm_connector_unregister(connector);
185 drm_connector_cleanup(connector);
186 }
187
vc4_hdmi_connector_get_modes(struct drm_connector * connector)188 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
189 {
190 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
191 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
192 int ret = 0;
193 struct edid *edid;
194
195 edid = drm_get_edid(connector, vc4_hdmi->ddc);
196 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
197 if (!edid)
198 return -ENODEV;
199
200 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
201
202 drm_connector_update_edid_property(connector, edid);
203 ret = drm_add_edid_modes(connector, edid);
204 kfree(edid);
205
206 return ret;
207 }
208
vc4_hdmi_connector_reset(struct drm_connector * connector)209 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
210 {
211 drm_atomic_helper_connector_reset(connector);
212 drm_atomic_helper_connector_tv_reset(connector);
213 }
214
215 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
216 .detect = vc4_hdmi_connector_detect,
217 .fill_modes = drm_helper_probe_single_connector_modes,
218 .destroy = vc4_hdmi_connector_destroy,
219 .reset = vc4_hdmi_connector_reset,
220 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
221 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
222 };
223
224 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
225 .get_modes = vc4_hdmi_connector_get_modes,
226 };
227
vc4_hdmi_connector_init(struct drm_device * dev,struct vc4_hdmi * vc4_hdmi)228 static int vc4_hdmi_connector_init(struct drm_device *dev,
229 struct vc4_hdmi *vc4_hdmi)
230 {
231 struct drm_connector *connector = &vc4_hdmi->connector;
232 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
233 int ret;
234
235 drm_connector_init_with_ddc(dev, connector,
236 &vc4_hdmi_connector_funcs,
237 DRM_MODE_CONNECTOR_HDMIA,
238 vc4_hdmi->ddc);
239 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
240
241 /* Create and attach TV margin props to this connector. */
242 ret = drm_mode_create_tv_margin_properties(dev);
243 if (ret)
244 return ret;
245
246 drm_connector_attach_tv_margin_properties(connector);
247
248 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
249 DRM_CONNECTOR_POLL_DISCONNECT);
250
251 connector->interlace_allowed = 1;
252 connector->doublescan_allowed = 0;
253
254 drm_connector_attach_encoder(connector, encoder);
255
256 return 0;
257 }
258
vc4_hdmi_stop_packet(struct drm_encoder * encoder,enum hdmi_infoframe_type type)259 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
260 enum hdmi_infoframe_type type)
261 {
262 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
263 u32 packet_id = type - 0x80;
264
265 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
266 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
267
268 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
269 BIT(packet_id)), 100);
270 }
271
vc4_hdmi_write_infoframe(struct drm_encoder * encoder,union hdmi_infoframe * frame)272 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
273 union hdmi_infoframe *frame)
274 {
275 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
276 u32 packet_id = frame->any.type - 0x80;
277 const struct vc4_hdmi_register *ram_packet_start =
278 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
279 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
280 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
281 ram_packet_start->reg);
282 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
283 ssize_t len, i;
284 int ret;
285
286 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
287 VC4_HDMI_RAM_PACKET_ENABLE),
288 "Packet RAM has to be on to store the packet.");
289
290 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
291 if (len < 0)
292 return;
293
294 ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
295 if (ret) {
296 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
297 return;
298 }
299
300 for (i = 0; i < len; i += 7) {
301 writel(buffer[i + 0] << 0 |
302 buffer[i + 1] << 8 |
303 buffer[i + 2] << 16,
304 base + packet_reg);
305 packet_reg += 4;
306
307 writel(buffer[i + 3] << 0 |
308 buffer[i + 4] << 8 |
309 buffer[i + 5] << 16 |
310 buffer[i + 6] << 24,
311 base + packet_reg);
312 packet_reg += 4;
313 }
314
315 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
316 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
317 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
318 BIT(packet_id)), 100);
319 if (ret)
320 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
321 }
322
vc4_hdmi_set_avi_infoframe(struct drm_encoder * encoder)323 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
324 {
325 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
326 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
327 struct drm_connector *connector = &vc4_hdmi->connector;
328 struct drm_connector_state *cstate = connector->state;
329 struct drm_crtc *crtc = encoder->crtc;
330 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
331 union hdmi_infoframe frame;
332 int ret;
333
334 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
335 connector, mode);
336 if (ret < 0) {
337 DRM_ERROR("couldn't fill AVI infoframe\n");
338 return;
339 }
340
341 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
342 connector, mode,
343 vc4_encoder->limited_rgb_range ?
344 HDMI_QUANTIZATION_RANGE_LIMITED :
345 HDMI_QUANTIZATION_RANGE_FULL);
346
347 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
348
349 vc4_hdmi_write_infoframe(encoder, &frame);
350 }
351
vc4_hdmi_set_spd_infoframe(struct drm_encoder * encoder)352 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
353 {
354 union hdmi_infoframe frame;
355 int ret;
356
357 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
358 if (ret < 0) {
359 DRM_ERROR("couldn't fill SPD infoframe\n");
360 return;
361 }
362
363 frame.spd.sdi = HDMI_SPD_SDI_PC;
364
365 vc4_hdmi_write_infoframe(encoder, &frame);
366 }
367
vc4_hdmi_set_audio_infoframe(struct drm_encoder * encoder)368 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
369 {
370 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
371 union hdmi_infoframe frame;
372 int ret;
373
374 ret = hdmi_audio_infoframe_init(&frame.audio);
375
376 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
377 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
378 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
379 frame.audio.channels = vc4_hdmi->audio.channels;
380
381 vc4_hdmi_write_infoframe(encoder, &frame);
382 }
383
vc4_hdmi_set_infoframes(struct drm_encoder * encoder)384 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
385 {
386 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
387
388 vc4_hdmi_set_avi_infoframe(encoder);
389 vc4_hdmi_set_spd_infoframe(encoder);
390 /*
391 * If audio was streaming, then we need to reenabled the audio
392 * infoframe here during encoder_enable.
393 */
394 if (vc4_hdmi->audio.streaming)
395 vc4_hdmi_set_audio_infoframe(encoder);
396 }
397
vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder * encoder)398 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder)
399 {
400 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
401
402 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
403
404 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
405 VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
406
407 HDMI_WRITE(HDMI_VID_CTL,
408 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
409 }
410
vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder * encoder)411 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder)
412 {
413 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
414 int ret;
415
416 if (vc4_hdmi->variant->phy_disable)
417 vc4_hdmi->variant->phy_disable(vc4_hdmi);
418
419 HDMI_WRITE(HDMI_VID_CTL,
420 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
421
422 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
423 clk_disable_unprepare(vc4_hdmi->pixel_clock);
424
425 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
426 if (ret < 0)
427 DRM_ERROR("Failed to release power domain: %d\n", ret);
428 }
429
vc4_hdmi_encoder_disable(struct drm_encoder * encoder)430 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
431 {
432 }
433
vc4_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,bool enable)434 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
435 {
436 u32 csc_ctl;
437
438 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
439 VC4_HD_CSC_CTL_ORDER);
440
441 if (enable) {
442 /* CEA VICs other than #1 requre limited range RGB
443 * output unless overridden by an AVI infoframe.
444 * Apply a colorspace conversion to squash 0-255 down
445 * to 16-235. The matrix here is:
446 *
447 * [ 0 0 0.8594 16]
448 * [ 0 0.8594 0 16]
449 * [ 0.8594 0 0 16]
450 * [ 0 0 0 1]
451 */
452 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
453 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
454 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
455 VC4_HD_CSC_CTL_MODE);
456
457 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
458 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
459 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
460 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
461 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
462 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
463 }
464
465 /* The RGB order applies even when CSC is disabled. */
466 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
467 }
468
vc5_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,bool enable)469 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
470 {
471 u32 csc_ctl;
472
473 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
474
475 if (enable) {
476 /* CEA VICs other than #1 requre limited range RGB
477 * output unless overridden by an AVI infoframe.
478 * Apply a colorspace conversion to squash 0-255 down
479 * to 16-235. The matrix here is:
480 *
481 * [ 0.8594 0 0 16]
482 * [ 0 0.8594 0 16]
483 * [ 0 0 0.8594 16]
484 * [ 0 0 0 1]
485 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
486 */
487 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
488 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
489 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
490 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
491 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
492 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
493 } else {
494 /* Still use the matrix for full range, but make it unity.
495 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
496 */
497 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
498 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
499 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
500 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
501 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
502 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
503 }
504
505 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
506 }
507
vc4_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_display_mode * mode)508 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
509 struct drm_display_mode *mode)
510 {
511 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
512 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
513 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
514 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
515 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
516 VC4_HDMI_VERTA_VSP) |
517 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
518 VC4_HDMI_VERTA_VFP) |
519 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
520 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
521 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
522 VC4_HDMI_VERTB_VBP));
523 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
524 VC4_SET_FIELD(mode->crtc_vtotal -
525 mode->crtc_vsync_end -
526 interlaced,
527 VC4_HDMI_VERTB_VBP));
528
529 HDMI_WRITE(HDMI_HORZA,
530 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
531 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
532 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
533 VC4_HDMI_HORZA_HAP));
534
535 HDMI_WRITE(HDMI_HORZB,
536 VC4_SET_FIELD((mode->htotal -
537 mode->hsync_end) * pixel_rep,
538 VC4_HDMI_HORZB_HBP) |
539 VC4_SET_FIELD((mode->hsync_end -
540 mode->hsync_start) * pixel_rep,
541 VC4_HDMI_HORZB_HSP) |
542 VC4_SET_FIELD((mode->hsync_start -
543 mode->hdisplay) * pixel_rep,
544 VC4_HDMI_HORZB_HFP));
545
546 HDMI_WRITE(HDMI_VERTA0, verta);
547 HDMI_WRITE(HDMI_VERTA1, verta);
548
549 HDMI_WRITE(HDMI_VERTB0, vertb_even);
550 HDMI_WRITE(HDMI_VERTB1, vertb);
551 }
vc5_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_display_mode * mode)552 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
553 struct drm_display_mode *mode)
554 {
555 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
556 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
557 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
558 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
559 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
560 VC5_HDMI_VERTA_VSP) |
561 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
562 VC5_HDMI_VERTA_VFP) |
563 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
564 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
565 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
566 VC4_HDMI_VERTB_VBP));
567 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
568 VC4_SET_FIELD(mode->crtc_vtotal -
569 mode->crtc_vsync_end -
570 interlaced,
571 VC4_HDMI_VERTB_VBP));
572
573 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
574 HDMI_WRITE(HDMI_HORZA,
575 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
576 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
577 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
578 VC5_HDMI_HORZA_HAP) |
579 VC4_SET_FIELD((mode->hsync_start -
580 mode->hdisplay) * pixel_rep,
581 VC5_HDMI_HORZA_HFP));
582
583 HDMI_WRITE(HDMI_HORZB,
584 VC4_SET_FIELD((mode->htotal -
585 mode->hsync_end) * pixel_rep,
586 VC5_HDMI_HORZB_HBP) |
587 VC4_SET_FIELD((mode->hsync_end -
588 mode->hsync_start) * pixel_rep,
589 VC5_HDMI_HORZB_HSP));
590
591 HDMI_WRITE(HDMI_VERTA0, verta);
592 HDMI_WRITE(HDMI_VERTA1, verta);
593
594 HDMI_WRITE(HDMI_VERTB0, vertb_even);
595 HDMI_WRITE(HDMI_VERTB1, vertb);
596
597 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
598 }
599
vc4_hdmi_recenter_fifo(struct vc4_hdmi * vc4_hdmi)600 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
601 {
602 u32 drift;
603 int ret;
604
605 drift = HDMI_READ(HDMI_FIFO_CTL);
606 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
607
608 HDMI_WRITE(HDMI_FIFO_CTL,
609 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
610 HDMI_WRITE(HDMI_FIFO_CTL,
611 drift | VC4_HDMI_FIFO_CTL_RECENTER);
612 usleep_range(1000, 1100);
613 HDMI_WRITE(HDMI_FIFO_CTL,
614 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
615 HDMI_WRITE(HDMI_FIFO_CTL,
616 drift | VC4_HDMI_FIFO_CTL_RECENTER);
617
618 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
619 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
620 WARN_ONCE(ret, "Timeout waiting for "
621 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
622 }
623
vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder * encoder)624 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder)
625 {
626 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
627 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
628 unsigned long pixel_rate, hsm_rate;
629 int ret;
630
631 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
632 if (ret < 0) {
633 DRM_ERROR("Failed to retain power domain: %d\n", ret);
634 return;
635 }
636
637 pixel_rate = mode->clock * 1000 * ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1);
638 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
639 if (ret) {
640 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
641 return;
642 }
643
644 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
645 if (ret) {
646 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
647 return;
648 }
649
650 /*
651 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
652 * be faster than pixel clock, infinitesimally faster, tested in
653 * simulation. Otherwise, exact value is unimportant for HDMI
654 * operation." This conflicts with bcm2835's vc4 documentation, which
655 * states HSM's clock has to be at least 108% of the pixel clock.
656 *
657 * Real life tests reveal that vc4's firmware statement holds up, and
658 * users are able to use pixel clocks closer to HSM's, namely for
659 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
660 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
661 * 162MHz.
662 *
663 * Additionally, the AXI clock needs to be at least 25% of
664 * pixel clock, but HSM ends up being the limiting factor.
665 */
666 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
667 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
668 if (ret) {
669 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
670 return;
671 }
672
673 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
674
675 /*
676 * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
677 * at 300MHz.
678 */
679 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
680 (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
681 if (ret) {
682 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
683 clk_disable_unprepare(vc4_hdmi->pixel_clock);
684 return;
685 }
686
687 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
688 if (ret) {
689 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
690 clk_disable_unprepare(vc4_hdmi->pixel_clock);
691 return;
692 }
693
694 if (vc4_hdmi->variant->phy_init)
695 vc4_hdmi->variant->phy_init(vc4_hdmi, mode);
696
697 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
698 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
699 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
700 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
701
702 if (vc4_hdmi->variant->set_timings)
703 vc4_hdmi->variant->set_timings(vc4_hdmi, mode);
704 }
705
vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder * encoder)706 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder)
707 {
708 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
709 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
710 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
711
712 if (vc4_encoder->hdmi_monitor &&
713 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
714 if (vc4_hdmi->variant->csc_setup)
715 vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
716
717 vc4_encoder->limited_rgb_range = true;
718 } else {
719 if (vc4_hdmi->variant->csc_setup)
720 vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
721
722 vc4_encoder->limited_rgb_range = false;
723 }
724
725 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
726 }
727
vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder * encoder)728 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder)
729 {
730 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
731 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
732 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
733 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
734 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
735 int ret;
736
737 HDMI_WRITE(HDMI_VID_CTL,
738 VC4_HD_VID_CTL_ENABLE |
739 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
740 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
741 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
742 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
743
744 HDMI_WRITE(HDMI_VID_CTL,
745 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
746
747 if (vc4_encoder->hdmi_monitor) {
748 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
749 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
750 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
751
752 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
753 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
754 WARN_ONCE(ret, "Timeout waiting for "
755 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
756 } else {
757 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
758 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
759 ~(VC4_HDMI_RAM_PACKET_ENABLE));
760 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
761 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
762 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
763
764 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
765 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
766 WARN_ONCE(ret, "Timeout waiting for "
767 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
768 }
769
770 if (vc4_encoder->hdmi_monitor) {
771 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
772 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
773 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
774 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
775 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
776
777 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
778 VC4_HDMI_RAM_PACKET_ENABLE);
779
780 vc4_hdmi_set_infoframes(encoder);
781 }
782
783 vc4_hdmi_recenter_fifo(vc4_hdmi);
784 }
785
vc4_hdmi_encoder_enable(struct drm_encoder * encoder)786 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
787 {
788 }
789
790 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
791 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
792
vc4_hdmi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)793 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
794 struct drm_crtc_state *crtc_state,
795 struct drm_connector_state *conn_state)
796 {
797 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
798 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
799 unsigned long long pixel_rate = mode->clock * 1000;
800 unsigned long long tmds_rate;
801
802 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
803 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
804 (mode->hsync_end % 2) || (mode->htotal % 2)))
805 return -EINVAL;
806
807 /*
808 * The 1440p@60 pixel rate is in the same range than the first
809 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
810 * bandwidth). Slightly lower the frequency to bring it out of
811 * the WiFi range.
812 */
813 tmds_rate = pixel_rate * 10;
814 if (vc4_hdmi->disable_wifi_frequencies &&
815 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
816 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
817 mode->clock = 238560;
818 pixel_rate = mode->clock * 1000;
819 }
820
821 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
822 pixel_rate = pixel_rate * 2;
823
824 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
825 return -EINVAL;
826
827 return 0;
828 }
829
830 static enum drm_mode_status
vc4_hdmi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)831 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
832 const struct drm_display_mode *mode)
833 {
834 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
835
836 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
837 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
838 (mode->hsync_end % 2) || (mode->htotal % 2)))
839 return MODE_H_ILLEGAL;
840
841 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
842 return MODE_CLOCK_HIGH;
843
844 return MODE_OK;
845 }
846
847 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
848 .atomic_check = vc4_hdmi_encoder_atomic_check,
849 .mode_valid = vc4_hdmi_encoder_mode_valid,
850 .disable = vc4_hdmi_encoder_disable,
851 .enable = vc4_hdmi_encoder_enable,
852 };
853
vc4_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)854 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
855 {
856 int i;
857 u32 channel_map = 0;
858
859 for (i = 0; i < 8; i++) {
860 if (channel_mask & BIT(i))
861 channel_map |= i << (3 * i);
862 }
863 return channel_map;
864 }
865
vc5_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)866 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
867 {
868 int i;
869 u32 channel_map = 0;
870
871 for (i = 0; i < 8; i++) {
872 if (channel_mask & BIT(i))
873 channel_map |= i << (4 * i);
874 }
875 return channel_map;
876 }
877
878 /* HDMI audio codec callbacks */
vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi * vc4_hdmi)879 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
880 {
881 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
882 unsigned long n, m;
883
884 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
885 VC4_HD_MAI_SMP_N_MASK >>
886 VC4_HD_MAI_SMP_N_SHIFT,
887 (VC4_HD_MAI_SMP_M_MASK >>
888 VC4_HD_MAI_SMP_M_SHIFT) + 1,
889 &n, &m);
890
891 HDMI_WRITE(HDMI_MAI_SMP,
892 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
893 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
894 }
895
vc4_hdmi_set_n_cts(struct vc4_hdmi * vc4_hdmi)896 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
897 {
898 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
899 struct drm_crtc *crtc = encoder->crtc;
900 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
901 u32 samplerate = vc4_hdmi->audio.samplerate;
902 u32 n, cts;
903 u64 tmp;
904
905 n = 128 * samplerate / 1000;
906 tmp = (u64)(mode->clock * 1000) * n;
907 do_div(tmp, 128 * samplerate);
908 cts = tmp;
909
910 HDMI_WRITE(HDMI_CRP_CFG,
911 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
912 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
913
914 /*
915 * We could get slightly more accurate clocks in some cases by
916 * providing a CTS_1 value. The two CTS values are alternated
917 * between based on the period fields
918 */
919 HDMI_WRITE(HDMI_CTS_0, cts);
920 HDMI_WRITE(HDMI_CTS_1, cts);
921 }
922
dai_to_hdmi(struct snd_soc_dai * dai)923 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
924 {
925 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
926
927 return snd_soc_card_get_drvdata(card);
928 }
929
vc4_hdmi_audio_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)930 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
931 struct snd_soc_dai *dai)
932 {
933 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
934 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
935 struct drm_connector *connector = &vc4_hdmi->connector;
936 int ret;
937
938 if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
939 return -EINVAL;
940
941 vc4_hdmi->audio.substream = substream;
942
943 /*
944 * If the HDMI encoder hasn't probed, or the encoder is
945 * currently in DVI mode, treat the codec dai as missing.
946 */
947 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
948 VC4_HDMI_RAM_PACKET_ENABLE))
949 return -ENODEV;
950
951 ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld);
952 if (ret)
953 return ret;
954
955 return 0;
956 }
957
vc4_hdmi_audio_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)958 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
959 {
960 return 0;
961 }
962
vc4_hdmi_audio_reset(struct vc4_hdmi * vc4_hdmi)963 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
964 {
965 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
966 struct device *dev = &vc4_hdmi->pdev->dev;
967 int ret;
968
969 vc4_hdmi->audio.streaming = false;
970 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
971 if (ret)
972 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
973
974 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
975 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
976 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
977 }
978
vc4_hdmi_audio_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)979 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
980 struct snd_soc_dai *dai)
981 {
982 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
983
984 if (substream != vc4_hdmi->audio.substream)
985 return;
986
987 vc4_hdmi_audio_reset(vc4_hdmi);
988
989 vc4_hdmi->audio.substream = NULL;
990 }
991
992 /* HDMI audio codec callbacks */
vc4_hdmi_audio_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)993 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
994 struct snd_pcm_hw_params *params,
995 struct snd_soc_dai *dai)
996 {
997 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
998 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
999 struct device *dev = &vc4_hdmi->pdev->dev;
1000 u32 audio_packet_config, channel_mask;
1001 u32 channel_map;
1002
1003 if (substream != vc4_hdmi->audio.substream)
1004 return -EINVAL;
1005
1006 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1007 params_rate(params), params_width(params),
1008 params_channels(params));
1009
1010 vc4_hdmi->audio.channels = params_channels(params);
1011 vc4_hdmi->audio.samplerate = params_rate(params);
1012
1013 HDMI_WRITE(HDMI_MAI_CTL,
1014 VC4_HD_MAI_CTL_RESET |
1015 VC4_HD_MAI_CTL_FLUSH |
1016 VC4_HD_MAI_CTL_DLATE |
1017 VC4_HD_MAI_CTL_ERRORE |
1018 VC4_HD_MAI_CTL_ERRORF);
1019
1020 vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
1021
1022 /* The B frame identifier should match the value used by alsa-lib (8) */
1023 audio_packet_config =
1024 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1025 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1026 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1027
1028 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
1029 audio_packet_config |= VC4_SET_FIELD(channel_mask,
1030 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1031
1032 /* Set the MAI threshold. This logic mimics the firmware's. */
1033 if (vc4_hdmi->audio.samplerate > 96000) {
1034 HDMI_WRITE(HDMI_MAI_THR,
1035 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
1036 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1037 } else if (vc4_hdmi->audio.samplerate > 48000) {
1038 HDMI_WRITE(HDMI_MAI_THR,
1039 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
1040 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1041 } else {
1042 HDMI_WRITE(HDMI_MAI_THR,
1043 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1044 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1045 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1046 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1047 }
1048
1049 HDMI_WRITE(HDMI_MAI_CONFIG,
1050 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1051 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1052
1053 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1054 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1055 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1056 vc4_hdmi_set_n_cts(vc4_hdmi);
1057
1058 vc4_hdmi_set_audio_infoframe(encoder);
1059
1060 return 0;
1061 }
1062
vc4_hdmi_audio_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1063 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
1064 struct snd_soc_dai *dai)
1065 {
1066 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1067
1068 switch (cmd) {
1069 case SNDRV_PCM_TRIGGER_START:
1070 vc4_hdmi->audio.streaming = true;
1071
1072 if (vc4_hdmi->variant->phy_rng_enable)
1073 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1074
1075 HDMI_WRITE(HDMI_MAI_CTL,
1076 VC4_SET_FIELD(vc4_hdmi->audio.channels,
1077 VC4_HD_MAI_CTL_CHNUM) |
1078 VC4_HD_MAI_CTL_WHOLSMP |
1079 VC4_HD_MAI_CTL_CHALIGN |
1080 VC4_HD_MAI_CTL_ENABLE);
1081 break;
1082 case SNDRV_PCM_TRIGGER_STOP:
1083 HDMI_WRITE(HDMI_MAI_CTL,
1084 VC4_HD_MAI_CTL_DLATE |
1085 VC4_HD_MAI_CTL_ERRORE |
1086 VC4_HD_MAI_CTL_ERRORF);
1087
1088 if (vc4_hdmi->variant->phy_rng_disable)
1089 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1090
1091 vc4_hdmi->audio.streaming = false;
1092
1093 break;
1094 default:
1095 break;
1096 }
1097
1098 return 0;
1099 }
1100
1101 static inline struct vc4_hdmi *
snd_component_to_hdmi(struct snd_soc_component * component)1102 snd_component_to_hdmi(struct snd_soc_component *component)
1103 {
1104 struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
1105
1106 return snd_soc_card_get_drvdata(card);
1107 }
1108
vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1109 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
1110 struct snd_ctl_elem_info *uinfo)
1111 {
1112 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1113 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1114 struct drm_connector *connector = &vc4_hdmi->connector;
1115
1116 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1117 uinfo->count = sizeof(connector->eld);
1118
1119 return 0;
1120 }
1121
vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1122 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
1123 struct snd_ctl_elem_value *ucontrol)
1124 {
1125 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1126 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1127 struct drm_connector *connector = &vc4_hdmi->connector;
1128
1129 memcpy(ucontrol->value.bytes.data, connector->eld,
1130 sizeof(connector->eld));
1131
1132 return 0;
1133 }
1134
1135 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
1136 {
1137 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1138 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1139 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1140 .name = "ELD",
1141 .info = vc4_hdmi_audio_eld_ctl_info,
1142 .get = vc4_hdmi_audio_eld_ctl_get,
1143 },
1144 };
1145
1146 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1147 SND_SOC_DAPM_OUTPUT("TX"),
1148 };
1149
1150 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1151 { "TX", NULL, "Playback" },
1152 };
1153
1154 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1155 .name = "vc4-hdmi-codec-dai-component",
1156 .controls = vc4_hdmi_audio_controls,
1157 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
1158 .dapm_widgets = vc4_hdmi_audio_widgets,
1159 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1160 .dapm_routes = vc4_hdmi_audio_routes,
1161 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
1162 .idle_bias_on = 1,
1163 .use_pmdown_time = 1,
1164 .endianness = 1,
1165 .non_legacy_dai_naming = 1,
1166 };
1167
1168 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1169 .startup = vc4_hdmi_audio_startup,
1170 .shutdown = vc4_hdmi_audio_shutdown,
1171 .hw_params = vc4_hdmi_audio_hw_params,
1172 .set_fmt = vc4_hdmi_audio_set_fmt,
1173 .trigger = vc4_hdmi_audio_trigger,
1174 };
1175
1176 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1177 .name = "vc4-hdmi-hifi",
1178 .playback = {
1179 .stream_name = "Playback",
1180 .channels_min = 2,
1181 .channels_max = 8,
1182 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1183 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1184 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1185 SNDRV_PCM_RATE_192000,
1186 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1187 },
1188 };
1189
1190 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1191 .name = "vc4-hdmi-cpu-dai-component",
1192 };
1193
vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai * dai)1194 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1195 {
1196 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1197
1198 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1199
1200 return 0;
1201 }
1202
1203 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1204 .name = "vc4-hdmi-cpu-dai",
1205 .probe = vc4_hdmi_audio_cpu_dai_probe,
1206 .playback = {
1207 .stream_name = "Playback",
1208 .channels_min = 1,
1209 .channels_max = 8,
1210 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1211 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1212 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1213 SNDRV_PCM_RATE_192000,
1214 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1215 },
1216 .ops = &vc4_hdmi_audio_dai_ops,
1217 };
1218
1219 static const struct snd_dmaengine_pcm_config pcm_conf = {
1220 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1221 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1222 };
1223
vc4_hdmi_audio_init(struct vc4_hdmi * vc4_hdmi)1224 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1225 {
1226 const struct vc4_hdmi_register *mai_data =
1227 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1228 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1229 struct snd_soc_card *card = &vc4_hdmi->audio.card;
1230 struct device *dev = &vc4_hdmi->pdev->dev;
1231 const __be32 *addr;
1232 int index;
1233 int ret;
1234
1235 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1236 dev_warn(dev,
1237 "'dmas' DT property is missing, no HDMI audio\n");
1238 return 0;
1239 }
1240
1241 if (mai_data->reg != VC4_HD) {
1242 WARN_ONCE(true, "MAI isn't in the HD block\n");
1243 return -EINVAL;
1244 }
1245
1246 /*
1247 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1248 * the bus address specified in the DT, because the physical address
1249 * (the one returned by platform_get_resource()) is not appropriate
1250 * for DMA transfers.
1251 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1252 */
1253 index = of_property_match_string(dev->of_node, "reg-names", "hd");
1254 /* Before BCM2711, we don't have a named register range */
1255 if (index < 0)
1256 index = 1;
1257
1258 addr = of_get_address(dev->of_node, index, NULL, NULL);
1259
1260 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1261 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1262 vc4_hdmi->audio.dma_data.maxburst = 2;
1263
1264 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1265 if (ret) {
1266 dev_err(dev, "Could not register PCM component: %d\n", ret);
1267 return ret;
1268 }
1269
1270 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1271 &vc4_hdmi_audio_cpu_dai_drv, 1);
1272 if (ret) {
1273 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1274 return ret;
1275 }
1276
1277 /* register component and codec dai */
1278 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1279 &vc4_hdmi_audio_codec_dai_drv, 1);
1280 if (ret) {
1281 dev_err(dev, "Could not register component: %d\n", ret);
1282 return ret;
1283 }
1284
1285 dai_link->cpus = &vc4_hdmi->audio.cpu;
1286 dai_link->codecs = &vc4_hdmi->audio.codec;
1287 dai_link->platforms = &vc4_hdmi->audio.platform;
1288
1289 dai_link->num_cpus = 1;
1290 dai_link->num_codecs = 1;
1291 dai_link->num_platforms = 1;
1292
1293 dai_link->name = "MAI";
1294 dai_link->stream_name = "MAI PCM";
1295 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1296 dai_link->cpus->dai_name = dev_name(dev);
1297 dai_link->codecs->name = dev_name(dev);
1298 dai_link->platforms->name = dev_name(dev);
1299
1300 card->dai_link = dai_link;
1301 card->num_links = 1;
1302 card->name = vc4_hdmi->variant->card_name;
1303 card->driver_name = "vc4-hdmi";
1304 card->dev = dev;
1305 card->owner = THIS_MODULE;
1306
1307 /*
1308 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1309 * stores a pointer to the snd card object in dev->driver_data. This
1310 * means we cannot use it for something else. The hdmi back-pointer is
1311 * now stored in card->drvdata and should be retrieved with
1312 * snd_soc_card_get_drvdata() if needed.
1313 */
1314 snd_soc_card_set_drvdata(card, vc4_hdmi);
1315 ret = devm_snd_soc_register_card(dev, card);
1316 if (ret)
1317 dev_err(dev, "Could not register sound card: %d\n", ret);
1318
1319 return ret;
1320
1321 }
1322
1323 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_cec_irq_handler_thread(int irq,void * priv)1324 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1325 {
1326 struct vc4_hdmi *vc4_hdmi = priv;
1327
1328 if (vc4_hdmi->cec_irq_was_rx) {
1329 if (vc4_hdmi->cec_rx_msg.len)
1330 cec_received_msg(vc4_hdmi->cec_adap,
1331 &vc4_hdmi->cec_rx_msg);
1332 } else if (vc4_hdmi->cec_tx_ok) {
1333 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1334 0, 0, 0, 0);
1335 } else {
1336 /*
1337 * This CEC implementation makes 1 retry, so if we
1338 * get a NACK, then that means it made 2 attempts.
1339 */
1340 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1341 0, 2, 0, 0);
1342 }
1343 return IRQ_HANDLED;
1344 }
1345
vc4_cec_read_msg(struct vc4_hdmi * vc4_hdmi,u32 cntrl1)1346 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1347 {
1348 struct drm_device *dev = vc4_hdmi->connector.dev;
1349 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1350 unsigned int i;
1351
1352 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1353 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1354
1355 if (msg->len > 16) {
1356 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1357 return;
1358 }
1359
1360 for (i = 0; i < msg->len; i += 4) {
1361 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1362
1363 msg->msg[i] = val & 0xff;
1364 msg->msg[i + 1] = (val >> 8) & 0xff;
1365 msg->msg[i + 2] = (val >> 16) & 0xff;
1366 msg->msg[i + 3] = (val >> 24) & 0xff;
1367 }
1368 }
1369
vc4_cec_irq_handler(int irq,void * priv)1370 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1371 {
1372 struct vc4_hdmi *vc4_hdmi = priv;
1373 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1374 u32 cntrl1, cntrl5;
1375
1376 if (!(stat & VC4_HDMI_CPU_CEC))
1377 return IRQ_NONE;
1378 vc4_hdmi->cec_rx_msg.len = 0;
1379 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1380 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1381 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1382 if (vc4_hdmi->cec_irq_was_rx) {
1383 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1384 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1385 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1386 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1387 } else {
1388 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1389 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1390 }
1391 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1392 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1393
1394 return IRQ_WAKE_THREAD;
1395 }
1396
vc4_hdmi_cec_adap_enable(struct cec_adapter * adap,bool enable)1397 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1398 {
1399 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1400 /* clock period in microseconds */
1401 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1402 u32 val;
1403 int ret;
1404
1405 if (enable) {
1406 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1407 if (ret)
1408 return ret;
1409
1410 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1411 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1412 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1413 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1414 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1415 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1416
1417 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1418 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1419 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1420 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1421 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1422 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1423 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1424 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1425 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1426 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1427 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1428 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1429 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1430 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1431 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1432 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1433 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1434 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1435 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1436
1437 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1438 } else {
1439 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1440 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1441 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1442
1443 pm_runtime_put(&vc4_hdmi->pdev->dev);
1444 }
1445
1446 return 0;
1447 }
1448
vc4_hdmi_cec_adap_log_addr(struct cec_adapter * adap,u8 log_addr)1449 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1450 {
1451 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1452
1453 HDMI_WRITE(HDMI_CEC_CNTRL_1,
1454 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1455 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1456 return 0;
1457 }
1458
vc4_hdmi_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)1459 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1460 u32 signal_free_time, struct cec_msg *msg)
1461 {
1462 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1463 struct drm_device *dev = vc4_hdmi->connector.dev;
1464 u32 val;
1465 unsigned int i;
1466
1467 if (msg->len > 16) {
1468 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1469 return -ENOMEM;
1470 }
1471
1472 for (i = 0; i < msg->len; i += 4)
1473 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1474 (msg->msg[i]) |
1475 (msg->msg[i + 1] << 8) |
1476 (msg->msg[i + 2] << 16) |
1477 (msg->msg[i + 3] << 24));
1478
1479 val = HDMI_READ(HDMI_CEC_CNTRL_1);
1480 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1481 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1482 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1483 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1484 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1485
1486 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1487 return 0;
1488 }
1489
1490 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1491 .adap_enable = vc4_hdmi_cec_adap_enable,
1492 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1493 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1494 };
1495
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)1496 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1497 {
1498 struct cec_connector_info conn_info;
1499 struct platform_device *pdev = vc4_hdmi->pdev;
1500 u32 value;
1501 int ret;
1502
1503 if (!vc4_hdmi->variant->cec_available)
1504 return 0;
1505
1506 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1507 vc4_hdmi, "vc4",
1508 CEC_CAP_DEFAULTS |
1509 CEC_CAP_CONNECTOR_INFO, 1);
1510 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1511 if (ret < 0)
1512 return ret;
1513
1514 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1515 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1516
1517 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1518
1519 value = HDMI_READ(HDMI_CEC_CNTRL_1);
1520 /* Set the logical address to Unregistered */
1521 value |= VC4_HDMI_CEC_ADDR_MASK;
1522 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1523
1524 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1525
1526 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
1527 vc4_cec_irq_handler,
1528 vc4_cec_irq_handler_thread, 0,
1529 "vc4 hdmi cec", vc4_hdmi);
1530 if (ret)
1531 goto err_delete_cec_adap;
1532
1533 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1534 if (ret < 0)
1535 goto err_delete_cec_adap;
1536
1537 return 0;
1538
1539 err_delete_cec_adap:
1540 cec_delete_adapter(vc4_hdmi->cec_adap);
1541
1542 return ret;
1543 }
1544
vc4_hdmi_cec_exit(struct vc4_hdmi * vc4_hdmi)1545 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1546 {
1547 cec_unregister_adapter(vc4_hdmi->cec_adap);
1548 }
1549 #else
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)1550 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1551 {
1552 return 0;
1553 }
1554
vc4_hdmi_cec_exit(struct vc4_hdmi * vc4_hdmi)1555 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1556
1557 #endif
1558
vc4_hdmi_build_regset(struct vc4_hdmi * vc4_hdmi,struct debugfs_regset32 * regset,enum vc4_hdmi_regs reg)1559 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1560 struct debugfs_regset32 *regset,
1561 enum vc4_hdmi_regs reg)
1562 {
1563 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1564 struct debugfs_reg32 *regs, *new_regs;
1565 unsigned int count = 0;
1566 unsigned int i;
1567
1568 regs = kcalloc(variant->num_registers, sizeof(*regs),
1569 GFP_KERNEL);
1570 if (!regs)
1571 return -ENOMEM;
1572
1573 for (i = 0; i < variant->num_registers; i++) {
1574 const struct vc4_hdmi_register *field = &variant->registers[i];
1575
1576 if (field->reg != reg)
1577 continue;
1578
1579 regs[count].name = field->name;
1580 regs[count].offset = field->offset;
1581 count++;
1582 }
1583
1584 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1585 if (!new_regs)
1586 return -ENOMEM;
1587
1588 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1589 regset->regs = new_regs;
1590 regset->nregs = count;
1591
1592 return 0;
1593 }
1594
vc4_hdmi_init_resources(struct vc4_hdmi * vc4_hdmi)1595 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1596 {
1597 struct platform_device *pdev = vc4_hdmi->pdev;
1598 struct device *dev = &pdev->dev;
1599 int ret;
1600
1601 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1602 if (IS_ERR(vc4_hdmi->hdmicore_regs))
1603 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1604
1605 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1606 if (IS_ERR(vc4_hdmi->hd_regs))
1607 return PTR_ERR(vc4_hdmi->hd_regs);
1608
1609 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1610 if (ret)
1611 return ret;
1612
1613 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1614 if (ret)
1615 return ret;
1616
1617 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1618 if (IS_ERR(vc4_hdmi->pixel_clock)) {
1619 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1620 if (ret != -EPROBE_DEFER)
1621 DRM_ERROR("Failed to get pixel clock\n");
1622 return ret;
1623 }
1624
1625 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1626 if (IS_ERR(vc4_hdmi->hsm_clock)) {
1627 DRM_ERROR("Failed to get HDMI state machine clock\n");
1628 return PTR_ERR(vc4_hdmi->hsm_clock);
1629 }
1630 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
1631
1632 return 0;
1633 }
1634
vc5_hdmi_init_resources(struct vc4_hdmi * vc4_hdmi)1635 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1636 {
1637 struct platform_device *pdev = vc4_hdmi->pdev;
1638 struct device *dev = &pdev->dev;
1639 struct resource *res;
1640
1641 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
1642 if (!res)
1643 return -ENODEV;
1644
1645 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
1646 resource_size(res));
1647 if (!vc4_hdmi->hdmicore_regs)
1648 return -ENOMEM;
1649
1650 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
1651 if (!res)
1652 return -ENODEV;
1653
1654 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
1655 if (!vc4_hdmi->hd_regs)
1656 return -ENOMEM;
1657
1658 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
1659 if (!res)
1660 return -ENODEV;
1661
1662 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
1663 if (!vc4_hdmi->cec_regs)
1664 return -ENOMEM;
1665
1666 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
1667 if (!res)
1668 return -ENODEV;
1669
1670 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
1671 if (!vc4_hdmi->csc_regs)
1672 return -ENOMEM;
1673
1674 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
1675 if (!res)
1676 return -ENODEV;
1677
1678 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
1679 if (!vc4_hdmi->dvp_regs)
1680 return -ENOMEM;
1681
1682 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
1683 if (!res)
1684 return -ENODEV;
1685
1686 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
1687 if (!vc4_hdmi->phy_regs)
1688 return -ENOMEM;
1689
1690 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
1691 if (!res)
1692 return -ENODEV;
1693
1694 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
1695 if (!vc4_hdmi->ram_regs)
1696 return -ENOMEM;
1697
1698 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
1699 if (!res)
1700 return -ENODEV;
1701
1702 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
1703 if (!vc4_hdmi->rm_regs)
1704 return -ENOMEM;
1705
1706 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1707 if (IS_ERR(vc4_hdmi->hsm_clock)) {
1708 DRM_ERROR("Failed to get HDMI state machine clock\n");
1709 return PTR_ERR(vc4_hdmi->hsm_clock);
1710 }
1711
1712 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
1713 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
1714 DRM_ERROR("Failed to get pixel bvb clock\n");
1715 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
1716 }
1717
1718 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
1719 if (IS_ERR(vc4_hdmi->audio_clock)) {
1720 DRM_ERROR("Failed to get audio clock\n");
1721 return PTR_ERR(vc4_hdmi->audio_clock);
1722 }
1723
1724 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
1725 if (IS_ERR(vc4_hdmi->reset)) {
1726 DRM_ERROR("Failed to get HDMI reset line\n");
1727 return PTR_ERR(vc4_hdmi->reset);
1728 }
1729
1730 return 0;
1731 }
1732
1733 #ifdef CONFIG_PM
vc4_hdmi_runtime_suspend(struct device * dev)1734 static int vc4_hdmi_runtime_suspend(struct device *dev)
1735 {
1736 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1737
1738 clk_disable_unprepare(vc4_hdmi->hsm_clock);
1739
1740 return 0;
1741 }
1742
vc4_hdmi_runtime_resume(struct device * dev)1743 static int vc4_hdmi_runtime_resume(struct device *dev)
1744 {
1745 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1746 int ret;
1747
1748 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
1749 if (ret)
1750 return ret;
1751
1752 return 0;
1753 }
1754 #endif
1755
vc4_hdmi_bind(struct device * dev,struct device * master,void * data)1756 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1757 {
1758 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
1759 struct platform_device *pdev = to_platform_device(dev);
1760 struct drm_device *drm = dev_get_drvdata(master);
1761 struct vc4_hdmi *vc4_hdmi;
1762 struct drm_encoder *encoder;
1763 struct device_node *ddc_node;
1764 u32 value;
1765 int ret;
1766
1767 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
1768 if (!vc4_hdmi)
1769 return -ENOMEM;
1770
1771 dev_set_drvdata(dev, vc4_hdmi);
1772 encoder = &vc4_hdmi->encoder.base.base;
1773 vc4_hdmi->encoder.base.type = variant->encoder_type;
1774 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
1775 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
1776 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
1777 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
1778 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
1779 vc4_hdmi->pdev = pdev;
1780 vc4_hdmi->variant = variant;
1781
1782 ret = variant->init_resources(vc4_hdmi);
1783 if (ret)
1784 return ret;
1785
1786 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1787 if (!ddc_node) {
1788 DRM_ERROR("Failed to find ddc node in device tree\n");
1789 return -ENODEV;
1790 }
1791
1792 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1793 of_node_put(ddc_node);
1794 if (!vc4_hdmi->ddc) {
1795 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1796 return -EPROBE_DEFER;
1797 }
1798
1799 /* Only use the GPIO HPD pin if present in the DT, otherwise
1800 * we'll use the HDMI core's register.
1801 */
1802 if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1803 enum of_gpio_flags hpd_gpio_flags;
1804
1805 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1806 "hpd-gpios", 0,
1807 &hpd_gpio_flags);
1808 if (vc4_hdmi->hpd_gpio < 0) {
1809 ret = vc4_hdmi->hpd_gpio;
1810 goto err_put_ddc;
1811 }
1812
1813 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1814 }
1815
1816 vc4_hdmi->disable_wifi_frequencies =
1817 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
1818
1819 /*
1820 * If we boot without any cable connected to the HDMI connector,
1821 * the firmware will skip the HSM initialization and leave it
1822 * with a rate of 0, resulting in a bus lockup when we're
1823 * accessing the registers even if it's enabled.
1824 *
1825 * Let's put a sensible default at runtime_resume so that we
1826 * don't end up in this situation.
1827 */
1828 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
1829 if (ret)
1830 goto err_put_ddc;
1831
1832 if (vc4_hdmi->variant->reset)
1833 vc4_hdmi->variant->reset(vc4_hdmi);
1834
1835 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
1836 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
1837 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
1838 clk_prepare_enable(vc4_hdmi->pixel_clock);
1839 clk_prepare_enable(vc4_hdmi->hsm_clock);
1840 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1841 }
1842
1843 pm_runtime_enable(dev);
1844
1845 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
1846 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
1847
1848 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
1849 if (ret)
1850 goto err_destroy_encoder;
1851
1852 ret = vc4_hdmi_cec_init(vc4_hdmi);
1853 if (ret)
1854 goto err_destroy_conn;
1855
1856 ret = vc4_hdmi_audio_init(vc4_hdmi);
1857 if (ret)
1858 goto err_free_cec;
1859
1860 vc4_debugfs_add_file(drm, variant->debugfs_name,
1861 vc4_hdmi_debugfs_regs,
1862 vc4_hdmi);
1863
1864 return 0;
1865
1866 err_free_cec:
1867 vc4_hdmi_cec_exit(vc4_hdmi);
1868 err_destroy_conn:
1869 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
1870 err_destroy_encoder:
1871 drm_encoder_cleanup(encoder);
1872 pm_runtime_disable(dev);
1873 err_put_ddc:
1874 put_device(&vc4_hdmi->ddc->dev);
1875
1876 return ret;
1877 }
1878
vc4_hdmi_unbind(struct device * dev,struct device * master,void * data)1879 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1880 void *data)
1881 {
1882 struct vc4_hdmi *vc4_hdmi;
1883
1884 /*
1885 * ASoC makes it a bit hard to retrieve a pointer to the
1886 * vc4_hdmi structure. Registering the card will overwrite our
1887 * device drvdata with a pointer to the snd_soc_card structure,
1888 * which can then be used to retrieve whatever drvdata we want
1889 * to associate.
1890 *
1891 * However, that doesn't fly in the case where we wouldn't
1892 * register an ASoC card (because of an old DT that is missing
1893 * the dmas properties for example), then the card isn't
1894 * registered and the device drvdata wouldn't be set.
1895 *
1896 * We can deal with both cases by making sure a snd_soc_card
1897 * pointer and a vc4_hdmi structure are pointing to the same
1898 * memory address, so we can treat them indistinctly without any
1899 * issue.
1900 */
1901 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
1902 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
1903 vc4_hdmi = dev_get_drvdata(dev);
1904
1905 kfree(vc4_hdmi->hdmi_regset.regs);
1906 kfree(vc4_hdmi->hd_regset.regs);
1907
1908 vc4_hdmi_cec_exit(vc4_hdmi);
1909 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
1910 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
1911
1912 pm_runtime_disable(dev);
1913
1914 put_device(&vc4_hdmi->ddc->dev);
1915 }
1916
1917 static const struct component_ops vc4_hdmi_ops = {
1918 .bind = vc4_hdmi_bind,
1919 .unbind = vc4_hdmi_unbind,
1920 };
1921
vc4_hdmi_dev_probe(struct platform_device * pdev)1922 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1923 {
1924 return component_add(&pdev->dev, &vc4_hdmi_ops);
1925 }
1926
vc4_hdmi_dev_remove(struct platform_device * pdev)1927 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1928 {
1929 component_del(&pdev->dev, &vc4_hdmi_ops);
1930 return 0;
1931 }
1932
1933 static const struct vc4_hdmi_variant bcm2835_variant = {
1934 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
1935 .debugfs_name = "hdmi_regs",
1936 .card_name = "vc4-hdmi",
1937 .max_pixel_clock = 162000000,
1938 .cec_available = true,
1939 .registers = vc4_hdmi_fields,
1940 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
1941
1942 .init_resources = vc4_hdmi_init_resources,
1943 .csc_setup = vc4_hdmi_csc_setup,
1944 .reset = vc4_hdmi_reset,
1945 .set_timings = vc4_hdmi_set_timings,
1946 .phy_init = vc4_hdmi_phy_init,
1947 .phy_disable = vc4_hdmi_phy_disable,
1948 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
1949 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
1950 .channel_map = vc4_hdmi_channel_map,
1951 };
1952
1953 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
1954 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
1955 .debugfs_name = "hdmi0_regs",
1956 .card_name = "vc4-hdmi-0",
1957 .max_pixel_clock = 297000000,
1958 .registers = vc5_hdmi_hdmi0_fields,
1959 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
1960 .phy_lane_mapping = {
1961 PHY_LANE_0,
1962 PHY_LANE_1,
1963 PHY_LANE_2,
1964 PHY_LANE_CK,
1965 },
1966 .unsupported_odd_h_timings = true,
1967
1968 .init_resources = vc5_hdmi_init_resources,
1969 .csc_setup = vc5_hdmi_csc_setup,
1970 .reset = vc5_hdmi_reset,
1971 .set_timings = vc5_hdmi_set_timings,
1972 .phy_init = vc5_hdmi_phy_init,
1973 .phy_disable = vc5_hdmi_phy_disable,
1974 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
1975 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
1976 .channel_map = vc5_hdmi_channel_map,
1977 };
1978
1979 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
1980 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
1981 .debugfs_name = "hdmi1_regs",
1982 .card_name = "vc4-hdmi-1",
1983 .max_pixel_clock = 297000000,
1984 .registers = vc5_hdmi_hdmi1_fields,
1985 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
1986 .phy_lane_mapping = {
1987 PHY_LANE_1,
1988 PHY_LANE_0,
1989 PHY_LANE_CK,
1990 PHY_LANE_2,
1991 },
1992 .unsupported_odd_h_timings = true,
1993
1994 .init_resources = vc5_hdmi_init_resources,
1995 .csc_setup = vc5_hdmi_csc_setup,
1996 .reset = vc5_hdmi_reset,
1997 .set_timings = vc5_hdmi_set_timings,
1998 .phy_init = vc5_hdmi_phy_init,
1999 .phy_disable = vc5_hdmi_phy_disable,
2000 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2001 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2002 .channel_map = vc5_hdmi_channel_map,
2003 };
2004
2005 static const struct of_device_id vc4_hdmi_dt_match[] = {
2006 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2007 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2008 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2009 {}
2010 };
2011
2012 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2013 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2014 vc4_hdmi_runtime_resume,
2015 NULL)
2016 };
2017
2018 struct platform_driver vc4_hdmi_driver = {
2019 .probe = vc4_hdmi_dev_probe,
2020 .remove = vc4_hdmi_dev_remove,
2021 .driver = {
2022 .name = "vc4_hdmi",
2023 .of_match_table = vc4_hdmi_dt_match,
2024 .pm = &vc4_hdmi_pm_ops,
2025 },
2026 };
2027