1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Synopsys DesignWare I2C adapter driver.
4 *
5 * Based on the TI DAVINCI I2C adapter driver.
6 *
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
10 */
11 #include <linux/acpi.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/export.h>
18 #include <linux/i2c.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regmap.h>
25 #include <linux/swab.h>
26 #include <linux/types.h>
27
28 #include "i2c-designware-core.h"
29
30 static char *abort_sources[] = {
31 [ABRT_7B_ADDR_NOACK] =
32 "slave address not acknowledged (7bit mode)",
33 [ABRT_10ADDR1_NOACK] =
34 "first address byte not acknowledged (10bit mode)",
35 [ABRT_10ADDR2_NOACK] =
36 "second address byte not acknowledged (10bit mode)",
37 [ABRT_TXDATA_NOACK] =
38 "data not acknowledged",
39 [ABRT_GCALL_NOACK] =
40 "no acknowledgement for a general call",
41 [ABRT_GCALL_READ] =
42 "read after general call",
43 [ABRT_SBYTE_ACKDET] =
44 "start byte acknowledged",
45 [ABRT_SBYTE_NORSTRT] =
46 "trying to send start byte when restart is disabled",
47 [ABRT_10B_RD_NORSTRT] =
48 "trying to read when restart is disabled (10bit mode)",
49 [ABRT_MASTER_DIS] =
50 "trying to use disabled adapter",
51 [ARB_LOST] =
52 "lost arbitration",
53 [ABRT_SLAVE_FLUSH_TXFIFO] =
54 "read command so flush old data in the TX FIFO",
55 [ABRT_SLAVE_ARBLOST] =
56 "slave lost the bus while transmitting data to a remote master",
57 [ABRT_SLAVE_RD_INTX] =
58 "incorrect slave-transmitter mode configuration",
59 };
60
dw_reg_read(void * context,unsigned int reg,unsigned int * val)61 static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
62 {
63 struct dw_i2c_dev *dev = context;
64
65 *val = readl_relaxed(dev->base + reg);
66
67 return 0;
68 }
69
dw_reg_write(void * context,unsigned int reg,unsigned int val)70 static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
71 {
72 struct dw_i2c_dev *dev = context;
73
74 writel_relaxed(val, dev->base + reg);
75
76 return 0;
77 }
78
dw_reg_read_swab(void * context,unsigned int reg,unsigned int * val)79 static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
80 {
81 struct dw_i2c_dev *dev = context;
82
83 *val = swab32(readl_relaxed(dev->base + reg));
84
85 return 0;
86 }
87
dw_reg_write_swab(void * context,unsigned int reg,unsigned int val)88 static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
89 {
90 struct dw_i2c_dev *dev = context;
91
92 writel_relaxed(swab32(val), dev->base + reg);
93
94 return 0;
95 }
96
dw_reg_read_word(void * context,unsigned int reg,unsigned int * val)97 static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
98 {
99 struct dw_i2c_dev *dev = context;
100
101 *val = readw_relaxed(dev->base + reg) |
102 (readw_relaxed(dev->base + reg + 2) << 16);
103
104 return 0;
105 }
106
dw_reg_write_word(void * context,unsigned int reg,unsigned int val)107 static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
108 {
109 struct dw_i2c_dev *dev = context;
110
111 writew_relaxed(val, dev->base + reg);
112 writew_relaxed(val >> 16, dev->base + reg + 2);
113
114 return 0;
115 }
116
117 /**
118 * i2c_dw_init_regmap() - Initialize registers map
119 * @dev: device private data
120 *
121 * Autodetects needed register access mode and creates the regmap with
122 * corresponding read/write callbacks. This must be called before doing any
123 * other register access.
124 */
i2c_dw_init_regmap(struct dw_i2c_dev * dev)125 int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
126 {
127 struct regmap_config map_cfg = {
128 .reg_bits = 32,
129 .val_bits = 32,
130 .reg_stride = 4,
131 .disable_locking = true,
132 .reg_read = dw_reg_read,
133 .reg_write = dw_reg_write,
134 .max_register = DW_IC_COMP_TYPE,
135 };
136 u32 reg;
137 int ret;
138
139 /*
140 * Skip detecting the registers map configuration if the regmap has
141 * already been provided by a higher code.
142 */
143 if (dev->map)
144 return 0;
145
146 ret = i2c_dw_acquire_lock(dev);
147 if (ret)
148 return ret;
149
150 reg = readl(dev->base + DW_IC_COMP_TYPE);
151 i2c_dw_release_lock(dev);
152
153 if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
154 map_cfg.reg_read = dw_reg_read_swab;
155 map_cfg.reg_write = dw_reg_write_swab;
156 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
157 map_cfg.reg_read = dw_reg_read_word;
158 map_cfg.reg_write = dw_reg_write_word;
159 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
160 dev_err(dev->dev,
161 "Unknown Synopsys component type: 0x%08x\n", reg);
162 return -ENODEV;
163 }
164
165 /*
166 * Note we'll check the return value of the regmap IO accessors only
167 * at the probe stage. The rest of the code won't do this because
168 * basically we have MMIO-based regmap so non of the read/write methods
169 * can fail.
170 */
171 dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg);
172 if (IS_ERR(dev->map)) {
173 dev_err(dev->dev, "Failed to init the registers map\n");
174 return PTR_ERR(dev->map);
175 }
176
177 return 0;
178 }
179
180 static const u32 supported_speeds[] = {
181 I2C_MAX_HIGH_SPEED_MODE_FREQ,
182 I2C_MAX_FAST_MODE_PLUS_FREQ,
183 I2C_MAX_FAST_MODE_FREQ,
184 I2C_MAX_STANDARD_MODE_FREQ,
185 };
186
i2c_dw_validate_speed(struct dw_i2c_dev * dev)187 int i2c_dw_validate_speed(struct dw_i2c_dev *dev)
188 {
189 struct i2c_timings *t = &dev->timings;
190 unsigned int i;
191
192 /*
193 * Only standard mode at 100kHz, fast mode at 400kHz,
194 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
195 */
196 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
197 if (t->bus_freq_hz == supported_speeds[i])
198 return 0;
199 }
200
201 dev_err(dev->dev,
202 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
203 t->bus_freq_hz);
204
205 return -EINVAL;
206 }
207 EXPORT_SYMBOL_GPL(i2c_dw_validate_speed);
208
209 #ifdef CONFIG_ACPI
210
211 #include <linux/dmi.h>
212
213 /*
214 * The HCNT/LCNT information coming from ACPI should be the most accurate
215 * for given platform. However, some systems get it wrong. On such systems
216 * we get better results by calculating those based on the input clock.
217 */
218 static const struct dmi_system_id i2c_dw_no_acpi_params[] = {
219 {
220 .ident = "Dell Inspiron 7348",
221 .matches = {
222 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
223 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
224 },
225 },
226 {}
227 };
228
i2c_dw_acpi_params(struct device * device,char method[],u16 * hcnt,u16 * lcnt,u32 * sda_hold)229 static void i2c_dw_acpi_params(struct device *device, char method[],
230 u16 *hcnt, u16 *lcnt, u32 *sda_hold)
231 {
232 struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
233 acpi_handle handle = ACPI_HANDLE(device);
234 union acpi_object *obj;
235
236 if (dmi_check_system(i2c_dw_no_acpi_params))
237 return;
238
239 if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
240 return;
241
242 obj = (union acpi_object *)buf.pointer;
243 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
244 const union acpi_object *objs = obj->package.elements;
245
246 *hcnt = (u16)objs[0].integer.value;
247 *lcnt = (u16)objs[1].integer.value;
248 *sda_hold = (u32)objs[2].integer.value;
249 }
250
251 kfree(buf.pointer);
252 }
253
i2c_dw_acpi_configure(struct device * device)254 int i2c_dw_acpi_configure(struct device *device)
255 {
256 struct dw_i2c_dev *dev = dev_get_drvdata(device);
257 struct i2c_timings *t = &dev->timings;
258 u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
259
260 /*
261 * Try to get SDA hold time and *CNT values from an ACPI method for
262 * selected speed modes.
263 */
264 i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
265 i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
266 i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
267 i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
268
269 switch (t->bus_freq_hz) {
270 case I2C_MAX_STANDARD_MODE_FREQ:
271 dev->sda_hold_time = ss_ht;
272 break;
273 case I2C_MAX_FAST_MODE_PLUS_FREQ:
274 dev->sda_hold_time = fp_ht;
275 break;
276 case I2C_MAX_HIGH_SPEED_MODE_FREQ:
277 dev->sda_hold_time = hs_ht;
278 break;
279 case I2C_MAX_FAST_MODE_FREQ:
280 default:
281 dev->sda_hold_time = fs_ht;
282 break;
283 }
284
285 return 0;
286 }
287 EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure);
288
i2c_dw_acpi_round_bus_speed(struct device * device)289 static u32 i2c_dw_acpi_round_bus_speed(struct device *device)
290 {
291 u32 acpi_speed;
292 int i;
293
294 acpi_speed = i2c_acpi_find_bus_speed(device);
295 /*
296 * Some DSTDs use a non standard speed, round down to the lowest
297 * standard speed.
298 */
299 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
300 if (acpi_speed >= supported_speeds[i])
301 return supported_speeds[i];
302 }
303
304 return 0;
305 }
306
307 #else /* CONFIG_ACPI */
308
i2c_dw_acpi_round_bus_speed(struct device * device)309 static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; }
310
311 #endif /* CONFIG_ACPI */
312
i2c_dw_adjust_bus_speed(struct dw_i2c_dev * dev)313 void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev)
314 {
315 u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);
316 struct i2c_timings *t = &dev->timings;
317
318 /*
319 * Find bus speed from the "clock-frequency" device property, ACPI
320 * or by using fast mode if neither is set.
321 */
322 if (acpi_speed && t->bus_freq_hz)
323 t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
324 else if (acpi_speed || t->bus_freq_hz)
325 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
326 else
327 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
328 }
329 EXPORT_SYMBOL_GPL(i2c_dw_adjust_bus_speed);
330
i2c_dw_scl_hcnt(u32 ic_clk,u32 tSYMBOL,u32 tf,int cond,int offset)331 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
332 {
333 /*
334 * DesignWare I2C core doesn't seem to have solid strategy to meet
335 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
336 * will result in violation of the tHD;STA spec.
337 */
338 if (cond)
339 /*
340 * Conditional expression:
341 *
342 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
343 *
344 * This is based on the DW manuals, and represents an ideal
345 * configuration. The resulting I2C bus speed will be
346 * faster than any of the others.
347 *
348 * If your hardware is free from tHD;STA issue, try this one.
349 */
350 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
351 else
352 /*
353 * Conditional expression:
354 *
355 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
356 *
357 * This is just experimental rule; the tHD;STA period turned
358 * out to be proportinal to (_HCNT + 3). With this setting,
359 * we could meet both tHIGH and tHD;STA timing specs.
360 *
361 * If unsure, you'd better to take this alternative.
362 *
363 * The reason why we need to take into account "tf" here,
364 * is the same as described in i2c_dw_scl_lcnt().
365 */
366 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
367 - 3 + offset;
368 }
369
i2c_dw_scl_lcnt(u32 ic_clk,u32 tLOW,u32 tf,int offset)370 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
371 {
372 /*
373 * Conditional expression:
374 *
375 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
376 *
377 * DW I2C core starts counting the SCL CNTs for the LOW period
378 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
379 * In order to meet the tLOW timing spec, we need to take into
380 * account the fall time of SCL signal (tf). Default tf value
381 * should be 0.3 us, for safety.
382 */
383 return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
384 }
385
i2c_dw_set_sda_hold(struct dw_i2c_dev * dev)386 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
387 {
388 u32 reg;
389 int ret;
390
391 ret = i2c_dw_acquire_lock(dev);
392 if (ret)
393 return ret;
394
395 /* Configure SDA Hold Time if required */
396 ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®);
397 if (ret)
398 goto err_release_lock;
399
400 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
401 if (!dev->sda_hold_time) {
402 /* Keep previous hold time setting if no one set it */
403 ret = regmap_read(dev->map, DW_IC_SDA_HOLD,
404 &dev->sda_hold_time);
405 if (ret)
406 goto err_release_lock;
407 }
408
409 /*
410 * Workaround for avoiding TX arbitration lost in case I2C
411 * slave pulls SDA down "too quickly" after falling edge of
412 * SCL by enabling non-zero SDA RX hold. Specification says it
413 * extends incoming SDA low to high transition while SCL is
414 * high but it appears to help also above issue.
415 */
416 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
417 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
418
419 dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
420 dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
421 dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
422 } else if (dev->set_sda_hold_time) {
423 dev->set_sda_hold_time(dev);
424 } else if (dev->sda_hold_time) {
425 dev_warn(dev->dev,
426 "Hardware too old to adjust SDA hold time.\n");
427 dev->sda_hold_time = 0;
428 }
429
430 err_release_lock:
431 i2c_dw_release_lock(dev);
432
433 return ret;
434 }
435
__i2c_dw_disable(struct dw_i2c_dev * dev)436 void __i2c_dw_disable(struct dw_i2c_dev *dev)
437 {
438 int timeout = 100;
439 u32 status;
440
441 do {
442 __i2c_dw_disable_nowait(dev);
443 /*
444 * The enable status register may be unimplemented, but
445 * in that case this test reads zero and exits the loop.
446 */
447 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status);
448 if ((status & 1) == 0)
449 return;
450
451 /*
452 * Wait 10 times the signaling period of the highest I2C
453 * transfer supported by the driver (for 400KHz this is
454 * 25us) as described in the DesignWare I2C databook.
455 */
456 usleep_range(25, 250);
457 } while (timeout--);
458
459 dev_warn(dev->dev, "timeout in disabling adapter\n");
460 }
461
i2c_dw_clk_rate(struct dw_i2c_dev * dev)462 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
463 {
464 /*
465 * Clock is not necessary if we got LCNT/HCNT values directly from
466 * the platform code.
467 */
468 if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
469 return 0;
470 return dev->get_clk_rate_khz(dev);
471 }
472
i2c_dw_prepare_clk(struct dw_i2c_dev * dev,bool prepare)473 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
474 {
475 int ret;
476
477 if (IS_ERR(dev->clk))
478 return PTR_ERR(dev->clk);
479
480 if (prepare) {
481 /* Optional interface clock */
482 ret = clk_prepare_enable(dev->pclk);
483 if (ret)
484 return ret;
485
486 ret = clk_prepare_enable(dev->clk);
487 if (ret)
488 clk_disable_unprepare(dev->pclk);
489
490 return ret;
491 }
492
493 clk_disable_unprepare(dev->clk);
494 clk_disable_unprepare(dev->pclk);
495
496 return 0;
497 }
498 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
499
i2c_dw_acquire_lock(struct dw_i2c_dev * dev)500 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
501 {
502 int ret;
503
504 if (!dev->acquire_lock)
505 return 0;
506
507 ret = dev->acquire_lock();
508 if (!ret)
509 return 0;
510
511 dev_err(dev->dev, "couldn't acquire bus ownership\n");
512
513 return ret;
514 }
515
i2c_dw_release_lock(struct dw_i2c_dev * dev)516 void i2c_dw_release_lock(struct dw_i2c_dev *dev)
517 {
518 if (dev->release_lock)
519 dev->release_lock();
520 }
521
522 /*
523 * Waiting for bus not busy
524 */
i2c_dw_wait_bus_not_busy(struct dw_i2c_dev * dev)525 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
526 {
527 u32 status;
528 int ret;
529
530 ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
531 !(status & DW_IC_STATUS_ACTIVITY),
532 1100, 20000);
533 if (ret) {
534 dev_warn(dev->dev, "timeout waiting for bus ready\n");
535
536 i2c_recover_bus(&dev->adapter);
537
538 regmap_read(dev->map, DW_IC_STATUS, &status);
539 if (!(status & DW_IC_STATUS_ACTIVITY))
540 ret = 0;
541 }
542
543 return ret;
544 }
545
i2c_dw_handle_tx_abort(struct dw_i2c_dev * dev)546 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
547 {
548 unsigned long abort_source = dev->abort_source;
549 int i;
550
551 if (abort_source & DW_IC_TX_ABRT_NOACK) {
552 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
553 dev_dbg(dev->dev,
554 "%s: %s\n", __func__, abort_sources[i]);
555 return -EREMOTEIO;
556 }
557
558 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
559 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
560
561 if (abort_source & DW_IC_TX_ARB_LOST)
562 return -EAGAIN;
563 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
564 return -EINVAL; /* wrong msgs[] data */
565 else
566 return -EIO;
567 }
568
i2c_dw_set_fifo_size(struct dw_i2c_dev * dev)569 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
570 {
571 u32 param, tx_fifo_depth, rx_fifo_depth;
572 int ret;
573
574 /*
575 * Try to detect the FIFO depth if not set by interface driver,
576 * the depth could be from 2 to 256 from HW spec.
577 */
578 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m);
579 if (ret)
580 return ret;
581
582 tx_fifo_depth = ((param >> 16) & 0xff) + 1;
583 rx_fifo_depth = ((param >> 8) & 0xff) + 1;
584 if (!dev->tx_fifo_depth) {
585 dev->tx_fifo_depth = tx_fifo_depth;
586 dev->rx_fifo_depth = rx_fifo_depth;
587 } else if (tx_fifo_depth >= 2) {
588 dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth,
589 tx_fifo_depth);
590 dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,
591 rx_fifo_depth);
592 }
593
594 return 0;
595 }
596
i2c_dw_func(struct i2c_adapter * adap)597 u32 i2c_dw_func(struct i2c_adapter *adap)
598 {
599 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
600
601 return dev->functionality;
602 }
603
i2c_dw_disable(struct dw_i2c_dev * dev)604 void i2c_dw_disable(struct dw_i2c_dev *dev)
605 {
606 u32 dummy;
607
608 /* Disable controller */
609 __i2c_dw_disable(dev);
610
611 /* Disable all interrupts */
612 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
613 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
614 }
615
i2c_dw_disable_int(struct dw_i2c_dev * dev)616 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
617 {
618 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
619 }
620
621 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
622 MODULE_LICENSE("GPL");
623