1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
6 *
7 * This code was implemented by Mocean Laboratories AB when porting linux
8 * to the automotive development board Russellville. The copyright holder
9 * as seen in the header is Intel corporation.
10 * Mocean Laboratories forked off the GNU/Linux platform work into a
11 * separate company called Pelagicore AB, which committed the code to the
12 * kernel.
13 */
14
15 /* Supports:
16 * Xilinx IIC
17 */
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/wait.h>
27 #include <linux/platform_data/i2c-xiic.h>
28 #include <linux/io.h>
29 #include <linux/slab.h>
30 #include <linux/of.h>
31 #include <linux/clk.h>
32 #include <linux/pm_runtime.h>
33
34 #define DRIVER_NAME "xiic-i2c"
35
36 enum xilinx_i2c_state {
37 STATE_DONE,
38 STATE_ERROR,
39 STATE_START
40 };
41
42 enum xiic_endian {
43 LITTLE,
44 BIG
45 };
46
47 /**
48 * struct xiic_i2c - Internal representation of the XIIC I2C bus
49 * @dev: Pointer to device structure
50 * @base: Memory base of the HW registers
51 * @wait: Wait queue for callers
52 * @adap: Kernel adapter representation
53 * @tx_msg: Messages from above to be sent
54 * @lock: Mutual exclusion
55 * @tx_pos: Current pos in TX message
56 * @nmsgs: Number of messages in tx_msg
57 * @rx_msg: Current RX message
58 * @rx_pos: Position within current RX message
59 * @endianness: big/little-endian byte order
60 * @clk: Pointer to AXI4-lite input clock
61 * @state: See STATE_
62 * @singlemaster: Indicates bus is single master
63 */
64 struct xiic_i2c {
65 struct device *dev;
66 void __iomem *base;
67 wait_queue_head_t wait;
68 struct i2c_adapter adap;
69 struct i2c_msg *tx_msg;
70 struct mutex lock;
71 unsigned int tx_pos;
72 unsigned int nmsgs;
73 struct i2c_msg *rx_msg;
74 int rx_pos;
75 enum xiic_endian endianness;
76 struct clk *clk;
77 enum xilinx_i2c_state state;
78 bool singlemaster;
79 };
80
81
82 #define XIIC_MSB_OFFSET 0
83 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
84
85 /*
86 * Register offsets in bytes from RegisterBase. Three is added to the
87 * base offset to access LSB (IBM style) of the word
88 */
89 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
90 #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
91 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
92 #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
93 #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
94 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
95 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
96 #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
97 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
98 #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
99
100 /* Control Register masks */
101 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
102 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
103 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
104 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
105 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
106 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
107 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
108
109 /* Status Register masks */
110 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
111 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
112 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
113 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
114 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
115 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
116 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
117 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
118
119 /* Interrupt Status Register masks Interrupt occurs when... */
120 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
121 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
122 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
123 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
124 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
125 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
126 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
127 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
128
129 /* The following constants specify the depth of the FIFOs */
130 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
131 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
132
133 /* The following constants specify groups of interrupts that are typically
134 * enabled or disables at the same time
135 */
136 #define XIIC_TX_INTERRUPTS \
137 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
138
139 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
140
141 /*
142 * Tx Fifo upper bit masks.
143 */
144 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
145 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
146
147 /*
148 * The following constants define the register offsets for the Interrupt
149 * registers. There are some holes in the memory map for reserved addresses
150 * to allow other registers to be added and still match the memory map of the
151 * interrupt controller registers
152 */
153 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
154 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
155 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
156 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
157
158 #define XIIC_RESET_MASK 0xAUL
159
160 #define XIIC_PM_TIMEOUT 1000 /* ms */
161 /* timeout waiting for the controller to respond */
162 #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000))
163 /*
164 * The following constant is used for the device global interrupt enable
165 * register, to enable all interrupts for the device, this is the only bit
166 * in the register
167 */
168 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL
169
170 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
171 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
172
173 static int xiic_start_xfer(struct xiic_i2c *i2c);
174 static void __xiic_start_xfer(struct xiic_i2c *i2c);
175
176 /*
177 * For the register read and write functions, a little-endian and big-endian
178 * version are necessary. Endianness is detected during the probe function.
179 * Only the least significant byte [doublet] of the register are ever
180 * accessed. This requires an offset of 3 [2] from the base address for
181 * big-endian systems.
182 */
183
xiic_setreg8(struct xiic_i2c * i2c,int reg,u8 value)184 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
185 {
186 if (i2c->endianness == LITTLE)
187 iowrite8(value, i2c->base + reg);
188 else
189 iowrite8(value, i2c->base + reg + 3);
190 }
191
xiic_getreg8(struct xiic_i2c * i2c,int reg)192 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
193 {
194 u8 ret;
195
196 if (i2c->endianness == LITTLE)
197 ret = ioread8(i2c->base + reg);
198 else
199 ret = ioread8(i2c->base + reg + 3);
200 return ret;
201 }
202
xiic_setreg16(struct xiic_i2c * i2c,int reg,u16 value)203 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
204 {
205 if (i2c->endianness == LITTLE)
206 iowrite16(value, i2c->base + reg);
207 else
208 iowrite16be(value, i2c->base + reg + 2);
209 }
210
xiic_setreg32(struct xiic_i2c * i2c,int reg,int value)211 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
212 {
213 if (i2c->endianness == LITTLE)
214 iowrite32(value, i2c->base + reg);
215 else
216 iowrite32be(value, i2c->base + reg);
217 }
218
xiic_getreg32(struct xiic_i2c * i2c,int reg)219 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
220 {
221 u32 ret;
222
223 if (i2c->endianness == LITTLE)
224 ret = ioread32(i2c->base + reg);
225 else
226 ret = ioread32be(i2c->base + reg);
227 return ret;
228 }
229
xiic_irq_dis(struct xiic_i2c * i2c,u32 mask)230 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
231 {
232 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
233 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
234 }
235
xiic_irq_en(struct xiic_i2c * i2c,u32 mask)236 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
237 {
238 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
239 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
240 }
241
xiic_irq_clr(struct xiic_i2c * i2c,u32 mask)242 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
243 {
244 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
245 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
246 }
247
xiic_irq_clr_en(struct xiic_i2c * i2c,u32 mask)248 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
249 {
250 xiic_irq_clr(i2c, mask);
251 xiic_irq_en(i2c, mask);
252 }
253
xiic_clear_rx_fifo(struct xiic_i2c * i2c)254 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
255 {
256 u8 sr;
257 unsigned long timeout;
258
259 timeout = jiffies + XIIC_I2C_TIMEOUT;
260 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
261 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
262 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) {
263 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
264 if (time_after(jiffies, timeout)) {
265 dev_err(i2c->dev, "Failed to clear rx fifo\n");
266 return -ETIMEDOUT;
267 }
268 }
269
270 return 0;
271 }
272
xiic_reinit(struct xiic_i2c * i2c)273 static int xiic_reinit(struct xiic_i2c *i2c)
274 {
275 int ret;
276
277 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
278
279 /* Set receive Fifo depth to maximum (zero based). */
280 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
281
282 /* Reset Tx Fifo. */
283 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
284
285 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
286 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
287
288 /* make sure RX fifo is empty */
289 ret = xiic_clear_rx_fifo(i2c);
290 if (ret)
291 return ret;
292
293 /* Enable interrupts */
294 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
295
296 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
297
298 return 0;
299 }
300
xiic_deinit(struct xiic_i2c * i2c)301 static void xiic_deinit(struct xiic_i2c *i2c)
302 {
303 u8 cr;
304
305 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
306
307 /* Disable IIC Device. */
308 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
309 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
310 }
311
xiic_read_rx(struct xiic_i2c * i2c)312 static void xiic_read_rx(struct xiic_i2c *i2c)
313 {
314 u8 bytes_in_fifo;
315 int i;
316
317 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
318
319 dev_dbg(i2c->adap.dev.parent,
320 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",
321 __func__, bytes_in_fifo, xiic_rx_space(i2c),
322 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
323 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
324
325 if (bytes_in_fifo > xiic_rx_space(i2c))
326 bytes_in_fifo = xiic_rx_space(i2c);
327
328 for (i = 0; i < bytes_in_fifo; i++)
329 i2c->rx_msg->buf[i2c->rx_pos++] =
330 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
331
332 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
333 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
334 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
335 }
336
xiic_tx_fifo_space(struct xiic_i2c * i2c)337 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
338 {
339 /* return the actual space left in the FIFO */
340 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
341 }
342
xiic_fill_tx_fifo(struct xiic_i2c * i2c)343 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
344 {
345 u8 fifo_space = xiic_tx_fifo_space(i2c);
346 int len = xiic_tx_space(i2c);
347
348 len = (len > fifo_space) ? fifo_space : len;
349
350 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
351 __func__, len, fifo_space);
352
353 while (len--) {
354 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
355 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
356 /* last message in transfer -> STOP */
357 data |= XIIC_TX_DYN_STOP_MASK;
358 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
359 }
360 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
361 }
362 }
363
xiic_wakeup(struct xiic_i2c * i2c,int code)364 static void xiic_wakeup(struct xiic_i2c *i2c, int code)
365 {
366 i2c->tx_msg = NULL;
367 i2c->rx_msg = NULL;
368 i2c->nmsgs = 0;
369 i2c->state = code;
370 wake_up(&i2c->wait);
371 }
372
xiic_process(int irq,void * dev_id)373 static irqreturn_t xiic_process(int irq, void *dev_id)
374 {
375 struct xiic_i2c *i2c = dev_id;
376 u32 pend, isr, ier;
377 u32 clr = 0;
378
379 /* Get the interrupt Status from the IPIF. There is no clearing of
380 * interrupts in the IPIF. Interrupts must be cleared at the source.
381 * To find which interrupts are pending; AND interrupts pending with
382 * interrupts masked.
383 */
384 mutex_lock(&i2c->lock);
385 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
386 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
387 pend = isr & ier;
388
389 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
390 __func__, ier, isr, pend);
391 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
392 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
393 i2c->tx_msg, i2c->nmsgs);
394
395
396 /* Service requesting interrupt */
397 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
398 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
399 !(pend & XIIC_INTR_RX_FULL_MASK))) {
400 /* bus arbritration lost, or...
401 * Transmit error _OR_ RX completed
402 * if this happens when RX_FULL is not set
403 * this is probably a TX error
404 */
405
406 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
407
408 /* dynamic mode seem to suffer from problems if we just flushes
409 * fifos and the next message is a TX with len 0 (only addr)
410 * reset the IP instead of just flush fifos
411 */
412 xiic_reinit(i2c);
413
414 if (i2c->rx_msg)
415 xiic_wakeup(i2c, STATE_ERROR);
416 if (i2c->tx_msg)
417 xiic_wakeup(i2c, STATE_ERROR);
418 }
419 if (pend & XIIC_INTR_RX_FULL_MASK) {
420 /* Receive register/FIFO is full */
421
422 clr |= XIIC_INTR_RX_FULL_MASK;
423 if (!i2c->rx_msg) {
424 dev_dbg(i2c->adap.dev.parent,
425 "%s unexpected RX IRQ\n", __func__);
426 xiic_clear_rx_fifo(i2c);
427 goto out;
428 }
429
430 xiic_read_rx(i2c);
431 if (xiic_rx_space(i2c) == 0) {
432 /* this is the last part of the message */
433 i2c->rx_msg = NULL;
434
435 /* also clear TX error if there (RX complete) */
436 clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
437
438 dev_dbg(i2c->adap.dev.parent,
439 "%s end of message, nmsgs: %d\n",
440 __func__, i2c->nmsgs);
441
442 /* send next message if this wasn't the last,
443 * otherwise the transfer will be finialise when
444 * receiving the bus not busy interrupt
445 */
446 if (i2c->nmsgs > 1) {
447 i2c->nmsgs--;
448 i2c->tx_msg++;
449 dev_dbg(i2c->adap.dev.parent,
450 "%s will start next...\n", __func__);
451
452 __xiic_start_xfer(i2c);
453 }
454 }
455 }
456 if (pend & XIIC_INTR_BNB_MASK) {
457 /* IIC bus has transitioned to not busy */
458 clr |= XIIC_INTR_BNB_MASK;
459
460 /* The bus is not busy, disable BusNotBusy interrupt */
461 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
462
463 if (!i2c->tx_msg)
464 goto out;
465
466 if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
467 xiic_tx_space(i2c) == 0)
468 xiic_wakeup(i2c, STATE_DONE);
469 else
470 xiic_wakeup(i2c, STATE_ERROR);
471 }
472 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
473 /* Transmit register/FIFO is empty or ½ empty */
474
475 clr |= (pend &
476 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
477
478 if (!i2c->tx_msg) {
479 dev_dbg(i2c->adap.dev.parent,
480 "%s unexpected TX IRQ\n", __func__);
481 goto out;
482 }
483
484 xiic_fill_tx_fifo(i2c);
485
486 /* current message sent and there is space in the fifo */
487 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
488 dev_dbg(i2c->adap.dev.parent,
489 "%s end of message sent, nmsgs: %d\n",
490 __func__, i2c->nmsgs);
491 if (i2c->nmsgs > 1) {
492 i2c->nmsgs--;
493 i2c->tx_msg++;
494 __xiic_start_xfer(i2c);
495 } else {
496 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
497
498 dev_dbg(i2c->adap.dev.parent,
499 "%s Got TX IRQ but no more to do...\n",
500 __func__);
501 }
502 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
503 /* current frame is sent and is last,
504 * make sure to disable tx half
505 */
506 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
507 }
508 out:
509 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
510
511 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
512 mutex_unlock(&i2c->lock);
513 return IRQ_HANDLED;
514 }
515
xiic_bus_busy(struct xiic_i2c * i2c)516 static int xiic_bus_busy(struct xiic_i2c *i2c)
517 {
518 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
519
520 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
521 }
522
xiic_busy(struct xiic_i2c * i2c)523 static int xiic_busy(struct xiic_i2c *i2c)
524 {
525 int tries = 3;
526 int err;
527
528 if (i2c->tx_msg)
529 return -EBUSY;
530
531 /* In single master mode bus can only be busy, when in use by this
532 * driver. If the register indicates bus being busy for some reason we
533 * should ignore it, since bus will never be released and i2c will be
534 * stuck forever.
535 */
536 if (i2c->singlemaster) {
537 return 0;
538 }
539
540 /* for instance if previous transfer was terminated due to TX error
541 * it might be that the bus is on it's way to become available
542 * give it at most 3 ms to wake
543 */
544 err = xiic_bus_busy(i2c);
545 while (err && tries--) {
546 msleep(1);
547 err = xiic_bus_busy(i2c);
548 }
549
550 return err;
551 }
552
xiic_start_recv(struct xiic_i2c * i2c)553 static void xiic_start_recv(struct xiic_i2c *i2c)
554 {
555 u8 rx_watermark;
556 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
557 unsigned long flags;
558
559 /* Clear and enable Rx full interrupt. */
560 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
561
562 /* we want to get all but last byte, because the TX_ERROR IRQ is used
563 * to inidicate error ACK on the address, and negative ack on the last
564 * received byte, so to not mix them receive all but last.
565 * In the case where there is only one byte to receive
566 * we can check if ERROR and RX full is set at the same time
567 */
568 rx_watermark = msg->len;
569 if (rx_watermark > IIC_RX_FIFO_DEPTH)
570 rx_watermark = IIC_RX_FIFO_DEPTH;
571 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
572
573 local_irq_save(flags);
574 if (!(msg->flags & I2C_M_NOSTART))
575 /* write the address */
576 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
577 i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK);
578
579 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
580
581 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
582 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
583 local_irq_restore(flags);
584
585 if (i2c->nmsgs == 1)
586 /* very last, enable bus not busy as well */
587 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
588
589 /* the message is tx:ed */
590 i2c->tx_pos = msg->len;
591 }
592
xiic_start_send(struct xiic_i2c * i2c)593 static void xiic_start_send(struct xiic_i2c *i2c)
594 {
595 struct i2c_msg *msg = i2c->tx_msg;
596
597 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
598
599 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
600 __func__, msg, msg->len);
601 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
602 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
603 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
604
605 if (!(msg->flags & I2C_M_NOSTART)) {
606 /* write the address */
607 u16 data = i2c_8bit_addr_from_msg(msg) |
608 XIIC_TX_DYN_START_MASK;
609 if ((i2c->nmsgs == 1) && msg->len == 0)
610 /* no data and last message -> add STOP */
611 data |= XIIC_TX_DYN_STOP_MASK;
612
613 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
614 }
615
616 xiic_fill_tx_fifo(i2c);
617
618 /* Clear any pending Tx empty, Tx Error and then enable them. */
619 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
620 XIIC_INTR_BNB_MASK);
621 }
622
xiic_isr(int irq,void * dev_id)623 static irqreturn_t xiic_isr(int irq, void *dev_id)
624 {
625 struct xiic_i2c *i2c = dev_id;
626 u32 pend, isr, ier;
627 irqreturn_t ret = IRQ_NONE;
628 /* Do not processes a devices interrupts if the device has no
629 * interrupts pending
630 */
631
632 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
633
634 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
635 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
636 pend = isr & ier;
637 if (pend)
638 ret = IRQ_WAKE_THREAD;
639
640 return ret;
641 }
642
__xiic_start_xfer(struct xiic_i2c * i2c)643 static void __xiic_start_xfer(struct xiic_i2c *i2c)
644 {
645 int first = 1;
646 int fifo_space = xiic_tx_fifo_space(i2c);
647 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
648 __func__, i2c->tx_msg, fifo_space);
649
650 if (!i2c->tx_msg)
651 return;
652
653 i2c->rx_pos = 0;
654 i2c->tx_pos = 0;
655 i2c->state = STATE_START;
656 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
657 if (!first) {
658 i2c->nmsgs--;
659 i2c->tx_msg++;
660 i2c->tx_pos = 0;
661 } else
662 first = 0;
663
664 if (i2c->tx_msg->flags & I2C_M_RD) {
665 /* we dont date putting several reads in the FIFO */
666 xiic_start_recv(i2c);
667 return;
668 } else {
669 xiic_start_send(i2c);
670 if (xiic_tx_space(i2c) != 0) {
671 /* the message could not be completely sent */
672 break;
673 }
674 }
675
676 fifo_space = xiic_tx_fifo_space(i2c);
677 }
678
679 /* there are more messages or the current one could not be completely
680 * put into the FIFO, also enable the half empty interrupt
681 */
682 if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
683 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
684
685 }
686
xiic_start_xfer(struct xiic_i2c * i2c)687 static int xiic_start_xfer(struct xiic_i2c *i2c)
688 {
689 int ret;
690 mutex_lock(&i2c->lock);
691
692 ret = xiic_reinit(i2c);
693 if (!ret)
694 __xiic_start_xfer(i2c);
695
696 mutex_unlock(&i2c->lock);
697
698 return ret;
699 }
700
xiic_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)701 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
702 {
703 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
704 int err;
705
706 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
707 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
708
709 err = pm_runtime_resume_and_get(i2c->dev);
710 if (err < 0)
711 return err;
712
713 err = xiic_busy(i2c);
714 if (err)
715 goto out;
716
717 i2c->tx_msg = msgs;
718 i2c->nmsgs = num;
719
720 err = xiic_start_xfer(i2c);
721 if (err < 0) {
722 dev_err(adap->dev.parent, "Error xiic_start_xfer\n");
723 goto out;
724 }
725
726 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
727 (i2c->state == STATE_DONE), HZ)) {
728 err = (i2c->state == STATE_DONE) ? num : -EIO;
729 goto out;
730 } else {
731 i2c->tx_msg = NULL;
732 i2c->rx_msg = NULL;
733 i2c->nmsgs = 0;
734 err = -ETIMEDOUT;
735 goto out;
736 }
737 out:
738 pm_runtime_mark_last_busy(i2c->dev);
739 pm_runtime_put_autosuspend(i2c->dev);
740 return err;
741 }
742
xiic_func(struct i2c_adapter * adap)743 static u32 xiic_func(struct i2c_adapter *adap)
744 {
745 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
746 }
747
748 static const struct i2c_algorithm xiic_algorithm = {
749 .master_xfer = xiic_xfer,
750 .functionality = xiic_func,
751 };
752
753 static const struct i2c_adapter_quirks xiic_quirks = {
754 .max_read_len = 255,
755 };
756
757 static const struct i2c_adapter xiic_adapter = {
758 .owner = THIS_MODULE,
759 .name = DRIVER_NAME,
760 .class = I2C_CLASS_DEPRECATED,
761 .algo = &xiic_algorithm,
762 .quirks = &xiic_quirks,
763 };
764
765
xiic_i2c_probe(struct platform_device * pdev)766 static int xiic_i2c_probe(struct platform_device *pdev)
767 {
768 struct xiic_i2c *i2c;
769 struct xiic_i2c_platform_data *pdata;
770 struct resource *res;
771 int ret, irq;
772 u8 i;
773 u32 sr;
774
775 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
776 if (!i2c)
777 return -ENOMEM;
778
779 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
780 i2c->base = devm_ioremap_resource(&pdev->dev, res);
781 if (IS_ERR(i2c->base))
782 return PTR_ERR(i2c->base);
783
784 irq = platform_get_irq(pdev, 0);
785 if (irq < 0)
786 return irq;
787
788 pdata = dev_get_platdata(&pdev->dev);
789
790 /* hook up driver to tree */
791 platform_set_drvdata(pdev, i2c);
792 i2c->adap = xiic_adapter;
793 i2c_set_adapdata(&i2c->adap, i2c);
794 i2c->adap.dev.parent = &pdev->dev;
795 i2c->adap.dev.of_node = pdev->dev.of_node;
796
797 mutex_init(&i2c->lock);
798 init_waitqueue_head(&i2c->wait);
799
800 i2c->clk = devm_clk_get(&pdev->dev, NULL);
801 if (IS_ERR(i2c->clk)) {
802 if (PTR_ERR(i2c->clk) != -EPROBE_DEFER)
803 dev_err(&pdev->dev, "input clock not found.\n");
804 return PTR_ERR(i2c->clk);
805 }
806 ret = clk_prepare_enable(i2c->clk);
807 if (ret) {
808 dev_err(&pdev->dev, "Unable to enable clock.\n");
809 return ret;
810 }
811 i2c->dev = &pdev->dev;
812 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
813 pm_runtime_use_autosuspend(i2c->dev);
814 pm_runtime_set_active(i2c->dev);
815 pm_runtime_enable(i2c->dev);
816 ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,
817 xiic_process, IRQF_ONESHOT,
818 pdev->name, i2c);
819
820 if (ret < 0) {
821 dev_err(&pdev->dev, "Cannot claim IRQ\n");
822 goto err_clk_dis;
823 }
824
825 i2c->singlemaster =
826 of_property_read_bool(pdev->dev.of_node, "single-master");
827
828 /*
829 * Detect endianness
830 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
831 * set, assume that the endianness was wrong and swap.
832 */
833 i2c->endianness = LITTLE;
834 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
835 /* Reset is cleared in xiic_reinit */
836 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
837 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
838 i2c->endianness = BIG;
839
840 ret = xiic_reinit(i2c);
841 if (ret < 0) {
842 dev_err(&pdev->dev, "Cannot xiic_reinit\n");
843 goto err_clk_dis;
844 }
845
846 /* add i2c adapter to i2c tree */
847 ret = i2c_add_adapter(&i2c->adap);
848 if (ret) {
849 xiic_deinit(i2c);
850 goto err_clk_dis;
851 }
852
853 if (pdata) {
854 /* add in known devices to the bus */
855 for (i = 0; i < pdata->num_devices; i++)
856 i2c_new_client_device(&i2c->adap, pdata->devices + i);
857 }
858
859 return 0;
860
861 err_clk_dis:
862 pm_runtime_set_suspended(&pdev->dev);
863 pm_runtime_disable(&pdev->dev);
864 clk_disable_unprepare(i2c->clk);
865 return ret;
866 }
867
xiic_i2c_remove(struct platform_device * pdev)868 static int xiic_i2c_remove(struct platform_device *pdev)
869 {
870 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
871 int ret;
872
873 /* remove adapter & data */
874 i2c_del_adapter(&i2c->adap);
875
876 ret = pm_runtime_resume_and_get(i2c->dev);
877 if (ret < 0)
878 return ret;
879
880 xiic_deinit(i2c);
881 pm_runtime_put_sync(i2c->dev);
882 clk_disable_unprepare(i2c->clk);
883 pm_runtime_disable(&pdev->dev);
884 pm_runtime_set_suspended(&pdev->dev);
885 pm_runtime_dont_use_autosuspend(&pdev->dev);
886
887 return 0;
888 }
889
890 #if defined(CONFIG_OF)
891 static const struct of_device_id xiic_of_match[] = {
892 { .compatible = "xlnx,xps-iic-2.00.a", },
893 {},
894 };
895 MODULE_DEVICE_TABLE(of, xiic_of_match);
896 #endif
897
xiic_i2c_runtime_suspend(struct device * dev)898 static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev)
899 {
900 struct xiic_i2c *i2c = dev_get_drvdata(dev);
901
902 clk_disable(i2c->clk);
903
904 return 0;
905 }
906
xiic_i2c_runtime_resume(struct device * dev)907 static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev)
908 {
909 struct xiic_i2c *i2c = dev_get_drvdata(dev);
910 int ret;
911
912 ret = clk_enable(i2c->clk);
913 if (ret) {
914 dev_err(dev, "Cannot enable clock.\n");
915 return ret;
916 }
917
918 return 0;
919 }
920
921 static const struct dev_pm_ops xiic_dev_pm_ops = {
922 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend,
923 xiic_i2c_runtime_resume, NULL)
924 };
925 static struct platform_driver xiic_i2c_driver = {
926 .probe = xiic_i2c_probe,
927 .remove = xiic_i2c_remove,
928 .driver = {
929 .name = DRIVER_NAME,
930 .of_match_table = of_match_ptr(xiic_of_match),
931 .pm = &xiic_dev_pm_ops,
932 },
933 };
934
935 module_platform_driver(xiic_i2c_driver);
936
937 MODULE_AUTHOR("info@mocean-labs.com");
938 MODULE_DESCRIPTION("Xilinx I2C bus driver");
939 MODULE_LICENSE("GPL v2");
940 MODULE_ALIAS("platform:"DRIVER_NAME);
941