1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7124 SPI ADC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/spi/spi.h>
18
19 #include <linux/iio/iio.h>
20 #include <linux/iio/adc/ad_sigma_delta.h>
21 #include <linux/iio/sysfs.h>
22
23 /* AD7124 registers */
24 #define AD7124_COMMS 0x00
25 #define AD7124_STATUS 0x00
26 #define AD7124_ADC_CONTROL 0x01
27 #define AD7124_DATA 0x02
28 #define AD7124_IO_CONTROL_1 0x03
29 #define AD7124_IO_CONTROL_2 0x04
30 #define AD7124_ID 0x05
31 #define AD7124_ERROR 0x06
32 #define AD7124_ERROR_EN 0x07
33 #define AD7124_MCLK_COUNT 0x08
34 #define AD7124_CHANNEL(x) (0x09 + (x))
35 #define AD7124_CONFIG(x) (0x19 + (x))
36 #define AD7124_FILTER(x) (0x21 + (x))
37 #define AD7124_OFFSET(x) (0x29 + (x))
38 #define AD7124_GAIN(x) (0x31 + (x))
39
40 /* AD7124_STATUS */
41 #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
42
43 /* AD7124_ADC_CONTROL */
44 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
45 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
46 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
47 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
48 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
49 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
50
51 /* AD7124 ID */
52 #define AD7124_DEVICE_ID_MSK GENMASK(7, 4)
53 #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x)
54 #define AD7124_SILICON_REV_MSK GENMASK(3, 0)
55 #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x)
56
57 #define CHIPID_AD7124_4 0x0
58 #define CHIPID_AD7124_8 0x1
59
60 /* AD7124_CHANNEL_X */
61 #define AD7124_CHANNEL_EN_MSK BIT(15)
62 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
63 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
64 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
65 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
66 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
67 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
68 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
69
70 /* AD7124_CONFIG_X */
71 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
72 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
73 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
74 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
75 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
76 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
77 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(7, 6)
78 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
79
80 /* AD7124_FILTER_X */
81 #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
82 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
83 #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21)
84 #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
85
86 #define AD7124_SINC3_FILTER 2
87 #define AD7124_SINC4_FILTER 0
88
89 enum ad7124_ids {
90 ID_AD7124_4,
91 ID_AD7124_8,
92 };
93
94 enum ad7124_ref_sel {
95 AD7124_REFIN1,
96 AD7124_REFIN2,
97 AD7124_INT_REF,
98 AD7124_AVDD_REF,
99 };
100
101 enum ad7124_power_mode {
102 AD7124_LOW_POWER,
103 AD7124_MID_POWER,
104 AD7124_FULL_POWER,
105 };
106
107 static const unsigned int ad7124_gain[8] = {
108 1, 2, 4, 8, 16, 32, 64, 128
109 };
110
111 static const unsigned int ad7124_reg_size[] = {
112 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
113 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
114 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
115 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
116 3, 3, 3, 3, 3
117 };
118
119 static const int ad7124_master_clk_freq_hz[3] = {
120 [AD7124_LOW_POWER] = 76800,
121 [AD7124_MID_POWER] = 153600,
122 [AD7124_FULL_POWER] = 614400,
123 };
124
125 static const char * const ad7124_ref_names[] = {
126 [AD7124_REFIN1] = "refin1",
127 [AD7124_REFIN2] = "refin2",
128 [AD7124_INT_REF] = "int",
129 [AD7124_AVDD_REF] = "avdd",
130 };
131
132 struct ad7124_chip_info {
133 const char *name;
134 unsigned int chip_id;
135 unsigned int num_inputs;
136 };
137
138 struct ad7124_channel_config {
139 enum ad7124_ref_sel refsel;
140 bool bipolar;
141 bool buf_positive;
142 bool buf_negative;
143 unsigned int ain;
144 unsigned int vref_mv;
145 unsigned int pga_bits;
146 unsigned int odr;
147 unsigned int filter_type;
148 };
149
150 struct ad7124_state {
151 const struct ad7124_chip_info *chip_info;
152 struct ad_sigma_delta sd;
153 struct ad7124_channel_config *channel_config;
154 struct regulator *vref[4];
155 struct clk *mclk;
156 unsigned int adc_control;
157 unsigned int num_channels;
158 };
159
160 static const struct iio_chan_spec ad7124_channel_template = {
161 .type = IIO_VOLTAGE,
162 .indexed = 1,
163 .differential = 1,
164 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
165 BIT(IIO_CHAN_INFO_SCALE) |
166 BIT(IIO_CHAN_INFO_OFFSET) |
167 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
168 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
169 .scan_type = {
170 .sign = 'u',
171 .realbits = 24,
172 .storagebits = 32,
173 .shift = 8,
174 .endianness = IIO_BE,
175 },
176 };
177
178 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
179 [ID_AD7124_4] = {
180 .name = "ad7124-4",
181 .chip_id = CHIPID_AD7124_4,
182 .num_inputs = 8,
183 },
184 [ID_AD7124_8] = {
185 .name = "ad7124-8",
186 .chip_id = CHIPID_AD7124_8,
187 .num_inputs = 16,
188 },
189 };
190
ad7124_find_closest_match(const int * array,unsigned int size,int val)191 static int ad7124_find_closest_match(const int *array,
192 unsigned int size, int val)
193 {
194 int i, idx;
195 unsigned int diff_new, diff_old;
196
197 diff_old = U32_MAX;
198 idx = 0;
199
200 for (i = 0; i < size; i++) {
201 diff_new = abs(val - array[i]);
202 if (diff_new < diff_old) {
203 diff_old = diff_new;
204 idx = i;
205 }
206 }
207
208 return idx;
209 }
210
ad7124_spi_write_mask(struct ad7124_state * st,unsigned int addr,unsigned long mask,unsigned int val,unsigned int bytes)211 static int ad7124_spi_write_mask(struct ad7124_state *st,
212 unsigned int addr,
213 unsigned long mask,
214 unsigned int val,
215 unsigned int bytes)
216 {
217 unsigned int readval;
218 int ret;
219
220 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
221 if (ret < 0)
222 return ret;
223
224 readval &= ~mask;
225 readval |= val;
226
227 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
228 }
229
ad7124_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)230 static int ad7124_set_mode(struct ad_sigma_delta *sd,
231 enum ad_sigma_delta_mode mode)
232 {
233 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
234
235 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
236 st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
237
238 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
239 }
240
ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)241 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
242 {
243 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
244 unsigned int val;
245
246 val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
247 AD7124_CHANNEL_SETUP(channel);
248
249 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
250 }
251
252 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
253 .set_channel = ad7124_set_channel,
254 .set_mode = ad7124_set_mode,
255 .has_registers = true,
256 .addr_shift = 0,
257 .read_mask = BIT(6),
258 .data_reg = AD7124_DATA,
259 .irq_flags = IRQF_TRIGGER_FALLING,
260 };
261
ad7124_set_channel_odr(struct ad7124_state * st,unsigned int channel,unsigned int odr)262 static int ad7124_set_channel_odr(struct ad7124_state *st,
263 unsigned int channel,
264 unsigned int odr)
265 {
266 unsigned int fclk, odr_sel_bits;
267 int ret;
268
269 fclk = clk_get_rate(st->mclk);
270 /*
271 * FS[10:0] = fCLK / (fADC x 32) where:
272 * fADC is the output data rate
273 * fCLK is the master clock frequency
274 * FS[10:0] are the bits in the filter register
275 * FS[10:0] can have a value from 1 to 2047
276 */
277 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
278 if (odr_sel_bits < 1)
279 odr_sel_bits = 1;
280 else if (odr_sel_bits > 2047)
281 odr_sel_bits = 2047;
282
283 ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
284 AD7124_FILTER_FS_MSK,
285 AD7124_FILTER_FS(odr_sel_bits), 3);
286 if (ret < 0)
287 return ret;
288 /* fADC = fCLK / (FS[10:0] x 32) */
289 st->channel_config[channel].odr =
290 DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
291
292 return 0;
293 }
294
ad7124_set_channel_gain(struct ad7124_state * st,unsigned int channel,unsigned int gain)295 static int ad7124_set_channel_gain(struct ad7124_state *st,
296 unsigned int channel,
297 unsigned int gain)
298 {
299 unsigned int res;
300 int ret;
301
302 res = ad7124_find_closest_match(ad7124_gain,
303 ARRAY_SIZE(ad7124_gain), gain);
304 ret = ad7124_spi_write_mask(st, AD7124_CONFIG(channel),
305 AD7124_CONFIG_PGA_MSK,
306 AD7124_CONFIG_PGA(res), 2);
307 if (ret < 0)
308 return ret;
309
310 st->channel_config[channel].pga_bits = res;
311
312 return 0;
313 }
314
ad7124_get_3db_filter_freq(struct ad7124_state * st,unsigned int channel)315 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
316 unsigned int channel)
317 {
318 unsigned int fadc;
319
320 fadc = st->channel_config[channel].odr;
321
322 switch (st->channel_config[channel].filter_type) {
323 case AD7124_SINC3_FILTER:
324 return DIV_ROUND_CLOSEST(fadc * 230, 1000);
325 case AD7124_SINC4_FILTER:
326 return DIV_ROUND_CLOSEST(fadc * 262, 1000);
327 default:
328 return -EINVAL;
329 }
330 }
331
ad7124_set_3db_filter_freq(struct ad7124_state * st,unsigned int channel,unsigned int freq)332 static int ad7124_set_3db_filter_freq(struct ad7124_state *st,
333 unsigned int channel,
334 unsigned int freq)
335 {
336 unsigned int sinc4_3db_odr;
337 unsigned int sinc3_3db_odr;
338 unsigned int new_filter;
339 unsigned int new_odr;
340
341 sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
342 sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
343
344 if (sinc4_3db_odr > sinc3_3db_odr) {
345 new_filter = AD7124_SINC3_FILTER;
346 new_odr = sinc4_3db_odr;
347 } else {
348 new_filter = AD7124_SINC4_FILTER;
349 new_odr = sinc3_3db_odr;
350 }
351
352 if (st->channel_config[channel].filter_type != new_filter) {
353 int ret;
354
355 st->channel_config[channel].filter_type = new_filter;
356 ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
357 AD7124_FILTER_TYPE_MSK,
358 AD7124_FILTER_TYPE_SEL(new_filter),
359 3);
360 if (ret < 0)
361 return ret;
362 }
363
364 return ad7124_set_channel_odr(st, channel, new_odr);
365 }
366
ad7124_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)367 static int ad7124_read_raw(struct iio_dev *indio_dev,
368 struct iio_chan_spec const *chan,
369 int *val, int *val2, long info)
370 {
371 struct ad7124_state *st = iio_priv(indio_dev);
372 int idx, ret;
373
374 switch (info) {
375 case IIO_CHAN_INFO_RAW:
376 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
377 if (ret < 0)
378 return ret;
379
380 /* After the conversion is performed, disable the channel */
381 ret = ad_sd_write_reg(&st->sd,
382 AD7124_CHANNEL(chan->address), 2,
383 st->channel_config[chan->address].ain |
384 AD7124_CHANNEL_EN(0));
385 if (ret < 0)
386 return ret;
387
388 return IIO_VAL_INT;
389 case IIO_CHAN_INFO_SCALE:
390 idx = st->channel_config[chan->address].pga_bits;
391 *val = st->channel_config[chan->address].vref_mv;
392 if (st->channel_config[chan->address].bipolar)
393 *val2 = chan->scan_type.realbits - 1 + idx;
394 else
395 *val2 = chan->scan_type.realbits + idx;
396
397 return IIO_VAL_FRACTIONAL_LOG2;
398 case IIO_CHAN_INFO_OFFSET:
399 if (st->channel_config[chan->address].bipolar)
400 *val = -(1 << (chan->scan_type.realbits - 1));
401 else
402 *val = 0;
403
404 return IIO_VAL_INT;
405 case IIO_CHAN_INFO_SAMP_FREQ:
406 *val = st->channel_config[chan->address].odr;
407
408 return IIO_VAL_INT;
409 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
410 *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
411 return IIO_VAL_INT;
412 default:
413 return -EINVAL;
414 }
415 }
416
ad7124_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)417 static int ad7124_write_raw(struct iio_dev *indio_dev,
418 struct iio_chan_spec const *chan,
419 int val, int val2, long info)
420 {
421 struct ad7124_state *st = iio_priv(indio_dev);
422 unsigned int res, gain, full_scale, vref;
423
424 switch (info) {
425 case IIO_CHAN_INFO_SAMP_FREQ:
426 if (val2 != 0)
427 return -EINVAL;
428
429 return ad7124_set_channel_odr(st, chan->address, val);
430 case IIO_CHAN_INFO_SCALE:
431 if (val != 0)
432 return -EINVAL;
433
434 if (st->channel_config[chan->address].bipolar)
435 full_scale = 1 << (chan->scan_type.realbits - 1);
436 else
437 full_scale = 1 << chan->scan_type.realbits;
438
439 vref = st->channel_config[chan->address].vref_mv * 1000000LL;
440 res = DIV_ROUND_CLOSEST(vref, full_scale);
441 gain = DIV_ROUND_CLOSEST(res, val2);
442
443 return ad7124_set_channel_gain(st, chan->address, gain);
444 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
445 if (val2 != 0)
446 return -EINVAL;
447
448 return ad7124_set_3db_filter_freq(st, chan->address, val);
449 default:
450 return -EINVAL;
451 }
452 }
453
ad7124_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)454 static int ad7124_reg_access(struct iio_dev *indio_dev,
455 unsigned int reg,
456 unsigned int writeval,
457 unsigned int *readval)
458 {
459 struct ad7124_state *st = iio_priv(indio_dev);
460 int ret;
461
462 if (reg >= ARRAY_SIZE(ad7124_reg_size))
463 return -EINVAL;
464
465 if (readval)
466 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
467 readval);
468 else
469 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
470 writeval);
471
472 return ret;
473 }
474
475 static IIO_CONST_ATTR(in_voltage_scale_available,
476 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
477
478 static struct attribute *ad7124_attributes[] = {
479 &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
480 NULL,
481 };
482
483 static const struct attribute_group ad7124_attrs_group = {
484 .attrs = ad7124_attributes,
485 };
486
487 static const struct iio_info ad7124_info = {
488 .read_raw = ad7124_read_raw,
489 .write_raw = ad7124_write_raw,
490 .debugfs_reg_access = &ad7124_reg_access,
491 .validate_trigger = ad_sd_validate_trigger,
492 .attrs = &ad7124_attrs_group,
493 };
494
ad7124_soft_reset(struct ad7124_state * st)495 static int ad7124_soft_reset(struct ad7124_state *st)
496 {
497 unsigned int readval, timeout;
498 int ret;
499
500 ret = ad_sd_reset(&st->sd, 64);
501 if (ret < 0)
502 return ret;
503
504 timeout = 100;
505 do {
506 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
507 if (ret < 0)
508 return ret;
509
510 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
511 return 0;
512
513 /* The AD7124 requires typically 2ms to power up and settle */
514 usleep_range(100, 2000);
515 } while (--timeout);
516
517 dev_err(&st->sd.spi->dev, "Soft reset failed\n");
518
519 return -EIO;
520 }
521
ad7124_check_chip_id(struct ad7124_state * st)522 static int ad7124_check_chip_id(struct ad7124_state *st)
523 {
524 unsigned int readval, chip_id, silicon_rev;
525 int ret;
526
527 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
528 if (ret < 0)
529 return ret;
530
531 chip_id = AD7124_DEVICE_ID_GET(readval);
532 silicon_rev = AD7124_SILICON_REV_GET(readval);
533
534 if (chip_id != st->chip_info->chip_id) {
535 dev_err(&st->sd.spi->dev,
536 "Chip ID mismatch: expected %u, got %u\n",
537 st->chip_info->chip_id, chip_id);
538 return -ENODEV;
539 }
540
541 if (silicon_rev == 0) {
542 dev_err(&st->sd.spi->dev,
543 "Silicon revision empty. Chip may not be present\n");
544 return -ENODEV;
545 }
546
547 return 0;
548 }
549
ad7124_init_channel_vref(struct ad7124_state * st,unsigned int channel_number)550 static int ad7124_init_channel_vref(struct ad7124_state *st,
551 unsigned int channel_number)
552 {
553 unsigned int refsel = st->channel_config[channel_number].refsel;
554
555 switch (refsel) {
556 case AD7124_REFIN1:
557 case AD7124_REFIN2:
558 case AD7124_AVDD_REF:
559 if (IS_ERR(st->vref[refsel])) {
560 dev_err(&st->sd.spi->dev,
561 "Error, trying to use external voltage reference without a %s regulator.\n",
562 ad7124_ref_names[refsel]);
563 return PTR_ERR(st->vref[refsel]);
564 }
565 st->channel_config[channel_number].vref_mv =
566 regulator_get_voltage(st->vref[refsel]);
567 /* Conversion from uV to mV */
568 st->channel_config[channel_number].vref_mv /= 1000;
569 break;
570 case AD7124_INT_REF:
571 st->channel_config[channel_number].vref_mv = 2500;
572 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
573 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
574 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
575 2, st->adc_control);
576 default:
577 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
578 return -EINVAL;
579 }
580
581 return 0;
582 }
583
ad7124_of_parse_channel_config(struct iio_dev * indio_dev,struct device_node * np)584 static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
585 struct device_node *np)
586 {
587 struct ad7124_state *st = iio_priv(indio_dev);
588 struct device_node *child;
589 struct iio_chan_spec *chan;
590 struct ad7124_channel_config *chan_config;
591 unsigned int ain[2], channel = 0, tmp;
592 int ret;
593
594 st->num_channels = of_get_available_child_count(np);
595 if (!st->num_channels) {
596 dev_err(indio_dev->dev.parent, "no channel children\n");
597 return -ENODEV;
598 }
599
600 chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
601 sizeof(*chan), GFP_KERNEL);
602 if (!chan)
603 return -ENOMEM;
604
605 chan_config = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
606 sizeof(*chan_config), GFP_KERNEL);
607 if (!chan_config)
608 return -ENOMEM;
609
610 indio_dev->channels = chan;
611 indio_dev->num_channels = st->num_channels;
612 st->channel_config = chan_config;
613
614 for_each_available_child_of_node(np, child) {
615 ret = of_property_read_u32(child, "reg", &channel);
616 if (ret)
617 goto err;
618
619 if (channel >= indio_dev->num_channels) {
620 dev_err(indio_dev->dev.parent,
621 "Channel index >= number of channels\n");
622 ret = -EINVAL;
623 goto err;
624 }
625
626 ret = of_property_read_u32_array(child, "diff-channels",
627 ain, 2);
628 if (ret)
629 goto err;
630
631 st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
632 AD7124_CHANNEL_AINM(ain[1]);
633 st->channel_config[channel].bipolar =
634 of_property_read_bool(child, "bipolar");
635
636 ret = of_property_read_u32(child, "adi,reference-select", &tmp);
637 if (ret)
638 st->channel_config[channel].refsel = AD7124_INT_REF;
639 else
640 st->channel_config[channel].refsel = tmp;
641
642 st->channel_config[channel].buf_positive =
643 of_property_read_bool(child, "adi,buffered-positive");
644 st->channel_config[channel].buf_negative =
645 of_property_read_bool(child, "adi,buffered-negative");
646
647 chan[channel] = ad7124_channel_template;
648 chan[channel].address = channel;
649 chan[channel].scan_index = channel;
650 chan[channel].channel = ain[0];
651 chan[channel].channel2 = ain[1];
652 }
653
654 return 0;
655 err:
656 of_node_put(child);
657
658 return ret;
659 }
660
ad7124_setup(struct ad7124_state * st)661 static int ad7124_setup(struct ad7124_state *st)
662 {
663 unsigned int val, fclk, power_mode;
664 int i, ret, tmp;
665
666 fclk = clk_get_rate(st->mclk);
667 if (!fclk)
668 return -EINVAL;
669
670 /* The power mode changes the master clock frequency */
671 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
672 ARRAY_SIZE(ad7124_master_clk_freq_hz),
673 fclk);
674 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
675 ret = clk_set_rate(st->mclk, fclk);
676 if (ret)
677 return ret;
678 }
679
680 /* Set the power mode */
681 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
682 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
683 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
684 if (ret < 0)
685 return ret;
686
687 for (i = 0; i < st->num_channels; i++) {
688 val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);
689 ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);
690 if (ret < 0)
691 return ret;
692
693 ret = ad7124_init_channel_vref(st, i);
694 if (ret < 0)
695 return ret;
696
697 tmp = (st->channel_config[i].buf_positive << 1) +
698 st->channel_config[i].buf_negative;
699
700 val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |
701 AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel) |
702 AD7124_CONFIG_IN_BUFF(tmp);
703 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);
704 if (ret < 0)
705 return ret;
706 /*
707 * 9.38 SPS is the minimum output data rate supported
708 * regardless of the selected power mode. Round it up to 10 and
709 * set all the enabled channels to this default value.
710 */
711 ret = ad7124_set_channel_odr(st, i, 10);
712 }
713
714 return ret;
715 }
716
ad7124_reg_disable(void * r)717 static void ad7124_reg_disable(void *r)
718 {
719 regulator_disable(r);
720 }
721
ad7124_probe(struct spi_device * spi)722 static int ad7124_probe(struct spi_device *spi)
723 {
724 const struct ad7124_chip_info *info;
725 struct ad7124_state *st;
726 struct iio_dev *indio_dev;
727 int i, ret;
728
729 info = of_device_get_match_data(&spi->dev);
730 if (!info)
731 return -ENODEV;
732
733 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
734 if (!indio_dev)
735 return -ENOMEM;
736
737 st = iio_priv(indio_dev);
738
739 st->chip_info = info;
740
741 ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
742
743 spi_set_drvdata(spi, indio_dev);
744
745 indio_dev->name = st->chip_info->name;
746 indio_dev->modes = INDIO_DIRECT_MODE;
747 indio_dev->info = &ad7124_info;
748
749 ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
750 if (ret < 0)
751 return ret;
752
753 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
754 if (i == AD7124_INT_REF)
755 continue;
756
757 st->vref[i] = devm_regulator_get_optional(&spi->dev,
758 ad7124_ref_names[i]);
759 if (PTR_ERR(st->vref[i]) == -ENODEV)
760 continue;
761 else if (IS_ERR(st->vref[i]))
762 return PTR_ERR(st->vref[i]);
763
764 ret = regulator_enable(st->vref[i]);
765 if (ret)
766 return ret;
767
768 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
769 st->vref[i]);
770 if (ret)
771 return ret;
772 }
773
774 st->mclk = devm_clk_get(&spi->dev, "mclk");
775 if (IS_ERR(st->mclk))
776 return PTR_ERR(st->mclk);
777
778 ret = clk_prepare_enable(st->mclk);
779 if (ret < 0)
780 return ret;
781
782 ret = ad7124_soft_reset(st);
783 if (ret < 0)
784 goto error_clk_disable_unprepare;
785
786 ret = ad7124_check_chip_id(st);
787 if (ret)
788 goto error_clk_disable_unprepare;
789
790 ret = ad7124_setup(st);
791 if (ret < 0)
792 goto error_clk_disable_unprepare;
793
794 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
795 if (ret < 0)
796 goto error_clk_disable_unprepare;
797
798 ret = iio_device_register(indio_dev);
799 if (ret < 0) {
800 dev_err(&spi->dev, "Failed to register iio device\n");
801 goto error_remove_trigger;
802 }
803
804 return 0;
805
806 error_remove_trigger:
807 ad_sd_cleanup_buffer_and_trigger(indio_dev);
808 error_clk_disable_unprepare:
809 clk_disable_unprepare(st->mclk);
810
811 return ret;
812 }
813
ad7124_remove(struct spi_device * spi)814 static int ad7124_remove(struct spi_device *spi)
815 {
816 struct iio_dev *indio_dev = spi_get_drvdata(spi);
817 struct ad7124_state *st = iio_priv(indio_dev);
818
819 iio_device_unregister(indio_dev);
820 ad_sd_cleanup_buffer_and_trigger(indio_dev);
821 clk_disable_unprepare(st->mclk);
822
823 return 0;
824 }
825
826 static const struct of_device_id ad7124_of_match[] = {
827 { .compatible = "adi,ad7124-4",
828 .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
829 { .compatible = "adi,ad7124-8",
830 .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
831 { },
832 };
833 MODULE_DEVICE_TABLE(of, ad7124_of_match);
834
835 static struct spi_driver ad71124_driver = {
836 .driver = {
837 .name = "ad7124",
838 .of_match_table = ad7124_of_match,
839 },
840 .probe = ad7124_probe,
841 .remove = ad7124_remove,
842 };
843 module_spi_driver(ad71124_driver);
844
845 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
846 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
847 MODULE_LICENSE("GPL");
848