1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Analog Devices AD7466/7/8 AD7476/5/7/8 (A) SPI ADC driver
4 * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
5 *
6 * Copyright 2010 Analog Devices Inc.
7 */
8
9 #include <linux/device.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sysfs.h>
13 #include <linux/spi/spi.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/err.h>
17 #include <linux/module.h>
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26
27 struct ad7476_state;
28
29 struct ad7476_chip_info {
30 unsigned int int_vref_uv;
31 struct iio_chan_spec channel[2];
32 /* channels used when convst gpio is defined */
33 struct iio_chan_spec convst_channel[2];
34 void (*reset)(struct ad7476_state *);
35 };
36
37 struct ad7476_state {
38 struct spi_device *spi;
39 const struct ad7476_chip_info *chip_info;
40 struct regulator *reg;
41 struct gpio_desc *convst_gpio;
42 struct spi_transfer xfer;
43 struct spi_message msg;
44 /*
45 * DMA (thus cache coherency maintenance) requires the
46 * transfer buffers to live in their own cache lines.
47 * Make the buffer large enough for one 16 bit sample and one 64 bit
48 * aligned 64 bit timestamp.
49 */
50 unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)]
51 ____cacheline_aligned;
52 };
53
54 enum ad7476_supported_device_ids {
55 ID_AD7091R,
56 ID_AD7276,
57 ID_AD7277,
58 ID_AD7278,
59 ID_AD7466,
60 ID_AD7467,
61 ID_AD7468,
62 ID_AD7495,
63 ID_AD7940,
64 ID_ADC081S,
65 ID_ADC101S,
66 ID_ADC121S,
67 ID_ADS7866,
68 ID_ADS7867,
69 ID_ADS7868,
70 };
71
ad7091_convst(struct ad7476_state * st)72 static void ad7091_convst(struct ad7476_state *st)
73 {
74 if (!st->convst_gpio)
75 return;
76
77 gpiod_set_value(st->convst_gpio, 0);
78 udelay(1); /* CONVST pulse width: 10 ns min */
79 gpiod_set_value(st->convst_gpio, 1);
80 udelay(1); /* Conversion time: 650 ns max */
81 }
82
ad7476_trigger_handler(int irq,void * p)83 static irqreturn_t ad7476_trigger_handler(int irq, void *p)
84 {
85 struct iio_poll_func *pf = p;
86 struct iio_dev *indio_dev = pf->indio_dev;
87 struct ad7476_state *st = iio_priv(indio_dev);
88 int b_sent;
89
90 ad7091_convst(st);
91
92 b_sent = spi_sync(st->spi, &st->msg);
93 if (b_sent < 0)
94 goto done;
95
96 iio_push_to_buffers_with_timestamp(indio_dev, st->data,
97 iio_get_time_ns(indio_dev));
98 done:
99 iio_trigger_notify_done(indio_dev->trig);
100
101 return IRQ_HANDLED;
102 }
103
ad7091_reset(struct ad7476_state * st)104 static void ad7091_reset(struct ad7476_state *st)
105 {
106 /* Any transfers with 8 scl cycles will reset the device */
107 spi_read(st->spi, st->data, 1);
108 }
109
ad7476_scan_direct(struct ad7476_state * st)110 static int ad7476_scan_direct(struct ad7476_state *st)
111 {
112 int ret;
113
114 ad7091_convst(st);
115
116 ret = spi_sync(st->spi, &st->msg);
117 if (ret)
118 return ret;
119
120 return be16_to_cpup((__be16 *)st->data);
121 }
122
ad7476_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)123 static int ad7476_read_raw(struct iio_dev *indio_dev,
124 struct iio_chan_spec const *chan,
125 int *val,
126 int *val2,
127 long m)
128 {
129 int ret;
130 struct ad7476_state *st = iio_priv(indio_dev);
131 int scale_uv;
132
133 switch (m) {
134 case IIO_CHAN_INFO_RAW:
135 ret = iio_device_claim_direct_mode(indio_dev);
136 if (ret)
137 return ret;
138 ret = ad7476_scan_direct(st);
139 iio_device_release_direct_mode(indio_dev);
140
141 if (ret < 0)
142 return ret;
143 *val = (ret >> st->chip_info->channel[0].scan_type.shift) &
144 GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0);
145 return IIO_VAL_INT;
146 case IIO_CHAN_INFO_SCALE:
147 if (!st->chip_info->int_vref_uv) {
148 scale_uv = regulator_get_voltage(st->reg);
149 if (scale_uv < 0)
150 return scale_uv;
151 } else {
152 scale_uv = st->chip_info->int_vref_uv;
153 }
154 *val = scale_uv / 1000;
155 *val2 = chan->scan_type.realbits;
156 return IIO_VAL_FRACTIONAL_LOG2;
157 }
158 return -EINVAL;
159 }
160
161 #define _AD7476_CHAN(bits, _shift, _info_mask_sep) \
162 { \
163 .type = IIO_VOLTAGE, \
164 .indexed = 1, \
165 .info_mask_separate = _info_mask_sep, \
166 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
167 .scan_type = { \
168 .sign = 'u', \
169 .realbits = (bits), \
170 .storagebits = 16, \
171 .shift = (_shift), \
172 .endianness = IIO_BE, \
173 }, \
174 }
175
176 #define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
177 BIT(IIO_CHAN_INFO_RAW))
178 #define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \
179 BIT(IIO_CHAN_INFO_RAW))
180 #define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \
181 BIT(IIO_CHAN_INFO_RAW))
182 #define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0)
183 #define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \
184 BIT(IIO_CHAN_INFO_RAW))
185 #define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
186 BIT(IIO_CHAN_INFO_RAW))
187
188 static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
189 [ID_AD7091R] = {
190 .channel[0] = AD7091R_CHAN(12),
191 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
192 .convst_channel[0] = AD7091R_CONVST_CHAN(12),
193 .convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
194 .reset = ad7091_reset,
195 },
196 [ID_AD7276] = {
197 .channel[0] = AD7940_CHAN(12),
198 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
199 },
200 [ID_AD7277] = {
201 .channel[0] = AD7940_CHAN(10),
202 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
203 },
204 [ID_AD7278] = {
205 .channel[0] = AD7940_CHAN(8),
206 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
207 },
208 [ID_AD7466] = {
209 .channel[0] = AD7476_CHAN(12),
210 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
211 },
212 [ID_AD7467] = {
213 .channel[0] = AD7476_CHAN(10),
214 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
215 },
216 [ID_AD7468] = {
217 .channel[0] = AD7476_CHAN(8),
218 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
219 },
220 [ID_AD7495] = {
221 .channel[0] = AD7476_CHAN(12),
222 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
223 .int_vref_uv = 2500000,
224 },
225 [ID_AD7940] = {
226 .channel[0] = AD7940_CHAN(14),
227 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
228 },
229 [ID_ADC081S] = {
230 .channel[0] = ADC081S_CHAN(8),
231 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
232 },
233 [ID_ADC101S] = {
234 .channel[0] = ADC081S_CHAN(10),
235 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
236 },
237 [ID_ADC121S] = {
238 .channel[0] = ADC081S_CHAN(12),
239 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
240 },
241 [ID_ADS7866] = {
242 .channel[0] = ADS786X_CHAN(12),
243 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
244 },
245 [ID_ADS7867] = {
246 .channel[0] = ADS786X_CHAN(10),
247 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
248 },
249 [ID_ADS7868] = {
250 .channel[0] = ADS786X_CHAN(8),
251 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
252 },
253 };
254
255 static const struct iio_info ad7476_info = {
256 .read_raw = &ad7476_read_raw,
257 };
258
ad7476_reg_disable(void * data)259 static void ad7476_reg_disable(void *data)
260 {
261 struct ad7476_state *st = data;
262
263 regulator_disable(st->reg);
264 }
265
ad7476_probe(struct spi_device * spi)266 static int ad7476_probe(struct spi_device *spi)
267 {
268 struct ad7476_state *st;
269 struct iio_dev *indio_dev;
270 int ret;
271
272 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
273 if (!indio_dev)
274 return -ENOMEM;
275
276 st = iio_priv(indio_dev);
277 st->chip_info =
278 &ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data];
279
280 st->reg = devm_regulator_get(&spi->dev, "vcc");
281 if (IS_ERR(st->reg))
282 return PTR_ERR(st->reg);
283
284 ret = regulator_enable(st->reg);
285 if (ret)
286 return ret;
287
288 ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable,
289 st);
290 if (ret)
291 return ret;
292
293 st->convst_gpio = devm_gpiod_get_optional(&spi->dev,
294 "adi,conversion-start",
295 GPIOD_OUT_LOW);
296 if (IS_ERR(st->convst_gpio))
297 return PTR_ERR(st->convst_gpio);
298
299 spi_set_drvdata(spi, indio_dev);
300
301 st->spi = spi;
302
303 indio_dev->name = spi_get_device_id(spi)->name;
304 indio_dev->modes = INDIO_DIRECT_MODE;
305 indio_dev->channels = st->chip_info->channel;
306 indio_dev->num_channels = 2;
307 indio_dev->info = &ad7476_info;
308
309 if (st->convst_gpio)
310 indio_dev->channels = st->chip_info->convst_channel;
311 /* Setup default message */
312
313 st->xfer.rx_buf = &st->data;
314 st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8;
315
316 spi_message_init(&st->msg);
317 spi_message_add_tail(&st->xfer, &st->msg);
318
319 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
320 &ad7476_trigger_handler, NULL);
321 if (ret)
322 return ret;
323
324 if (st->chip_info->reset)
325 st->chip_info->reset(st);
326
327 return devm_iio_device_register(&spi->dev, indio_dev);
328 }
329
330 static const struct spi_device_id ad7476_id[] = {
331 {"ad7091", ID_AD7091R},
332 {"ad7091r", ID_AD7091R},
333 {"ad7273", ID_AD7277},
334 {"ad7274", ID_AD7276},
335 {"ad7276", ID_AD7276},
336 {"ad7277", ID_AD7277},
337 {"ad7278", ID_AD7278},
338 {"ad7466", ID_AD7466},
339 {"ad7467", ID_AD7467},
340 {"ad7468", ID_AD7468},
341 {"ad7475", ID_AD7466},
342 {"ad7476", ID_AD7466},
343 {"ad7476a", ID_AD7466},
344 {"ad7477", ID_AD7467},
345 {"ad7477a", ID_AD7467},
346 {"ad7478", ID_AD7468},
347 {"ad7478a", ID_AD7468},
348 {"ad7495", ID_AD7495},
349 {"ad7910", ID_AD7467},
350 {"ad7920", ID_AD7466},
351 {"ad7940", ID_AD7940},
352 {"adc081s", ID_ADC081S},
353 {"adc101s", ID_ADC101S},
354 {"adc121s", ID_ADC121S},
355 {"ads7866", ID_ADS7866},
356 {"ads7867", ID_ADS7867},
357 {"ads7868", ID_ADS7868},
358 {}
359 };
360 MODULE_DEVICE_TABLE(spi, ad7476_id);
361
362 static struct spi_driver ad7476_driver = {
363 .driver = {
364 .name = "ad7476",
365 },
366 .probe = ad7476_probe,
367 .id_table = ad7476_id,
368 };
369 module_spi_driver(ad7476_driver);
370
371 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
372 MODULE_DESCRIPTION("Analog Devices AD7476 and similar 1-channel ADCs");
373 MODULE_LICENSE("GPL v2");
374