1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * V4L2 Driver for PXA camera host
4 *
5 * Copyright (C) 2006, Sascha Hauer, Pengutronix
6 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
8 */
9
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/io.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/errno.h>
18 #include <linux/fs.h>
19 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/mm.h>
22 #include <linux/moduleparam.h>
23 #include <linux/of.h>
24 #include <linux/of_graph.h>
25 #include <linux/time.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/dmaengine.h>
31 #include <linux/dma/pxa-dma.h>
32
33 #include <media/v4l2-async.h>
34 #include <media/v4l2-clk.h>
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-ctrls.h>
37 #include <media/v4l2-device.h>
38 #include <media/v4l2-event.h>
39 #include <media/v4l2-ioctl.h>
40 #include <media/v4l2-fwnode.h>
41
42 #include <media/videobuf2-dma-sg.h>
43
44 #include <linux/videodev2.h>
45
46 #include <linux/platform_data/media/camera-pxa.h>
47
48 #define PXA_CAM_VERSION "0.0.6"
49 #define PXA_CAM_DRV_NAME "pxa27x-camera"
50
51 #define DEFAULT_WIDTH 640
52 #define DEFAULT_HEIGHT 480
53
54 /* Camera Interface */
55 #define CICR0 0x0000
56 #define CICR1 0x0004
57 #define CICR2 0x0008
58 #define CICR3 0x000C
59 #define CICR4 0x0010
60 #define CISR 0x0014
61 #define CIFR 0x0018
62 #define CITOR 0x001C
63 #define CIBR0 0x0028
64 #define CIBR1 0x0030
65 #define CIBR2 0x0038
66
67 #define CICR0_DMAEN (1UL << 31) /* DMA request enable */
68 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
69 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
70 #define CICR0_ENB (1 << 28) /* Camera interface enable */
71 #define CICR0_DIS (1 << 27) /* Camera interface disable */
72 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
73 #define CICR0_TOM (1 << 9) /* Time-out mask */
74 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
75 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
76 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
77 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
78 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
79 #define CICR0_CDM (1 << 3) /* Disable-done mask */
80 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
81 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
82 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
83
84 #define CICR1_TBIT (1UL << 31) /* Transparency bit */
85 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
86 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
87 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
88 #define CICR1_RGB_F (1 << 11) /* RGB format */
89 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
90 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
91 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
92 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
93 #define CICR1_DW (0x7 << 0) /* Data width mask */
94
95 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
96 wait count mask */
97 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
98 wait count mask */
99 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
100 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
101 wait count mask */
102 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
103 wait count mask */
104
105 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
106 wait count mask */
107 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
108 wait count mask */
109 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
110 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
111 wait count mask */
112 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
113
114 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
115 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
116 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
117 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
118 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
119 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
120 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
121 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
122
123 #define CISR_FTO (1 << 15) /* FIFO time-out */
124 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
125 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
126 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
127 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
128 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
129 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
130 #define CISR_EOL (1 << 8) /* End of line */
131 #define CISR_PAR_ERR (1 << 7) /* Parity error */
132 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
133 #define CISR_CDD (1 << 5) /* Camera interface disable done */
134 #define CISR_SOF (1 << 4) /* Start of frame */
135 #define CISR_EOF (1 << 3) /* End of frame */
136 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
137 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
138 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
139
140 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
141 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
142 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
143 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
144 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
145 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
146 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
147 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
148
149 #define CICR0_SIM_MP (0 << 24)
150 #define CICR0_SIM_SP (1 << 24)
151 #define CICR0_SIM_MS (2 << 24)
152 #define CICR0_SIM_EP (3 << 24)
153 #define CICR0_SIM_ES (4 << 24)
154
155 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
156 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
157 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
158 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
159 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
160
161 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
162 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
163 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
164 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
165 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
166
167 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
168 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
169 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
170 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
171
172 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
173 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
174 CICR0_EOFM | CICR0_FOM)
175
176 #define sensor_call(cam, o, f, args...) \
177 v4l2_subdev_call(cam->sensor, o, f, ##args)
178
179 /*
180 * Format handling
181 */
182
183 /**
184 * enum pxa_mbus_packing - data packing types on the media-bus
185 * @PXA_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
186 * sample represents one pixel
187 * @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
188 * possibly incomplete byte high bits are padding
189 * @PXA_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
190 * to 16 bits
191 */
192 enum pxa_mbus_packing {
193 PXA_MBUS_PACKING_NONE,
194 PXA_MBUS_PACKING_2X8_PADHI,
195 PXA_MBUS_PACKING_EXTEND16,
196 };
197
198 /**
199 * enum pxa_mbus_order - sample order on the media bus
200 * @PXA_MBUS_ORDER_LE: least significant sample first
201 * @PXA_MBUS_ORDER_BE: most significant sample first
202 */
203 enum pxa_mbus_order {
204 PXA_MBUS_ORDER_LE,
205 PXA_MBUS_ORDER_BE,
206 };
207
208 /**
209 * enum pxa_mbus_layout - planes layout in memory
210 * @PXA_MBUS_LAYOUT_PACKED: color components packed
211 * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2)
212 * @PXA_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a
213 * chroma plane (C plane is half the size
214 * of Y plane)
215 * @PXA_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a
216 * chroma plane (C plane is the same size
217 * as Y plane)
218 */
219 enum pxa_mbus_layout {
220 PXA_MBUS_LAYOUT_PACKED = 0,
221 PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
222 PXA_MBUS_LAYOUT_PLANAR_2Y_C,
223 PXA_MBUS_LAYOUT_PLANAR_Y_C,
224 };
225
226 /**
227 * struct pxa_mbus_pixelfmt - Data format on the media bus
228 * @name: Name of the format
229 * @fourcc: Fourcc code, that will be obtained if the data is
230 * stored in memory in the following way:
231 * @packing: Type of sample-packing, that has to be used
232 * @order: Sample order when storing in memory
233 * @layout: Planes layout in memory
234 * @bits_per_sample: How many bits the bridge has to sample
235 */
236 struct pxa_mbus_pixelfmt {
237 const char *name;
238 u32 fourcc;
239 enum pxa_mbus_packing packing;
240 enum pxa_mbus_order order;
241 enum pxa_mbus_layout layout;
242 u8 bits_per_sample;
243 };
244
245 /**
246 * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
247 * @code: mediabus pixel-code
248 * @fmt: pixel format description
249 */
250 struct pxa_mbus_lookup {
251 u32 code;
252 struct pxa_mbus_pixelfmt fmt;
253 };
254
255 static const struct pxa_mbus_lookup mbus_fmt[] = {
256 {
257 .code = MEDIA_BUS_FMT_YUYV8_2X8,
258 .fmt = {
259 .fourcc = V4L2_PIX_FMT_YUYV,
260 .name = "YUYV",
261 .bits_per_sample = 8,
262 .packing = PXA_MBUS_PACKING_2X8_PADHI,
263 .order = PXA_MBUS_ORDER_LE,
264 .layout = PXA_MBUS_LAYOUT_PACKED,
265 },
266 }, {
267 .code = MEDIA_BUS_FMT_YVYU8_2X8,
268 .fmt = {
269 .fourcc = V4L2_PIX_FMT_YVYU,
270 .name = "YVYU",
271 .bits_per_sample = 8,
272 .packing = PXA_MBUS_PACKING_2X8_PADHI,
273 .order = PXA_MBUS_ORDER_LE,
274 .layout = PXA_MBUS_LAYOUT_PACKED,
275 },
276 }, {
277 .code = MEDIA_BUS_FMT_UYVY8_2X8,
278 .fmt = {
279 .fourcc = V4L2_PIX_FMT_UYVY,
280 .name = "UYVY",
281 .bits_per_sample = 8,
282 .packing = PXA_MBUS_PACKING_2X8_PADHI,
283 .order = PXA_MBUS_ORDER_LE,
284 .layout = PXA_MBUS_LAYOUT_PACKED,
285 },
286 }, {
287 .code = MEDIA_BUS_FMT_VYUY8_2X8,
288 .fmt = {
289 .fourcc = V4L2_PIX_FMT_VYUY,
290 .name = "VYUY",
291 .bits_per_sample = 8,
292 .packing = PXA_MBUS_PACKING_2X8_PADHI,
293 .order = PXA_MBUS_ORDER_LE,
294 .layout = PXA_MBUS_LAYOUT_PACKED,
295 },
296 }, {
297 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
298 .fmt = {
299 .fourcc = V4L2_PIX_FMT_RGB555,
300 .name = "RGB555",
301 .bits_per_sample = 8,
302 .packing = PXA_MBUS_PACKING_2X8_PADHI,
303 .order = PXA_MBUS_ORDER_LE,
304 .layout = PXA_MBUS_LAYOUT_PACKED,
305 },
306 }, {
307 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
308 .fmt = {
309 .fourcc = V4L2_PIX_FMT_RGB555X,
310 .name = "RGB555X",
311 .bits_per_sample = 8,
312 .packing = PXA_MBUS_PACKING_2X8_PADHI,
313 .order = PXA_MBUS_ORDER_BE,
314 .layout = PXA_MBUS_LAYOUT_PACKED,
315 },
316 }, {
317 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
318 .fmt = {
319 .fourcc = V4L2_PIX_FMT_RGB565,
320 .name = "RGB565",
321 .bits_per_sample = 8,
322 .packing = PXA_MBUS_PACKING_2X8_PADHI,
323 .order = PXA_MBUS_ORDER_LE,
324 .layout = PXA_MBUS_LAYOUT_PACKED,
325 },
326 }, {
327 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
328 .fmt = {
329 .fourcc = V4L2_PIX_FMT_RGB565X,
330 .name = "RGB565X",
331 .bits_per_sample = 8,
332 .packing = PXA_MBUS_PACKING_2X8_PADHI,
333 .order = PXA_MBUS_ORDER_BE,
334 .layout = PXA_MBUS_LAYOUT_PACKED,
335 },
336 }, {
337 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
338 .fmt = {
339 .fourcc = V4L2_PIX_FMT_SBGGR8,
340 .name = "Bayer 8 BGGR",
341 .bits_per_sample = 8,
342 .packing = PXA_MBUS_PACKING_NONE,
343 .order = PXA_MBUS_ORDER_LE,
344 .layout = PXA_MBUS_LAYOUT_PACKED,
345 },
346 }, {
347 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
348 .fmt = {
349 .fourcc = V4L2_PIX_FMT_SGBRG8,
350 .name = "Bayer 8 GBRG",
351 .bits_per_sample = 8,
352 .packing = PXA_MBUS_PACKING_NONE,
353 .order = PXA_MBUS_ORDER_LE,
354 .layout = PXA_MBUS_LAYOUT_PACKED,
355 },
356 }, {
357 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
358 .fmt = {
359 .fourcc = V4L2_PIX_FMT_SGRBG8,
360 .name = "Bayer 8 GRBG",
361 .bits_per_sample = 8,
362 .packing = PXA_MBUS_PACKING_NONE,
363 .order = PXA_MBUS_ORDER_LE,
364 .layout = PXA_MBUS_LAYOUT_PACKED,
365 },
366 }, {
367 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
368 .fmt = {
369 .fourcc = V4L2_PIX_FMT_SRGGB8,
370 .name = "Bayer 8 RGGB",
371 .bits_per_sample = 8,
372 .packing = PXA_MBUS_PACKING_NONE,
373 .order = PXA_MBUS_ORDER_LE,
374 .layout = PXA_MBUS_LAYOUT_PACKED,
375 },
376 }, {
377 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
378 .fmt = {
379 .fourcc = V4L2_PIX_FMT_SBGGR10,
380 .name = "Bayer 10 BGGR",
381 .bits_per_sample = 10,
382 .packing = PXA_MBUS_PACKING_EXTEND16,
383 .order = PXA_MBUS_ORDER_LE,
384 .layout = PXA_MBUS_LAYOUT_PACKED,
385 },
386 }, {
387 .code = MEDIA_BUS_FMT_Y8_1X8,
388 .fmt = {
389 .fourcc = V4L2_PIX_FMT_GREY,
390 .name = "Grey",
391 .bits_per_sample = 8,
392 .packing = PXA_MBUS_PACKING_NONE,
393 .order = PXA_MBUS_ORDER_LE,
394 .layout = PXA_MBUS_LAYOUT_PACKED,
395 },
396 }, {
397 .code = MEDIA_BUS_FMT_Y10_1X10,
398 .fmt = {
399 .fourcc = V4L2_PIX_FMT_Y10,
400 .name = "Grey 10bit",
401 .bits_per_sample = 10,
402 .packing = PXA_MBUS_PACKING_EXTEND16,
403 .order = PXA_MBUS_ORDER_LE,
404 .layout = PXA_MBUS_LAYOUT_PACKED,
405 },
406 }, {
407 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
408 .fmt = {
409 .fourcc = V4L2_PIX_FMT_SBGGR10,
410 .name = "Bayer 10 BGGR",
411 .bits_per_sample = 8,
412 .packing = PXA_MBUS_PACKING_2X8_PADHI,
413 .order = PXA_MBUS_ORDER_LE,
414 .layout = PXA_MBUS_LAYOUT_PACKED,
415 },
416 }, {
417 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
418 .fmt = {
419 .fourcc = V4L2_PIX_FMT_SBGGR10,
420 .name = "Bayer 10 BGGR",
421 .bits_per_sample = 8,
422 .packing = PXA_MBUS_PACKING_2X8_PADHI,
423 .order = PXA_MBUS_ORDER_BE,
424 .layout = PXA_MBUS_LAYOUT_PACKED,
425 },
426 }, {
427 .code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
428 .fmt = {
429 .fourcc = V4L2_PIX_FMT_RGB444,
430 .name = "RGB444",
431 .bits_per_sample = 8,
432 .packing = PXA_MBUS_PACKING_2X8_PADHI,
433 .order = PXA_MBUS_ORDER_BE,
434 .layout = PXA_MBUS_LAYOUT_PACKED,
435 },
436 }, {
437 .code = MEDIA_BUS_FMT_UYVY8_1X16,
438 .fmt = {
439 .fourcc = V4L2_PIX_FMT_UYVY,
440 .name = "UYVY 16bit",
441 .bits_per_sample = 16,
442 .packing = PXA_MBUS_PACKING_EXTEND16,
443 .order = PXA_MBUS_ORDER_LE,
444 .layout = PXA_MBUS_LAYOUT_PACKED,
445 },
446 }, {
447 .code = MEDIA_BUS_FMT_VYUY8_1X16,
448 .fmt = {
449 .fourcc = V4L2_PIX_FMT_VYUY,
450 .name = "VYUY 16bit",
451 .bits_per_sample = 16,
452 .packing = PXA_MBUS_PACKING_EXTEND16,
453 .order = PXA_MBUS_ORDER_LE,
454 .layout = PXA_MBUS_LAYOUT_PACKED,
455 },
456 }, {
457 .code = MEDIA_BUS_FMT_YUYV8_1X16,
458 .fmt = {
459 .fourcc = V4L2_PIX_FMT_YUYV,
460 .name = "YUYV 16bit",
461 .bits_per_sample = 16,
462 .packing = PXA_MBUS_PACKING_EXTEND16,
463 .order = PXA_MBUS_ORDER_LE,
464 .layout = PXA_MBUS_LAYOUT_PACKED,
465 },
466 }, {
467 .code = MEDIA_BUS_FMT_YVYU8_1X16,
468 .fmt = {
469 .fourcc = V4L2_PIX_FMT_YVYU,
470 .name = "YVYU 16bit",
471 .bits_per_sample = 16,
472 .packing = PXA_MBUS_PACKING_EXTEND16,
473 .order = PXA_MBUS_ORDER_LE,
474 .layout = PXA_MBUS_LAYOUT_PACKED,
475 },
476 }, {
477 .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
478 .fmt = {
479 .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8,
480 .name = "Bayer 10 BGGR DPCM 8",
481 .bits_per_sample = 8,
482 .packing = PXA_MBUS_PACKING_NONE,
483 .order = PXA_MBUS_ORDER_LE,
484 .layout = PXA_MBUS_LAYOUT_PACKED,
485 },
486 }, {
487 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
488 .fmt = {
489 .fourcc = V4L2_PIX_FMT_SGBRG10,
490 .name = "Bayer 10 GBRG",
491 .bits_per_sample = 10,
492 .packing = PXA_MBUS_PACKING_EXTEND16,
493 .order = PXA_MBUS_ORDER_LE,
494 .layout = PXA_MBUS_LAYOUT_PACKED,
495 },
496 }, {
497 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
498 .fmt = {
499 .fourcc = V4L2_PIX_FMT_SGRBG10,
500 .name = "Bayer 10 GRBG",
501 .bits_per_sample = 10,
502 .packing = PXA_MBUS_PACKING_EXTEND16,
503 .order = PXA_MBUS_ORDER_LE,
504 .layout = PXA_MBUS_LAYOUT_PACKED,
505 },
506 }, {
507 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
508 .fmt = {
509 .fourcc = V4L2_PIX_FMT_SRGGB10,
510 .name = "Bayer 10 RGGB",
511 .bits_per_sample = 10,
512 .packing = PXA_MBUS_PACKING_EXTEND16,
513 .order = PXA_MBUS_ORDER_LE,
514 .layout = PXA_MBUS_LAYOUT_PACKED,
515 },
516 }, {
517 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
518 .fmt = {
519 .fourcc = V4L2_PIX_FMT_SBGGR12,
520 .name = "Bayer 12 BGGR",
521 .bits_per_sample = 12,
522 .packing = PXA_MBUS_PACKING_EXTEND16,
523 .order = PXA_MBUS_ORDER_LE,
524 .layout = PXA_MBUS_LAYOUT_PACKED,
525 },
526 }, {
527 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
528 .fmt = {
529 .fourcc = V4L2_PIX_FMT_SGBRG12,
530 .name = "Bayer 12 GBRG",
531 .bits_per_sample = 12,
532 .packing = PXA_MBUS_PACKING_EXTEND16,
533 .order = PXA_MBUS_ORDER_LE,
534 .layout = PXA_MBUS_LAYOUT_PACKED,
535 },
536 }, {
537 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
538 .fmt = {
539 .fourcc = V4L2_PIX_FMT_SGRBG12,
540 .name = "Bayer 12 GRBG",
541 .bits_per_sample = 12,
542 .packing = PXA_MBUS_PACKING_EXTEND16,
543 .order = PXA_MBUS_ORDER_LE,
544 .layout = PXA_MBUS_LAYOUT_PACKED,
545 },
546 }, {
547 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
548 .fmt = {
549 .fourcc = V4L2_PIX_FMT_SRGGB12,
550 .name = "Bayer 12 RGGB",
551 .bits_per_sample = 12,
552 .packing = PXA_MBUS_PACKING_EXTEND16,
553 .order = PXA_MBUS_ORDER_LE,
554 .layout = PXA_MBUS_LAYOUT_PACKED,
555 },
556 },
557 };
558
pxa_mbus_bytes_per_line(u32 width,const struct pxa_mbus_pixelfmt * mf)559 static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
560 {
561 if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
562 return width * mf->bits_per_sample / 8;
563
564 switch (mf->packing) {
565 case PXA_MBUS_PACKING_NONE:
566 return width * mf->bits_per_sample / 8;
567 case PXA_MBUS_PACKING_2X8_PADHI:
568 case PXA_MBUS_PACKING_EXTEND16:
569 return width * 2;
570 }
571 return -EINVAL;
572 }
573
pxa_mbus_image_size(const struct pxa_mbus_pixelfmt * mf,u32 bytes_per_line,u32 height)574 static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
575 u32 bytes_per_line, u32 height)
576 {
577 if (mf->layout == PXA_MBUS_LAYOUT_PACKED)
578 return bytes_per_line * height;
579
580 switch (mf->packing) {
581 case PXA_MBUS_PACKING_2X8_PADHI:
582 return bytes_per_line * height * 2;
583 default:
584 return -EINVAL;
585 }
586 }
587
pxa_mbus_find_fmtdesc(u32 code,const struct pxa_mbus_lookup * lookup,int n)588 static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
589 u32 code,
590 const struct pxa_mbus_lookup *lookup,
591 int n)
592 {
593 int i;
594
595 for (i = 0; i < n; i++)
596 if (lookup[i].code == code)
597 return &lookup[i].fmt;
598
599 return NULL;
600 }
601
pxa_mbus_get_fmtdesc(u32 code)602 static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
603 u32 code)
604 {
605 return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
606 }
607
608 /**
609 * struct pxa_camera_format_xlate - match between host and sensor formats
610 * @code: code of a sensor provided format
611 * @host_fmt: host format after host translation from code
612 *
613 * Host and sensor translation structure. Used in table of host and sensor
614 * formats matchings in pxa_camera_device. A host can override the generic list
615 * generation by implementing get_formats(), and use it for format checks and
616 * format setup.
617 */
618 struct pxa_camera_format_xlate {
619 u32 code;
620 const struct pxa_mbus_pixelfmt *host_fmt;
621 };
622
623 /*
624 * Structures
625 */
626 enum pxa_camera_active_dma {
627 DMA_Y = 0x1,
628 DMA_U = 0x2,
629 DMA_V = 0x4,
630 };
631
632 /* buffer for one video frame */
633 struct pxa_buffer {
634 /* common v4l buffer stuff -- must be first */
635 struct vb2_v4l2_buffer vbuf;
636 struct list_head queue;
637 u32 code;
638 int nb_planes;
639 /* our descriptor lists for Y, U and V channels */
640 struct dma_async_tx_descriptor *descs[3];
641 dma_cookie_t cookie[3];
642 struct scatterlist *sg[3];
643 int sg_len[3];
644 size_t plane_sizes[3];
645 int inwork;
646 enum pxa_camera_active_dma active_dma;
647 };
648
649 struct pxa_camera_dev {
650 struct v4l2_device v4l2_dev;
651 struct video_device vdev;
652 struct v4l2_async_notifier notifier;
653 struct vb2_queue vb2_vq;
654 struct v4l2_subdev *sensor;
655 struct pxa_camera_format_xlate *user_formats;
656 const struct pxa_camera_format_xlate *current_fmt;
657 struct v4l2_pix_format current_pix;
658
659 struct v4l2_async_subdev asd;
660
661 /*
662 * PXA27x is only supposed to handle one camera on its Quick Capture
663 * interface. If anyone ever builds hardware to enable more than
664 * one camera, they will have to modify this driver too
665 */
666 struct clk *clk;
667
668 unsigned int irq;
669 void __iomem *base;
670
671 int channels;
672 struct dma_chan *dma_chans[3];
673
674 struct pxacamera_platform_data *pdata;
675 struct resource *res;
676 unsigned long platform_flags;
677 unsigned long ciclk;
678 unsigned long mclk;
679 u32 mclk_divisor;
680 struct v4l2_clk *mclk_clk;
681 u16 width_flags; /* max 10 bits */
682
683 struct list_head capture;
684
685 spinlock_t lock;
686 struct mutex mlock;
687 unsigned int buf_sequence;
688
689 struct pxa_buffer *active;
690 struct tasklet_struct task_eof;
691
692 u32 save_cicr[5];
693 };
694
695 struct pxa_cam {
696 unsigned long flags;
697 };
698
699 static const char *pxa_cam_driver_description = "PXA_Camera";
700
701 /*
702 * Format translation functions
703 */
704 static const struct pxa_camera_format_xlate
pxa_mbus_xlate_by_fourcc(struct pxa_camera_format_xlate * user_formats,unsigned int fourcc)705 *pxa_mbus_xlate_by_fourcc(struct pxa_camera_format_xlate *user_formats,
706 unsigned int fourcc)
707 {
708 unsigned int i;
709
710 for (i = 0; user_formats[i].code; i++)
711 if (user_formats[i].host_fmt->fourcc == fourcc)
712 return user_formats + i;
713 return NULL;
714 }
715
pxa_mbus_build_fmts_xlate(struct v4l2_device * v4l2_dev,struct v4l2_subdev * subdev,int (* get_formats)(struct v4l2_device *,unsigned int,struct pxa_camera_format_xlate * xlate))716 static struct pxa_camera_format_xlate *pxa_mbus_build_fmts_xlate(
717 struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
718 int (*get_formats)(struct v4l2_device *, unsigned int,
719 struct pxa_camera_format_xlate *xlate))
720 {
721 unsigned int i, fmts = 0, raw_fmts = 0;
722 int ret;
723 struct v4l2_subdev_mbus_code_enum code = {
724 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
725 };
726 struct pxa_camera_format_xlate *user_formats;
727
728 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
729 raw_fmts++;
730 code.index++;
731 }
732
733 /*
734 * First pass - only count formats this host-sensor
735 * configuration can provide
736 */
737 for (i = 0; i < raw_fmts; i++) {
738 ret = get_formats(v4l2_dev, i, NULL);
739 if (ret < 0)
740 return ERR_PTR(ret);
741 fmts += ret;
742 }
743
744 if (!fmts)
745 return ERR_PTR(-ENXIO);
746
747 user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
748 if (!user_formats)
749 return ERR_PTR(-ENOMEM);
750
751 /* Second pass - actually fill data formats */
752 fmts = 0;
753 for (i = 0; i < raw_fmts; i++) {
754 ret = get_formats(v4l2_dev, i, user_formats + fmts);
755 if (ret < 0)
756 goto egfmt;
757 fmts += ret;
758 }
759 user_formats[fmts].code = 0;
760
761 return user_formats;
762 egfmt:
763 kfree(user_formats);
764 return ERR_PTR(ret);
765 }
766
767 /*
768 * Videobuf operations
769 */
vb2_to_pxa_buffer(struct vb2_buffer * vb)770 static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
771 {
772 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
773
774 return container_of(vbuf, struct pxa_buffer, vbuf);
775 }
776
pcdev_to_dev(struct pxa_camera_dev * pcdev)777 static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
778 {
779 return pcdev->v4l2_dev.dev;
780 }
781
v4l2_dev_to_pcdev(struct v4l2_device * v4l2_dev)782 static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
783 {
784 return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
785 }
786
787 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
788 enum pxa_camera_active_dma act_dma);
789
pxa_camera_dma_irq_y(void * data)790 static void pxa_camera_dma_irq_y(void *data)
791 {
792 struct pxa_camera_dev *pcdev = data;
793
794 pxa_camera_dma_irq(pcdev, DMA_Y);
795 }
796
pxa_camera_dma_irq_u(void * data)797 static void pxa_camera_dma_irq_u(void *data)
798 {
799 struct pxa_camera_dev *pcdev = data;
800
801 pxa_camera_dma_irq(pcdev, DMA_U);
802 }
803
pxa_camera_dma_irq_v(void * data)804 static void pxa_camera_dma_irq_v(void *data)
805 {
806 struct pxa_camera_dev *pcdev = data;
807
808 pxa_camera_dma_irq(pcdev, DMA_V);
809 }
810
811 /**
812 * pxa_init_dma_channel - init dma descriptors
813 * @pcdev: pxa camera device
814 * @buf: pxa camera buffer
815 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
816 * @sg: dma scatter list
817 * @sglen: dma scatter list length
818 *
819 * Prepares the pxa dma descriptors to transfer one camera channel.
820 *
821 * Returns 0 if success or -ENOMEM if no memory is available
822 */
pxa_init_dma_channel(struct pxa_camera_dev * pcdev,struct pxa_buffer * buf,int channel,struct scatterlist * sg,int sglen)823 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
824 struct pxa_buffer *buf, int channel,
825 struct scatterlist *sg, int sglen)
826 {
827 struct dma_chan *dma_chan = pcdev->dma_chans[channel];
828 struct dma_async_tx_descriptor *tx;
829
830 tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
831 DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
832 if (!tx) {
833 dev_err(pcdev_to_dev(pcdev),
834 "dmaengine_prep_slave_sg failed\n");
835 goto fail;
836 }
837
838 tx->callback_param = pcdev;
839 switch (channel) {
840 case 0:
841 tx->callback = pxa_camera_dma_irq_y;
842 break;
843 case 1:
844 tx->callback = pxa_camera_dma_irq_u;
845 break;
846 case 2:
847 tx->callback = pxa_camera_dma_irq_v;
848 break;
849 }
850
851 buf->descs[channel] = tx;
852 return 0;
853 fail:
854 dev_dbg(pcdev_to_dev(pcdev),
855 "%s (vb=%p) dma_tx=%p\n",
856 __func__, buf, tx);
857
858 return -ENOMEM;
859 }
860
pxa_videobuf_set_actdma(struct pxa_camera_dev * pcdev,struct pxa_buffer * buf)861 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
862 struct pxa_buffer *buf)
863 {
864 buf->active_dma = DMA_Y;
865 if (buf->nb_planes == 3)
866 buf->active_dma |= DMA_U | DMA_V;
867 }
868
869 /**
870 * pxa_dma_start_channels - start DMA channel for active buffer
871 * @pcdev: pxa camera device
872 *
873 * Initialize DMA channels to the beginning of the active video buffer, and
874 * start these channels.
875 */
pxa_dma_start_channels(struct pxa_camera_dev * pcdev)876 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
877 {
878 int i;
879
880 for (i = 0; i < pcdev->channels; i++) {
881 dev_dbg(pcdev_to_dev(pcdev),
882 "%s (channel=%d)\n", __func__, i);
883 dma_async_issue_pending(pcdev->dma_chans[i]);
884 }
885 }
886
pxa_dma_stop_channels(struct pxa_camera_dev * pcdev)887 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
888 {
889 int i;
890
891 for (i = 0; i < pcdev->channels; i++) {
892 dev_dbg(pcdev_to_dev(pcdev),
893 "%s (channel=%d)\n", __func__, i);
894 dmaengine_terminate_all(pcdev->dma_chans[i]);
895 }
896 }
897
pxa_dma_add_tail_buf(struct pxa_camera_dev * pcdev,struct pxa_buffer * buf)898 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
899 struct pxa_buffer *buf)
900 {
901 int i;
902
903 for (i = 0; i < pcdev->channels; i++) {
904 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
905 dev_dbg(pcdev_to_dev(pcdev),
906 "%s (channel=%d) : submit vb=%p cookie=%d\n",
907 __func__, i, buf, buf->descs[i]->cookie);
908 }
909 }
910
911 /**
912 * pxa_camera_start_capture - start video capturing
913 * @pcdev: camera device
914 *
915 * Launch capturing. DMA channels should not be active yet. They should get
916 * activated at the end of frame interrupt, to capture only whole frames, and
917 * never begin the capture of a partial frame.
918 */
pxa_camera_start_capture(struct pxa_camera_dev * pcdev)919 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
920 {
921 unsigned long cicr0;
922
923 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
924 __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
925 /* Enable End-Of-Frame Interrupt */
926 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
927 cicr0 &= ~CICR0_EOFM;
928 __raw_writel(cicr0, pcdev->base + CICR0);
929 }
930
pxa_camera_stop_capture(struct pxa_camera_dev * pcdev)931 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
932 {
933 unsigned long cicr0;
934
935 pxa_dma_stop_channels(pcdev);
936
937 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
938 __raw_writel(cicr0, pcdev->base + CICR0);
939
940 pcdev->active = NULL;
941 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
942 }
943
pxa_camera_wakeup(struct pxa_camera_dev * pcdev,struct pxa_buffer * buf,enum vb2_buffer_state state)944 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
945 struct pxa_buffer *buf,
946 enum vb2_buffer_state state)
947 {
948 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
949 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
950
951 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
952 list_del_init(&buf->queue);
953 vb->timestamp = ktime_get_ns();
954 vbuf->sequence = pcdev->buf_sequence++;
955 vbuf->field = V4L2_FIELD_NONE;
956 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
957 dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
958 __func__, buf);
959
960 if (list_empty(&pcdev->capture)) {
961 pxa_camera_stop_capture(pcdev);
962 return;
963 }
964
965 pcdev->active = list_entry(pcdev->capture.next,
966 struct pxa_buffer, queue);
967 }
968
969 /**
970 * pxa_camera_check_link_miss - check missed DMA linking
971 * @pcdev: camera device
972 * @last_submitted: an opaque DMA cookie for last submitted
973 * @last_issued: an opaque DMA cookie for last issued
974 *
975 * The DMA chaining is done with DMA running. This means a tiny temporal window
976 * remains, where a buffer is queued on the chain, while the chain is already
977 * stopped. This means the tailed buffer would never be transferred by DMA.
978 * This function restarts the capture for this corner case, where :
979 * - DADR() == DADDR_STOP
980 * - a videobuffer is queued on the pcdev->capture list
981 *
982 * Please check the "DMA hot chaining timeslice issue" in
983 * Documentation/driver-api/media/drivers/pxa_camera.rst
984 *
985 * Context: should only be called within the dma irq handler
986 */
pxa_camera_check_link_miss(struct pxa_camera_dev * pcdev,dma_cookie_t last_submitted,dma_cookie_t last_issued)987 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
988 dma_cookie_t last_submitted,
989 dma_cookie_t last_issued)
990 {
991 bool is_dma_stopped = last_submitted != last_issued;
992
993 dev_dbg(pcdev_to_dev(pcdev),
994 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
995 __func__, pcdev->active, is_dma_stopped);
996
997 if (pcdev->active && is_dma_stopped)
998 pxa_camera_start_capture(pcdev);
999 }
1000
pxa_camera_dma_irq(struct pxa_camera_dev * pcdev,enum pxa_camera_active_dma act_dma)1001 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
1002 enum pxa_camera_active_dma act_dma)
1003 {
1004 struct pxa_buffer *buf, *last_buf;
1005 unsigned long flags;
1006 u32 camera_status, overrun;
1007 int chan;
1008 enum dma_status last_status;
1009 dma_cookie_t last_issued;
1010
1011 spin_lock_irqsave(&pcdev->lock, flags);
1012
1013 camera_status = __raw_readl(pcdev->base + CISR);
1014 dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1015 camera_status, act_dma);
1016 overrun = CISR_IFO_0;
1017 if (pcdev->channels == 3)
1018 overrun |= CISR_IFO_1 | CISR_IFO_2;
1019
1020 /*
1021 * pcdev->active should not be NULL in DMA irq handler.
1022 *
1023 * But there is one corner case : if capture was stopped due to an
1024 * overrun of channel 1, and at that same channel 2 was completed.
1025 *
1026 * When handling the overrun in DMA irq for channel 1, we'll stop the
1027 * capture and restart it (and thus set pcdev->active to NULL). But the
1028 * DMA irq handler will already be pending for channel 2. So on entering
1029 * the DMA irq handler for channel 2 there will be no active buffer, yet
1030 * that is normal.
1031 */
1032 if (!pcdev->active)
1033 goto out;
1034
1035 buf = pcdev->active;
1036 WARN_ON(buf->inwork || list_empty(&buf->queue));
1037
1038 /*
1039 * It's normal if the last frame creates an overrun, as there
1040 * are no more DMA descriptors to fetch from QCI fifos
1041 */
1042 switch (act_dma) {
1043 case DMA_U:
1044 chan = 1;
1045 break;
1046 case DMA_V:
1047 chan = 2;
1048 break;
1049 default:
1050 chan = 0;
1051 break;
1052 }
1053 last_buf = list_entry(pcdev->capture.prev,
1054 struct pxa_buffer, queue);
1055 last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
1056 last_buf->cookie[chan],
1057 NULL, &last_issued);
1058 if (camera_status & overrun &&
1059 last_status != DMA_COMPLETE) {
1060 dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1061 camera_status);
1062 pxa_camera_stop_capture(pcdev);
1063 list_for_each_entry(buf, &pcdev->capture, queue)
1064 pxa_dma_add_tail_buf(pcdev, buf);
1065 pxa_camera_start_capture(pcdev);
1066 goto out;
1067 }
1068 buf->active_dma &= ~act_dma;
1069 if (!buf->active_dma) {
1070 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1071 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
1072 last_issued);
1073 }
1074
1075 out:
1076 spin_unlock_irqrestore(&pcdev->lock, flags);
1077 }
1078
mclk_get_divisor(struct platform_device * pdev,struct pxa_camera_dev * pcdev)1079 static u32 mclk_get_divisor(struct platform_device *pdev,
1080 struct pxa_camera_dev *pcdev)
1081 {
1082 unsigned long mclk = pcdev->mclk;
1083 u32 div;
1084 unsigned long lcdclk;
1085
1086 lcdclk = clk_get_rate(pcdev->clk);
1087 pcdev->ciclk = lcdclk;
1088
1089 /* mclk <= ciclk / 4 (27.4.2) */
1090 if (mclk > lcdclk / 4) {
1091 mclk = lcdclk / 4;
1092 dev_warn(&pdev->dev,
1093 "Limiting master clock to %lu\n", mclk);
1094 }
1095
1096 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
1097 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1098
1099 /* If we're not supplying MCLK, leave it at 0 */
1100 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1101 pcdev->mclk = lcdclk / (2 * (div + 1));
1102
1103 dev_dbg(&pdev->dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
1104 lcdclk, mclk, div);
1105
1106 return div;
1107 }
1108
recalculate_fifo_timeout(struct pxa_camera_dev * pcdev,unsigned long pclk)1109 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
1110 unsigned long pclk)
1111 {
1112 /* We want a timeout > 1 pixel time, not ">=" */
1113 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
1114
1115 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
1116 }
1117
pxa_camera_activate(struct pxa_camera_dev * pcdev)1118 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1119 {
1120 u32 cicr4 = 0;
1121
1122 /* disable all interrupts */
1123 __raw_writel(0x3ff, pcdev->base + CICR0);
1124
1125 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1126 cicr4 |= CICR4_PCLK_EN;
1127 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1128 cicr4 |= CICR4_MCLK_EN;
1129 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1130 cicr4 |= CICR4_PCP;
1131 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1132 cicr4 |= CICR4_HSP;
1133 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1134 cicr4 |= CICR4_VSP;
1135
1136 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
1137
1138 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1139 /* Initialise the timeout under the assumption pclk = mclk */
1140 recalculate_fifo_timeout(pcdev, pcdev->mclk);
1141 else
1142 /* "Safe default" - 13MHz */
1143 recalculate_fifo_timeout(pcdev, 13000000);
1144
1145 clk_prepare_enable(pcdev->clk);
1146 }
1147
pxa_camera_deactivate(struct pxa_camera_dev * pcdev)1148 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1149 {
1150 clk_disable_unprepare(pcdev->clk);
1151 }
1152
pxa_camera_eof(struct tasklet_struct * t)1153 static void pxa_camera_eof(struct tasklet_struct *t)
1154 {
1155 struct pxa_camera_dev *pcdev = from_tasklet(pcdev, t, task_eof);
1156 unsigned long cifr;
1157 struct pxa_buffer *buf;
1158
1159 dev_dbg(pcdev_to_dev(pcdev),
1160 "Camera interrupt status 0x%x\n",
1161 __raw_readl(pcdev->base + CISR));
1162
1163 /* Reset the FIFOs */
1164 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1165 __raw_writel(cifr, pcdev->base + CIFR);
1166
1167 pcdev->active = list_first_entry(&pcdev->capture,
1168 struct pxa_buffer, queue);
1169 buf = pcdev->active;
1170 pxa_videobuf_set_actdma(pcdev, buf);
1171
1172 pxa_dma_start_channels(pcdev);
1173 }
1174
pxa_camera_irq(int irq,void * data)1175 static irqreturn_t pxa_camera_irq(int irq, void *data)
1176 {
1177 struct pxa_camera_dev *pcdev = data;
1178 unsigned long status, cicr0;
1179
1180 status = __raw_readl(pcdev->base + CISR);
1181 dev_dbg(pcdev_to_dev(pcdev),
1182 "Camera interrupt status 0x%lx\n", status);
1183
1184 if (!status)
1185 return IRQ_NONE;
1186
1187 __raw_writel(status, pcdev->base + CISR);
1188
1189 if (status & CISR_EOF) {
1190 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
1191 __raw_writel(cicr0, pcdev->base + CICR0);
1192 tasklet_schedule(&pcdev->task_eof);
1193 }
1194
1195 return IRQ_HANDLED;
1196 }
1197
pxa_camera_setup_cicr(struct pxa_camera_dev * pcdev,unsigned long flags,__u32 pixfmt)1198 static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1199 unsigned long flags, __u32 pixfmt)
1200 {
1201 unsigned long dw, bpp;
1202 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1203 int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1204
1205 if (ret < 0)
1206 y_skip_top = 0;
1207
1208 /*
1209 * Datawidth is now guaranteed to be equal to one of the three values.
1210 * We fix bit-per-pixel equal to data-width...
1211 */
1212 switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1213 case 10:
1214 dw = 4;
1215 bpp = 0x40;
1216 break;
1217 case 9:
1218 dw = 3;
1219 bpp = 0x20;
1220 break;
1221 default:
1222 /*
1223 * Actually it can only be 8 now,
1224 * default is just to silence compiler warnings
1225 */
1226 case 8:
1227 dw = 2;
1228 bpp = 0;
1229 }
1230
1231 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1232 cicr4 |= CICR4_PCLK_EN;
1233 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1234 cicr4 |= CICR4_MCLK_EN;
1235 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1236 cicr4 |= CICR4_PCP;
1237 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1238 cicr4 |= CICR4_HSP;
1239 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1240 cicr4 |= CICR4_VSP;
1241
1242 cicr0 = __raw_readl(pcdev->base + CICR0);
1243 if (cicr0 & CICR0_ENB)
1244 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1245
1246 cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1247
1248 switch (pixfmt) {
1249 case V4L2_PIX_FMT_YUV422P:
1250 pcdev->channels = 3;
1251 cicr1 |= CICR1_YCBCR_F;
1252 /*
1253 * Normally, pxa bus wants as input UYVY format. We allow all
1254 * reorderings of the YUV422 format, as no processing is done,
1255 * and the YUV stream is just passed through without any
1256 * transformation. Note that UYVY is the only format that
1257 * should be used if pxa framebuffer Overlay2 is used.
1258 */
1259 /* fall through */
1260 case V4L2_PIX_FMT_UYVY:
1261 case V4L2_PIX_FMT_VYUY:
1262 case V4L2_PIX_FMT_YUYV:
1263 case V4L2_PIX_FMT_YVYU:
1264 cicr1 |= CICR1_COLOR_SP_VAL(2);
1265 break;
1266 case V4L2_PIX_FMT_RGB555:
1267 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1268 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1269 break;
1270 case V4L2_PIX_FMT_RGB565:
1271 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1272 break;
1273 }
1274
1275 cicr2 = 0;
1276 cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1277 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1278 cicr4 |= pcdev->mclk_divisor;
1279
1280 __raw_writel(cicr1, pcdev->base + CICR1);
1281 __raw_writel(cicr2, pcdev->base + CICR2);
1282 __raw_writel(cicr3, pcdev->base + CICR3);
1283 __raw_writel(cicr4, pcdev->base + CICR4);
1284
1285 /* CIF interrupts are not used, only DMA */
1286 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1287 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1288 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1289 __raw_writel(cicr0, pcdev->base + CICR0);
1290 }
1291
1292 /*
1293 * Videobuf2 section
1294 */
pxa_buffer_cleanup(struct pxa_buffer * buf)1295 static void pxa_buffer_cleanup(struct pxa_buffer *buf)
1296 {
1297 int i;
1298
1299 for (i = 0; i < 3 && buf->descs[i]; i++) {
1300 dmaengine_desc_free(buf->descs[i]);
1301 kfree(buf->sg[i]);
1302 buf->descs[i] = NULL;
1303 buf->sg[i] = NULL;
1304 buf->sg_len[i] = 0;
1305 buf->plane_sizes[i] = 0;
1306 }
1307 buf->nb_planes = 0;
1308 }
1309
pxa_buffer_init(struct pxa_camera_dev * pcdev,struct pxa_buffer * buf)1310 static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
1311 struct pxa_buffer *buf)
1312 {
1313 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
1314 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1315 int nb_channels = pcdev->channels;
1316 int i, ret = 0;
1317 unsigned long size = vb2_plane_size(vb, 0);
1318
1319 switch (nb_channels) {
1320 case 1:
1321 buf->plane_sizes[0] = size;
1322 break;
1323 case 3:
1324 buf->plane_sizes[0] = size / 2;
1325 buf->plane_sizes[1] = size / 4;
1326 buf->plane_sizes[2] = size / 4;
1327 break;
1328 default:
1329 return -EINVAL;
1330 }
1331 buf->nb_planes = nb_channels;
1332
1333 ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
1334 buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
1335 if (ret < 0) {
1336 dev_err(pcdev_to_dev(pcdev),
1337 "sg_split failed: %d\n", ret);
1338 return ret;
1339 }
1340 for (i = 0; i < nb_channels; i++) {
1341 ret = pxa_init_dma_channel(pcdev, buf, i,
1342 buf->sg[i], buf->sg_len[i]);
1343 if (ret) {
1344 pxa_buffer_cleanup(buf);
1345 return ret;
1346 }
1347 }
1348 INIT_LIST_HEAD(&buf->queue);
1349
1350 return ret;
1351 }
1352
pxac_vb2_cleanup(struct vb2_buffer * vb)1353 static void pxac_vb2_cleanup(struct vb2_buffer *vb)
1354 {
1355 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1356 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1357
1358 dev_dbg(pcdev_to_dev(pcdev),
1359 "%s(vb=%p)\n", __func__, vb);
1360 pxa_buffer_cleanup(buf);
1361 }
1362
pxac_vb2_queue(struct vb2_buffer * vb)1363 static void pxac_vb2_queue(struct vb2_buffer *vb)
1364 {
1365 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1366 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1367
1368 dev_dbg(pcdev_to_dev(pcdev),
1369 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
1370 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
1371 pcdev->active);
1372
1373 list_add_tail(&buf->queue, &pcdev->capture);
1374
1375 pxa_dma_add_tail_buf(pcdev, buf);
1376 }
1377
1378 /*
1379 * Please check the DMA prepared buffer structure in :
1380 * Documentation/driver-api/media/drivers/pxa_camera.rst
1381 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
1382 * modification while DMA chain is running will work anyway.
1383 */
pxac_vb2_prepare(struct vb2_buffer * vb)1384 static int pxac_vb2_prepare(struct vb2_buffer *vb)
1385 {
1386 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1387 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1388 int ret = 0;
1389 #ifdef DEBUG
1390 int i;
1391 #endif
1392
1393 switch (pcdev->channels) {
1394 case 1:
1395 case 3:
1396 vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1397 break;
1398 default:
1399 return -EINVAL;
1400 }
1401
1402 dev_dbg(pcdev_to_dev(pcdev),
1403 "%s (vb=%p) nb_channels=%d size=%lu\n",
1404 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
1405
1406 WARN_ON(!pcdev->current_fmt);
1407
1408 #ifdef DEBUG
1409 /*
1410 * This can be useful if you want to see if we actually fill
1411 * the buffer with something
1412 */
1413 for (i = 0; i < vb->num_planes; i++)
1414 memset((void *)vb2_plane_vaddr(vb, i),
1415 0xaa, vb2_get_plane_payload(vb, i));
1416 #endif
1417
1418 /*
1419 * I think, in buf_prepare you only have to protect global data,
1420 * the actual buffer is yours
1421 */
1422 buf->inwork = 0;
1423 pxa_videobuf_set_actdma(pcdev, buf);
1424
1425 return ret;
1426 }
1427
pxac_vb2_init(struct vb2_buffer * vb)1428 static int pxac_vb2_init(struct vb2_buffer *vb)
1429 {
1430 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1431 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1432
1433 dev_dbg(pcdev_to_dev(pcdev),
1434 "%s(nb_channels=%d)\n",
1435 __func__, pcdev->channels);
1436
1437 return pxa_buffer_init(pcdev, buf);
1438 }
1439
pxac_vb2_queue_setup(struct vb2_queue * vq,unsigned int * nbufs,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_devs[])1440 static int pxac_vb2_queue_setup(struct vb2_queue *vq,
1441 unsigned int *nbufs,
1442 unsigned int *num_planes, unsigned int sizes[],
1443 struct device *alloc_devs[])
1444 {
1445 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1446 int size = pcdev->current_pix.sizeimage;
1447
1448 dev_dbg(pcdev_to_dev(pcdev),
1449 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
1450 __func__, vq, *nbufs, *num_planes, size);
1451 /*
1452 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1453 * format, even if there are 3 planes Y, U and V, we reply there is only
1454 * one plane, containing Y, U and V data, one after the other.
1455 */
1456 if (*num_planes)
1457 return sizes[0] < size ? -EINVAL : 0;
1458
1459 *num_planes = 1;
1460 switch (pcdev->channels) {
1461 case 1:
1462 case 3:
1463 sizes[0] = size;
1464 break;
1465 default:
1466 return -EINVAL;
1467 }
1468
1469 if (!*nbufs)
1470 *nbufs = 1;
1471
1472 return 0;
1473 }
1474
pxac_vb2_start_streaming(struct vb2_queue * vq,unsigned int count)1475 static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1476 {
1477 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1478
1479 dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1480 __func__, count, pcdev->active);
1481
1482 pcdev->buf_sequence = 0;
1483 if (!pcdev->active)
1484 pxa_camera_start_capture(pcdev);
1485
1486 return 0;
1487 }
1488
pxac_vb2_stop_streaming(struct vb2_queue * vq)1489 static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1490 {
1491 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1492 struct pxa_buffer *buf, *tmp;
1493
1494 dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
1495 __func__, pcdev->active);
1496 pxa_camera_stop_capture(pcdev);
1497
1498 list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
1499 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1500 }
1501
1502 static const struct vb2_ops pxac_vb2_ops = {
1503 .queue_setup = pxac_vb2_queue_setup,
1504 .buf_init = pxac_vb2_init,
1505 .buf_prepare = pxac_vb2_prepare,
1506 .buf_queue = pxac_vb2_queue,
1507 .buf_cleanup = pxac_vb2_cleanup,
1508 .start_streaming = pxac_vb2_start_streaming,
1509 .stop_streaming = pxac_vb2_stop_streaming,
1510 .wait_prepare = vb2_ops_wait_prepare,
1511 .wait_finish = vb2_ops_wait_finish,
1512 };
1513
pxa_camera_init_videobuf2(struct pxa_camera_dev * pcdev)1514 static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1515 {
1516 int ret;
1517 struct vb2_queue *vq = &pcdev->vb2_vq;
1518
1519 memset(vq, 0, sizeof(*vq));
1520 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1521 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1522 vq->drv_priv = pcdev;
1523 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1524 vq->buf_struct_size = sizeof(struct pxa_buffer);
1525 vq->dev = pcdev->v4l2_dev.dev;
1526
1527 vq->ops = &pxac_vb2_ops;
1528 vq->mem_ops = &vb2_dma_sg_memops;
1529 vq->lock = &pcdev->mlock;
1530
1531 ret = vb2_queue_init(vq);
1532 dev_dbg(pcdev_to_dev(pcdev),
1533 "vb2_queue_init(vq=%p): %d\n", vq, ret);
1534
1535 return ret;
1536 }
1537
1538 /*
1539 * Video ioctls section
1540 */
pxa_camera_set_bus_param(struct pxa_camera_dev * pcdev)1541 static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1542 {
1543 unsigned int bus_width = pcdev->current_fmt->host_fmt->bits_per_sample;
1544 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1545 u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1546 int mbus_config;
1547 int ret;
1548
1549 if (!((1 << (bus_width - 1)) & pcdev->width_flags)) {
1550 dev_err(pcdev_to_dev(pcdev), "Unsupported bus width %u",
1551 bus_width);
1552 return -EINVAL;
1553 }
1554
1555 pcdev->channels = 1;
1556
1557 /* Make choices, based on platform preferences */
1558 mbus_config = 0;
1559 if (pcdev->platform_flags & PXA_CAMERA_MASTER)
1560 mbus_config |= V4L2_MBUS_MASTER;
1561 else
1562 mbus_config |= V4L2_MBUS_SLAVE;
1563
1564 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1565 mbus_config |= V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1566 else
1567 mbus_config |= V4L2_MBUS_HSYNC_ACTIVE_LOW;
1568
1569 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1570 mbus_config |= V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1571 else
1572 mbus_config |= V4L2_MBUS_VSYNC_ACTIVE_LOW;
1573
1574 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1575 mbus_config |= V4L2_MBUS_PCLK_SAMPLE_RISING;
1576 else
1577 mbus_config |= V4L2_MBUS_PCLK_SAMPLE_FALLING;
1578 mbus_config |= V4L2_MBUS_DATA_ACTIVE_HIGH;
1579
1580 cfg.flags = mbus_config;
1581 ret = sensor_call(pcdev, pad, set_mbus_config, 0, &cfg);
1582 if (ret < 0 && ret != -ENOIOCTLCMD) {
1583 dev_err(pcdev_to_dev(pcdev),
1584 "Failed to call set_mbus_config: %d\n", ret);
1585 return ret;
1586 }
1587
1588 /*
1589 * If the requested media bus configuration has not been fully applied
1590 * make sure it is supported by the platform.
1591 *
1592 * PXA does not support V4L2_MBUS_DATA_ACTIVE_LOW and the bus mastering
1593 * roles should match.
1594 */
1595 if (cfg.flags != mbus_config) {
1596 unsigned int pxa_mbus_role = mbus_config & (V4L2_MBUS_MASTER |
1597 V4L2_MBUS_SLAVE);
1598 if (pxa_mbus_role != (cfg.flags & (V4L2_MBUS_MASTER |
1599 V4L2_MBUS_SLAVE))) {
1600 dev_err(pcdev_to_dev(pcdev),
1601 "Unsupported mbus configuration: bus mastering\n");
1602 return -EINVAL;
1603 }
1604
1605 if (cfg.flags & V4L2_MBUS_DATA_ACTIVE_LOW) {
1606 dev_err(pcdev_to_dev(pcdev),
1607 "Unsupported mbus configuration: DATA_ACTIVE_LOW\n");
1608 return -EINVAL;
1609 }
1610 }
1611
1612 pxa_camera_setup_cicr(pcdev, cfg.flags, pixfmt);
1613
1614 return 0;
1615 }
1616
1617 static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1618 {
1619 .fourcc = V4L2_PIX_FMT_YUV422P,
1620 .name = "Planar YUV422 16 bit",
1621 .bits_per_sample = 8,
1622 .packing = PXA_MBUS_PACKING_2X8_PADHI,
1623 .order = PXA_MBUS_ORDER_LE,
1624 .layout = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1625 },
1626 };
1627
1628 /* This will be corrected as we get more formats */
pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt * fmt)1629 static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1630 {
1631 return fmt->packing == PXA_MBUS_PACKING_NONE ||
1632 (fmt->bits_per_sample == 8 &&
1633 fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1634 (fmt->bits_per_sample > 8 &&
1635 fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1636 }
1637
pxa_camera_get_formats(struct v4l2_device * v4l2_dev,unsigned int idx,struct pxa_camera_format_xlate * xlate)1638 static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
1639 unsigned int idx,
1640 struct pxa_camera_format_xlate *xlate)
1641 {
1642 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1643 int formats = 0, ret;
1644 struct v4l2_subdev_mbus_code_enum code = {
1645 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1646 .index = idx,
1647 };
1648 const struct pxa_mbus_pixelfmt *fmt;
1649
1650 ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1651 if (ret < 0)
1652 /* No more formats */
1653 return 0;
1654
1655 fmt = pxa_mbus_get_fmtdesc(code.code);
1656 if (!fmt) {
1657 dev_err(pcdev_to_dev(pcdev),
1658 "Invalid format code #%u: %d\n", idx, code.code);
1659 return 0;
1660 }
1661
1662 switch (code.code) {
1663 case MEDIA_BUS_FMT_UYVY8_2X8:
1664 formats++;
1665 if (xlate) {
1666 xlate->host_fmt = &pxa_camera_formats[0];
1667 xlate->code = code.code;
1668 xlate++;
1669 dev_dbg(pcdev_to_dev(pcdev),
1670 "Providing format %s using code %d\n",
1671 pxa_camera_formats[0].name, code.code);
1672 }
1673 /* fall through */
1674 case MEDIA_BUS_FMT_VYUY8_2X8:
1675 case MEDIA_BUS_FMT_YUYV8_2X8:
1676 case MEDIA_BUS_FMT_YVYU8_2X8:
1677 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1678 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1679 if (xlate)
1680 dev_dbg(pcdev_to_dev(pcdev),
1681 "Providing format %s packed\n",
1682 fmt->name);
1683 break;
1684 default:
1685 if (!pxa_camera_packing_supported(fmt))
1686 return 0;
1687 if (xlate)
1688 dev_dbg(pcdev_to_dev(pcdev),
1689 "Providing format %s in pass-through mode\n",
1690 fmt->name);
1691 break;
1692 }
1693
1694 /* Generic pass-through */
1695 formats++;
1696 if (xlate) {
1697 xlate->host_fmt = fmt;
1698 xlate->code = code.code;
1699 xlate++;
1700 }
1701
1702 return formats;
1703 }
1704
pxa_camera_build_formats(struct pxa_camera_dev * pcdev)1705 static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
1706 {
1707 struct pxa_camera_format_xlate *xlate;
1708
1709 xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1710 pxa_camera_get_formats);
1711 if (IS_ERR(xlate))
1712 return PTR_ERR(xlate);
1713
1714 pcdev->user_formats = xlate;
1715 return 0;
1716 }
1717
pxa_camera_destroy_formats(struct pxa_camera_dev * pcdev)1718 static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1719 {
1720 kfree(pcdev->user_formats);
1721 }
1722
pxa_camera_check_frame(u32 width,u32 height)1723 static int pxa_camera_check_frame(u32 width, u32 height)
1724 {
1725 /* limit to pxa hardware capabilities */
1726 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1727 (width & 0x01);
1728 }
1729
1730 #ifdef CONFIG_VIDEO_ADV_DEBUG
pxac_vidioc_g_register(struct file * file,void * priv,struct v4l2_dbg_register * reg)1731 static int pxac_vidioc_g_register(struct file *file, void *priv,
1732 struct v4l2_dbg_register *reg)
1733 {
1734 struct pxa_camera_dev *pcdev = video_drvdata(file);
1735
1736 if (reg->reg > CIBR2)
1737 return -ERANGE;
1738
1739 reg->val = __raw_readl(pcdev->base + reg->reg);
1740 reg->size = sizeof(__u32);
1741 return 0;
1742 }
1743
pxac_vidioc_s_register(struct file * file,void * priv,const struct v4l2_dbg_register * reg)1744 static int pxac_vidioc_s_register(struct file *file, void *priv,
1745 const struct v4l2_dbg_register *reg)
1746 {
1747 struct pxa_camera_dev *pcdev = video_drvdata(file);
1748
1749 if (reg->reg > CIBR2)
1750 return -ERANGE;
1751 if (reg->size != sizeof(__u32))
1752 return -EINVAL;
1753 __raw_writel(reg->val, pcdev->base + reg->reg);
1754 return 0;
1755 }
1756 #endif
1757
pxac_vidioc_enum_fmt_vid_cap(struct file * filp,void * priv,struct v4l2_fmtdesc * f)1758 static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv,
1759 struct v4l2_fmtdesc *f)
1760 {
1761 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1762 const struct pxa_mbus_pixelfmt *format;
1763 unsigned int idx;
1764
1765 for (idx = 0; pcdev->user_formats[idx].code; idx++);
1766 if (f->index >= idx)
1767 return -EINVAL;
1768
1769 format = pcdev->user_formats[f->index].host_fmt;
1770 f->pixelformat = format->fourcc;
1771 return 0;
1772 }
1773
pxac_vidioc_g_fmt_vid_cap(struct file * filp,void * priv,struct v4l2_format * f)1774 static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1775 struct v4l2_format *f)
1776 {
1777 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1778 struct v4l2_pix_format *pix = &f->fmt.pix;
1779
1780 pix->width = pcdev->current_pix.width;
1781 pix->height = pcdev->current_pix.height;
1782 pix->bytesperline = pcdev->current_pix.bytesperline;
1783 pix->sizeimage = pcdev->current_pix.sizeimage;
1784 pix->field = pcdev->current_pix.field;
1785 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
1786 pix->colorspace = pcdev->current_pix.colorspace;
1787 dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
1788 pcdev->current_fmt->host_fmt->fourcc);
1789 return 0;
1790 }
1791
pxac_vidioc_try_fmt_vid_cap(struct file * filp,void * priv,struct v4l2_format * f)1792 static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1793 struct v4l2_format *f)
1794 {
1795 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1796 const struct pxa_camera_format_xlate *xlate;
1797 struct v4l2_pix_format *pix = &f->fmt.pix;
1798 struct v4l2_subdev_pad_config pad_cfg;
1799 struct v4l2_subdev_format format = {
1800 .which = V4L2_SUBDEV_FORMAT_TRY,
1801 };
1802 struct v4l2_mbus_framefmt *mf = &format.format;
1803 __u32 pixfmt = pix->pixelformat;
1804 int ret;
1805
1806 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1807 if (!xlate) {
1808 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1809 return -EINVAL;
1810 }
1811
1812 /*
1813 * Limit to pxa hardware capabilities. YUV422P planar format requires
1814 * images size to be a multiple of 16 bytes. If not, zeros will be
1815 * inserted between Y and U planes, and U and V planes, which violates
1816 * the YUV422P standard.
1817 */
1818 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1819 &pix->height, 32, 2048, 0,
1820 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1821
1822 v4l2_fill_mbus_format(mf, pix, xlate->code);
1823 ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format);
1824 if (ret < 0)
1825 return ret;
1826
1827 v4l2_fill_pix_format(pix, mf);
1828
1829 /* Only progressive video supported so far */
1830 switch (mf->field) {
1831 case V4L2_FIELD_ANY:
1832 case V4L2_FIELD_NONE:
1833 pix->field = V4L2_FIELD_NONE;
1834 break;
1835 default:
1836 /* TODO: support interlaced at least in pass-through mode */
1837 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1838 mf->field);
1839 return -EINVAL;
1840 }
1841
1842 ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1843 if (ret < 0)
1844 return ret;
1845
1846 pix->bytesperline = ret;
1847 ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1848 pix->height);
1849 if (ret < 0)
1850 return ret;
1851
1852 pix->sizeimage = ret;
1853 return 0;
1854 }
1855
pxac_vidioc_s_fmt_vid_cap(struct file * filp,void * priv,struct v4l2_format * f)1856 static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1857 struct v4l2_format *f)
1858 {
1859 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1860 const struct pxa_camera_format_xlate *xlate;
1861 struct v4l2_pix_format *pix = &f->fmt.pix;
1862 struct v4l2_subdev_format format = {
1863 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1864 };
1865 unsigned long flags;
1866 int ret, is_busy;
1867
1868 dev_dbg(pcdev_to_dev(pcdev),
1869 "s_fmt_vid_cap(pix=%dx%d:%x)\n",
1870 pix->width, pix->height, pix->pixelformat);
1871
1872 spin_lock_irqsave(&pcdev->lock, flags);
1873 is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
1874 spin_unlock_irqrestore(&pcdev->lock, flags);
1875
1876 if (is_busy)
1877 return -EBUSY;
1878
1879 ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
1880 if (ret)
1881 return ret;
1882
1883 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1884 pix->pixelformat);
1885 v4l2_fill_mbus_format(&format.format, pix, xlate->code);
1886 ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1887 if (ret < 0) {
1888 dev_warn(pcdev_to_dev(pcdev),
1889 "Failed to configure for format %x\n",
1890 pix->pixelformat);
1891 } else if (pxa_camera_check_frame(pix->width, pix->height)) {
1892 dev_warn(pcdev_to_dev(pcdev),
1893 "Camera driver produced an unsupported frame %dx%d\n",
1894 pix->width, pix->height);
1895 return -EINVAL;
1896 }
1897
1898 pcdev->current_fmt = xlate;
1899 pcdev->current_pix = *pix;
1900
1901 ret = pxa_camera_set_bus_param(pcdev);
1902 return ret;
1903 }
1904
pxac_vidioc_querycap(struct file * file,void * priv,struct v4l2_capability * cap)1905 static int pxac_vidioc_querycap(struct file *file, void *priv,
1906 struct v4l2_capability *cap)
1907 {
1908 strscpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
1909 strscpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
1910 strscpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1911 return 0;
1912 }
1913
pxac_vidioc_enum_input(struct file * file,void * priv,struct v4l2_input * i)1914 static int pxac_vidioc_enum_input(struct file *file, void *priv,
1915 struct v4l2_input *i)
1916 {
1917 if (i->index > 0)
1918 return -EINVAL;
1919
1920 i->type = V4L2_INPUT_TYPE_CAMERA;
1921 strscpy(i->name, "Camera", sizeof(i->name));
1922
1923 return 0;
1924 }
1925
pxac_vidioc_g_input(struct file * file,void * priv,unsigned int * i)1926 static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1927 {
1928 *i = 0;
1929
1930 return 0;
1931 }
1932
pxac_vidioc_s_input(struct file * file,void * priv,unsigned int i)1933 static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
1934 {
1935 if (i > 0)
1936 return -EINVAL;
1937
1938 return 0;
1939 }
1940
pxac_sensor_set_power(struct pxa_camera_dev * pcdev,int on)1941 static int pxac_sensor_set_power(struct pxa_camera_dev *pcdev, int on)
1942 {
1943 int ret;
1944
1945 ret = sensor_call(pcdev, core, s_power, on);
1946 if (ret == -ENOIOCTLCMD)
1947 ret = 0;
1948 if (ret) {
1949 dev_warn(pcdev_to_dev(pcdev),
1950 "Failed to put subdevice in %s mode: %d\n",
1951 on ? "normal operation" : "power saving", ret);
1952 }
1953
1954 return ret;
1955 }
1956
pxac_fops_camera_open(struct file * filp)1957 static int pxac_fops_camera_open(struct file *filp)
1958 {
1959 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1960 int ret;
1961
1962 mutex_lock(&pcdev->mlock);
1963 ret = v4l2_fh_open(filp);
1964 if (ret < 0)
1965 goto out;
1966
1967 if (!v4l2_fh_is_singular_file(filp))
1968 goto out;
1969
1970 ret = pxac_sensor_set_power(pcdev, 1);
1971 if (ret)
1972 v4l2_fh_release(filp);
1973 out:
1974 mutex_unlock(&pcdev->mlock);
1975 return ret;
1976 }
1977
pxac_fops_camera_release(struct file * filp)1978 static int pxac_fops_camera_release(struct file *filp)
1979 {
1980 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1981 int ret;
1982 bool fh_singular;
1983
1984 mutex_lock(&pcdev->mlock);
1985
1986 fh_singular = v4l2_fh_is_singular_file(filp);
1987
1988 ret = _vb2_fop_release(filp, NULL);
1989
1990 if (fh_singular)
1991 ret = pxac_sensor_set_power(pcdev, 0);
1992
1993 mutex_unlock(&pcdev->mlock);
1994
1995 return ret;
1996 }
1997
1998 static const struct v4l2_file_operations pxa_camera_fops = {
1999 .owner = THIS_MODULE,
2000 .open = pxac_fops_camera_open,
2001 .release = pxac_fops_camera_release,
2002 .read = vb2_fop_read,
2003 .poll = vb2_fop_poll,
2004 .mmap = vb2_fop_mmap,
2005 .unlocked_ioctl = video_ioctl2,
2006 };
2007
2008 static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
2009 .vidioc_querycap = pxac_vidioc_querycap,
2010
2011 .vidioc_enum_input = pxac_vidioc_enum_input,
2012 .vidioc_g_input = pxac_vidioc_g_input,
2013 .vidioc_s_input = pxac_vidioc_s_input,
2014
2015 .vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap,
2016 .vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap,
2017 .vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap,
2018 .vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap,
2019
2020 .vidioc_reqbufs = vb2_ioctl_reqbufs,
2021 .vidioc_create_bufs = vb2_ioctl_create_bufs,
2022 .vidioc_querybuf = vb2_ioctl_querybuf,
2023 .vidioc_qbuf = vb2_ioctl_qbuf,
2024 .vidioc_dqbuf = vb2_ioctl_dqbuf,
2025 .vidioc_expbuf = vb2_ioctl_expbuf,
2026 .vidioc_streamon = vb2_ioctl_streamon,
2027 .vidioc_streamoff = vb2_ioctl_streamoff,
2028 #ifdef CONFIG_VIDEO_ADV_DEBUG
2029 .vidioc_g_register = pxac_vidioc_g_register,
2030 .vidioc_s_register = pxac_vidioc_s_register,
2031 #endif
2032 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
2033 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2034 };
2035
2036 static const struct v4l2_clk_ops pxa_camera_mclk_ops = {
2037 };
2038
2039 static const struct video_device pxa_camera_videodev_template = {
2040 .name = "pxa-camera",
2041 .minor = -1,
2042 .fops = &pxa_camera_fops,
2043 .ioctl_ops = &pxa_camera_ioctl_ops,
2044 .release = video_device_release_empty,
2045 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
2046 };
2047
pxa_camera_sensor_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)2048 static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
2049 struct v4l2_subdev *subdev,
2050 struct v4l2_async_subdev *asd)
2051 {
2052 int err;
2053 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
2054 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
2055 struct video_device *vdev = &pcdev->vdev;
2056 struct v4l2_pix_format *pix = &pcdev->current_pix;
2057 struct v4l2_subdev_format format = {
2058 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2059 };
2060 struct v4l2_mbus_framefmt *mf = &format.format;
2061
2062 dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
2063 __func__);
2064 mutex_lock(&pcdev->mlock);
2065 *vdev = pxa_camera_videodev_template;
2066 vdev->v4l2_dev = v4l2_dev;
2067 vdev->lock = &pcdev->mlock;
2068 pcdev->sensor = subdev;
2069 pcdev->vdev.queue = &pcdev->vb2_vq;
2070 pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
2071 pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
2072 video_set_drvdata(&pcdev->vdev, pcdev);
2073
2074 err = pxa_camera_build_formats(pcdev);
2075 if (err) {
2076 dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
2077 err);
2078 goto out;
2079 }
2080
2081 pcdev->current_fmt = pcdev->user_formats;
2082 pix->field = V4L2_FIELD_NONE;
2083 pix->width = DEFAULT_WIDTH;
2084 pix->height = DEFAULT_HEIGHT;
2085 pix->bytesperline =
2086 pxa_mbus_bytes_per_line(pix->width,
2087 pcdev->current_fmt->host_fmt);
2088 pix->sizeimage =
2089 pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2090 pix->bytesperline, pix->height);
2091 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
2092 v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
2093
2094 err = pxac_sensor_set_power(pcdev, 1);
2095 if (err)
2096 goto out;
2097
2098 err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
2099 if (err)
2100 goto out_sensor_poweroff;
2101
2102 v4l2_fill_pix_format(pix, mf);
2103 pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
2104 __func__, pix->colorspace, pix->pixelformat);
2105
2106 err = pxa_camera_init_videobuf2(pcdev);
2107 if (err)
2108 goto out_sensor_poweroff;
2109
2110 err = video_register_device(&pcdev->vdev, VFL_TYPE_VIDEO, -1);
2111 if (err) {
2112 v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
2113 pcdev->sensor = NULL;
2114 } else {
2115 dev_info(pcdev_to_dev(pcdev),
2116 "PXA Camera driver attached to camera %s\n",
2117 subdev->name);
2118 }
2119
2120 out_sensor_poweroff:
2121 err = pxac_sensor_set_power(pcdev, 0);
2122 out:
2123 mutex_unlock(&pcdev->mlock);
2124 return err;
2125 }
2126
pxa_camera_sensor_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)2127 static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
2128 struct v4l2_subdev *subdev,
2129 struct v4l2_async_subdev *asd)
2130 {
2131 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
2132
2133 mutex_lock(&pcdev->mlock);
2134 dev_info(pcdev_to_dev(pcdev),
2135 "PXA Camera driver detached from camera %s\n",
2136 subdev->name);
2137
2138 /* disable capture, disable interrupts */
2139 __raw_writel(0x3ff, pcdev->base + CICR0);
2140
2141 /* Stop DMA engine */
2142 pxa_dma_stop_channels(pcdev);
2143
2144 pxa_camera_destroy_formats(pcdev);
2145
2146 if (pcdev->mclk_clk) {
2147 v4l2_clk_unregister(pcdev->mclk_clk);
2148 pcdev->mclk_clk = NULL;
2149 }
2150
2151 video_unregister_device(&pcdev->vdev);
2152 pcdev->sensor = NULL;
2153
2154 mutex_unlock(&pcdev->mlock);
2155 }
2156
2157 static const struct v4l2_async_notifier_operations pxa_camera_sensor_ops = {
2158 .bound = pxa_camera_sensor_bound,
2159 .unbind = pxa_camera_sensor_unbind,
2160 };
2161
2162 /*
2163 * Driver probe, remove, suspend and resume operations
2164 */
pxa_camera_suspend(struct device * dev)2165 static int pxa_camera_suspend(struct device *dev)
2166 {
2167 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2168 int i = 0, ret = 0;
2169
2170 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
2171 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
2172 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
2173 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
2174 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2175
2176 if (pcdev->sensor)
2177 ret = pxac_sensor_set_power(pcdev, 0);
2178
2179 return ret;
2180 }
2181
pxa_camera_resume(struct device * dev)2182 static int pxa_camera_resume(struct device *dev)
2183 {
2184 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2185 int i = 0, ret = 0;
2186
2187 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
2188 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
2189 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
2190 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
2191 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2192
2193 if (pcdev->sensor) {
2194 ret = pxac_sensor_set_power(pcdev, 1);
2195 }
2196
2197 /* Restart frame capture if active buffer exists */
2198 if (!ret && pcdev->active)
2199 pxa_camera_start_capture(pcdev);
2200
2201 return ret;
2202 }
2203
pxa_camera_pdata_from_dt(struct device * dev,struct pxa_camera_dev * pcdev,struct v4l2_async_subdev * asd)2204 static int pxa_camera_pdata_from_dt(struct device *dev,
2205 struct pxa_camera_dev *pcdev,
2206 struct v4l2_async_subdev *asd)
2207 {
2208 u32 mclk_rate;
2209 struct device_node *remote, *np = dev->of_node;
2210 struct v4l2_fwnode_endpoint ep = { .bus_type = 0 };
2211 int err = of_property_read_u32(np, "clock-frequency",
2212 &mclk_rate);
2213 if (!err) {
2214 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
2215 pcdev->mclk = mclk_rate;
2216 }
2217
2218 np = of_graph_get_next_endpoint(np, NULL);
2219 if (!np) {
2220 dev_err(dev, "could not find endpoint\n");
2221 return -EINVAL;
2222 }
2223
2224 err = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
2225 if (err) {
2226 dev_err(dev, "could not parse endpoint\n");
2227 goto out;
2228 }
2229
2230 switch (ep.bus.parallel.bus_width) {
2231 case 4:
2232 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
2233 break;
2234 case 5:
2235 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
2236 break;
2237 case 8:
2238 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
2239 break;
2240 case 9:
2241 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
2242 break;
2243 case 10:
2244 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2245 break;
2246 default:
2247 break;
2248 }
2249
2250 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
2251 pcdev->platform_flags |= PXA_CAMERA_MASTER;
2252 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2253 pcdev->platform_flags |= PXA_CAMERA_HSP;
2254 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2255 pcdev->platform_flags |= PXA_CAMERA_VSP;
2256 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2257 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
2258 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
2259 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
2260
2261 asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
2262 remote = of_graph_get_remote_port_parent(np);
2263 if (remote)
2264 asd->match.fwnode = of_fwnode_handle(remote);
2265 else
2266 dev_notice(dev, "no remote for %pOF\n", np);
2267
2268 out:
2269 of_node_put(np);
2270
2271 return err;
2272 }
2273
pxa_camera_probe(struct platform_device * pdev)2274 static int pxa_camera_probe(struct platform_device *pdev)
2275 {
2276 struct pxa_camera_dev *pcdev;
2277 struct resource *res;
2278 void __iomem *base;
2279 struct dma_slave_config config = {
2280 .src_addr_width = 0,
2281 .src_maxburst = 8,
2282 .direction = DMA_DEV_TO_MEM,
2283 };
2284 char clk_name[V4L2_CLK_NAME_SIZE];
2285 int irq;
2286 int err = 0, i;
2287
2288 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2289 irq = platform_get_irq(pdev, 0);
2290 if (!res || irq < 0)
2291 return -ENODEV;
2292
2293 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2294 if (!pcdev) {
2295 dev_err(&pdev->dev, "Could not allocate pcdev\n");
2296 return -ENOMEM;
2297 }
2298
2299 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
2300 if (IS_ERR(pcdev->clk))
2301 return PTR_ERR(pcdev->clk);
2302
2303 pcdev->res = res;
2304
2305 pcdev->pdata = pdev->dev.platform_data;
2306 if (pcdev->pdata) {
2307 pcdev->platform_flags = pcdev->pdata->flags;
2308 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2309 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2310 pcdev->asd.match.i2c.adapter_id =
2311 pcdev->pdata->sensor_i2c_adapter_id;
2312 pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address;
2313 } else if (pdev->dev.of_node) {
2314 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd);
2315 } else {
2316 return -ENODEV;
2317 }
2318 if (err < 0)
2319 return err;
2320
2321 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
2322 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2323 /*
2324 * Platform hasn't set available data widths. This is bad.
2325 * Warn and use a default.
2326 */
2327 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
2328 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2329 }
2330 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
2331 pcdev->width_flags = 1 << 7;
2332 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
2333 pcdev->width_flags |= 1 << 8;
2334 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
2335 pcdev->width_flags |= 1 << 9;
2336 if (!pcdev->mclk) {
2337 dev_warn(&pdev->dev,
2338 "mclk == 0! Please, fix your platform data. Using default 20MHz\n");
2339 pcdev->mclk = 20000000;
2340 }
2341
2342 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2343
2344 INIT_LIST_HEAD(&pcdev->capture);
2345 spin_lock_init(&pcdev->lock);
2346 mutex_init(&pcdev->mlock);
2347
2348 /*
2349 * Request the regions.
2350 */
2351 base = devm_ioremap_resource(&pdev->dev, res);
2352 if (IS_ERR(base))
2353 return PTR_ERR(base);
2354
2355 pcdev->irq = irq;
2356 pcdev->base = base;
2357
2358 /* request dma */
2359 pcdev->dma_chans[0] = dma_request_chan(&pdev->dev, "CI_Y");
2360 if (IS_ERR(pcdev->dma_chans[0])) {
2361 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2362 return PTR_ERR(pcdev->dma_chans[0]);
2363 }
2364
2365 pcdev->dma_chans[1] = dma_request_chan(&pdev->dev, "CI_U");
2366 if (IS_ERR(pcdev->dma_chans[1])) {
2367 dev_err(&pdev->dev, "Can't request DMA for U\n");
2368 err = PTR_ERR(pcdev->dma_chans[1]);
2369 goto exit_free_dma_y;
2370 }
2371
2372 pcdev->dma_chans[2] = dma_request_chan(&pdev->dev, "CI_V");
2373 if (IS_ERR(pcdev->dma_chans[2])) {
2374 dev_err(&pdev->dev, "Can't request DMA for V\n");
2375 err = PTR_ERR(pcdev->dma_chans[2]);
2376 goto exit_free_dma_u;
2377 }
2378
2379 for (i = 0; i < 3; i++) {
2380 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
2381 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
2382 if (err < 0) {
2383 dev_err(&pdev->dev, "dma slave config failed: %d\n",
2384 err);
2385 goto exit_free_dma;
2386 }
2387 }
2388
2389 /* request irq */
2390 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
2391 PXA_CAM_DRV_NAME, pcdev);
2392 if (err) {
2393 dev_err(&pdev->dev, "Camera interrupt register failed\n");
2394 goto exit_free_dma;
2395 }
2396
2397 tasklet_setup(&pcdev->task_eof, pxa_camera_eof);
2398
2399 pxa_camera_activate(pcdev);
2400
2401 dev_set_drvdata(&pdev->dev, pcdev);
2402 err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2403 if (err)
2404 goto exit_deactivate;
2405
2406 v4l2_async_notifier_init(&pcdev->notifier);
2407
2408 err = v4l2_async_notifier_add_subdev(&pcdev->notifier, &pcdev->asd);
2409 if (err) {
2410 fwnode_handle_put(pcdev->asd.match.fwnode);
2411 goto exit_free_v4l2dev;
2412 }
2413
2414 pcdev->notifier.ops = &pxa_camera_sensor_ops;
2415
2416 if (!of_have_populated_dt())
2417 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2418
2419 err = pxa_camera_init_videobuf2(pcdev);
2420 if (err)
2421 goto exit_notifier_cleanup;
2422
2423 v4l2_clk_name_i2c(clk_name, sizeof(clk_name),
2424 pcdev->asd.match.i2c.adapter_id,
2425 pcdev->asd.match.i2c.address);
2426
2427 pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops, clk_name, NULL);
2428 if (IS_ERR(pcdev->mclk_clk)) {
2429 err = PTR_ERR(pcdev->mclk_clk);
2430 goto exit_notifier_cleanup;
2431 }
2432
2433 err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier);
2434 if (err)
2435 goto exit_free_clk;
2436
2437 return 0;
2438 exit_free_clk:
2439 v4l2_clk_unregister(pcdev->mclk_clk);
2440 exit_notifier_cleanup:
2441 v4l2_async_notifier_cleanup(&pcdev->notifier);
2442 exit_free_v4l2dev:
2443 v4l2_device_unregister(&pcdev->v4l2_dev);
2444 exit_deactivate:
2445 pxa_camera_deactivate(pcdev);
2446 tasklet_kill(&pcdev->task_eof);
2447 exit_free_dma:
2448 dma_release_channel(pcdev->dma_chans[2]);
2449 exit_free_dma_u:
2450 dma_release_channel(pcdev->dma_chans[1]);
2451 exit_free_dma_y:
2452 dma_release_channel(pcdev->dma_chans[0]);
2453 return err;
2454 }
2455
pxa_camera_remove(struct platform_device * pdev)2456 static int pxa_camera_remove(struct platform_device *pdev)
2457 {
2458 struct pxa_camera_dev *pcdev = dev_get_drvdata(&pdev->dev);
2459
2460 pxa_camera_deactivate(pcdev);
2461 tasklet_kill(&pcdev->task_eof);
2462 dma_release_channel(pcdev->dma_chans[0]);
2463 dma_release_channel(pcdev->dma_chans[1]);
2464 dma_release_channel(pcdev->dma_chans[2]);
2465
2466 v4l2_async_notifier_unregister(&pcdev->notifier);
2467 v4l2_async_notifier_cleanup(&pcdev->notifier);
2468
2469 if (pcdev->mclk_clk) {
2470 v4l2_clk_unregister(pcdev->mclk_clk);
2471 pcdev->mclk_clk = NULL;
2472 }
2473
2474 v4l2_device_unregister(&pcdev->v4l2_dev);
2475
2476 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2477
2478 return 0;
2479 }
2480
2481 static const struct dev_pm_ops pxa_camera_pm = {
2482 .suspend = pxa_camera_suspend,
2483 .resume = pxa_camera_resume,
2484 };
2485
2486 static const struct of_device_id pxa_camera_of_match[] = {
2487 { .compatible = "marvell,pxa270-qci", },
2488 {},
2489 };
2490 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
2491
2492 static struct platform_driver pxa_camera_driver = {
2493 .driver = {
2494 .name = PXA_CAM_DRV_NAME,
2495 .pm = &pxa_camera_pm,
2496 .of_match_table = of_match_ptr(pxa_camera_of_match),
2497 },
2498 .probe = pxa_camera_probe,
2499 .remove = pxa_camera_remove,
2500 };
2501
2502 module_platform_driver(pxa_camera_driver);
2503
2504 MODULE_DESCRIPTION("PXA27x Camera Driver");
2505 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
2506 MODULE_LICENSE("GPL");
2507 MODULE_VERSION(PXA_CAM_VERSION);
2508 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
2509