1 /*
2 * Toshiba TMIO NAND flash controller driver
3 *
4 * Slightly murky pre-git history of the driver:
5 *
6 * Copyright (c) Ian Molton 2004, 2005, 2008
7 * Original work, independent of sharps code. Included hardware ECC support.
8 * Hard ECC did not work for writes in the early revisions.
9 * Copyright (c) Dirk Opfer 2005.
10 * Modifications developed from sharps code but
11 * NOT containing any, ported onto Ians base.
12 * Copyright (c) Chris Humbert 2005
13 * Copyright (c) Dmitry Baryshkov 2008
14 * Minor fixes
15 *
16 * Parts copyright Sebastian Carlier
17 *
18 * This file is licensed under
19 * the terms of the GNU General Public License version 2. This program
20 * is licensed "as is" without any warranty of any kind, whether express
21 * or implied.
22 *
23 */
24
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/mfd/core.h>
30 #include <linux/mfd/tmio.h>
31 #include <linux/delay.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/interrupt.h>
35 #include <linux/ioport.h>
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/rawnand.h>
38 #include <linux/mtd/nand_ecc.h>
39 #include <linux/mtd/partitions.h>
40 #include <linux/slab.h>
41
42 /*--------------------------------------------------------------------------*/
43
44 /*
45 * NAND Flash Host Controller Configuration Register
46 */
47 #define CCR_COMMAND 0x04 /* w Command */
48 #define CCR_BASE 0x10 /* l NAND Flash Control Reg Base Addr */
49 #define CCR_INTP 0x3d /* b Interrupt Pin */
50 #define CCR_INTE 0x48 /* b Interrupt Enable */
51 #define CCR_EC 0x4a /* b Event Control */
52 #define CCR_ICC 0x4c /* b Internal Clock Control */
53 #define CCR_ECCC 0x5b /* b ECC Control */
54 #define CCR_NFTC 0x60 /* b NAND Flash Transaction Control */
55 #define CCR_NFM 0x61 /* b NAND Flash Monitor */
56 #define CCR_NFPSC 0x62 /* b NAND Flash Power Supply Control */
57 #define CCR_NFDC 0x63 /* b NAND Flash Detect Control */
58
59 /*
60 * NAND Flash Control Register
61 */
62 #define FCR_DATA 0x00 /* bwl Data Register */
63 #define FCR_MODE 0x04 /* b Mode Register */
64 #define FCR_STATUS 0x05 /* b Status Register */
65 #define FCR_ISR 0x06 /* b Interrupt Status Register */
66 #define FCR_IMR 0x07 /* b Interrupt Mask Register */
67
68 /* FCR_MODE Register Command List */
69 #define FCR_MODE_DATA 0x94 /* Data Data_Mode */
70 #define FCR_MODE_COMMAND 0x95 /* Data Command_Mode */
71 #define FCR_MODE_ADDRESS 0x96 /* Data Address_Mode */
72
73 #define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */
74 #define FCR_MODE_HWECC_RESULT 0xD4 /* HW-ECC Calc result Read_Mode */
75 #define FCR_MODE_HWECC_RESET 0xF4 /* HW-ECC Reset */
76
77 #define FCR_MODE_POWER_ON 0x0C /* Power Supply ON to SSFDC card */
78 #define FCR_MODE_POWER_OFF 0x08 /* Power Supply OFF to SSFDC card */
79
80 #define FCR_MODE_LED_OFF 0x00 /* LED OFF */
81 #define FCR_MODE_LED_ON 0x04 /* LED ON */
82
83 #define FCR_MODE_EJECT_ON 0x68 /* Ejection events active */
84 #define FCR_MODE_EJECT_OFF 0x08 /* Ejection events ignored */
85
86 #define FCR_MODE_LOCK 0x6C /* Lock_Mode. Eject Switch Invalid */
87 #define FCR_MODE_UNLOCK 0x0C /* UnLock_Mode. Eject Switch is valid */
88
89 #define FCR_MODE_CONTROLLER_ID 0x40 /* Controller ID Read */
90 #define FCR_MODE_STANDBY 0x00 /* SSFDC card Changes Standby State */
91
92 #define FCR_MODE_WE 0x80
93 #define FCR_MODE_ECC1 0x40
94 #define FCR_MODE_ECC0 0x20
95 #define FCR_MODE_CE 0x10
96 #define FCR_MODE_PCNT1 0x08
97 #define FCR_MODE_PCNT0 0x04
98 #define FCR_MODE_ALE 0x02
99 #define FCR_MODE_CLE 0x01
100
101 #define FCR_STATUS_BUSY 0x80
102
103 /*--------------------------------------------------------------------------*/
104
105 struct tmio_nand {
106 struct nand_controller controller;
107 struct nand_chip chip;
108 struct completion comp;
109
110 struct platform_device *dev;
111
112 void __iomem *ccr;
113 void __iomem *fcr;
114 unsigned long fcr_base;
115
116 unsigned int irq;
117
118 /* for tmio_nand_read_byte */
119 u8 read;
120 unsigned read_good:1;
121 };
122
mtd_to_tmio(struct mtd_info * mtd)123 static inline struct tmio_nand *mtd_to_tmio(struct mtd_info *mtd)
124 {
125 return container_of(mtd_to_nand(mtd), struct tmio_nand, chip);
126 }
127
128
129 /*--------------------------------------------------------------------------*/
130
tmio_nand_hwcontrol(struct nand_chip * chip,int cmd,unsigned int ctrl)131 static void tmio_nand_hwcontrol(struct nand_chip *chip, int cmd,
132 unsigned int ctrl)
133 {
134 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
135
136 if (ctrl & NAND_CTRL_CHANGE) {
137 u8 mode;
138
139 if (ctrl & NAND_NCE) {
140 mode = FCR_MODE_DATA;
141
142 if (ctrl & NAND_CLE)
143 mode |= FCR_MODE_CLE;
144 else
145 mode &= ~FCR_MODE_CLE;
146
147 if (ctrl & NAND_ALE)
148 mode |= FCR_MODE_ALE;
149 else
150 mode &= ~FCR_MODE_ALE;
151 } else {
152 mode = FCR_MODE_STANDBY;
153 }
154
155 tmio_iowrite8(mode, tmio->fcr + FCR_MODE);
156 tmio->read_good = 0;
157 }
158
159 if (cmd != NAND_CMD_NONE)
160 tmio_iowrite8(cmd, chip->legacy.IO_ADDR_W);
161 }
162
tmio_nand_dev_ready(struct nand_chip * chip)163 static int tmio_nand_dev_ready(struct nand_chip *chip)
164 {
165 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
166
167 return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY);
168 }
169
tmio_irq(int irq,void * __tmio)170 static irqreturn_t tmio_irq(int irq, void *__tmio)
171 {
172 struct tmio_nand *tmio = __tmio;
173
174 /* disable RDYREQ interrupt */
175 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
176 complete(&tmio->comp);
177
178 return IRQ_HANDLED;
179 }
180
181 /*
182 *The TMIO core has a RDYREQ interrupt on the posedge of #SMRB.
183 *This interrupt is normally disabled, but for long operations like
184 *erase and write, we enable it to wake us up. The irq handler
185 *disables the interrupt.
186 */
tmio_nand_wait(struct nand_chip * nand_chip)187 static int tmio_nand_wait(struct nand_chip *nand_chip)
188 {
189 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(nand_chip));
190 long timeout;
191 u8 status;
192
193 /* enable RDYREQ interrupt */
194
195 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
196 reinit_completion(&tmio->comp);
197 tmio_iowrite8(0x81, tmio->fcr + FCR_IMR);
198
199 timeout = 400;
200 timeout = wait_for_completion_timeout(&tmio->comp,
201 msecs_to_jiffies(timeout));
202
203 if (unlikely(!tmio_nand_dev_ready(nand_chip))) {
204 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
205 dev_warn(&tmio->dev->dev, "still busy after 400 ms\n");
206
207 } else if (unlikely(!timeout)) {
208 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
209 dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n");
210 }
211
212 nand_status_op(nand_chip, &status);
213 return status;
214 }
215
216 /*
217 *The TMIO controller combines two 8-bit data bytes into one 16-bit
218 *word. This function separates them so nand_base.c works as expected,
219 *especially its NAND_CMD_READID routines.
220 *
221 *To prevent stale data from being read, tmio_nand_hwcontrol() clears
222 *tmio->read_good.
223 */
tmio_nand_read_byte(struct nand_chip * chip)224 static u_char tmio_nand_read_byte(struct nand_chip *chip)
225 {
226 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
227 unsigned int data;
228
229 if (tmio->read_good--)
230 return tmio->read;
231
232 data = tmio_ioread16(tmio->fcr + FCR_DATA);
233 tmio->read = data >> 8;
234 return data;
235 }
236
237 /*
238 *The TMIO controller converts an 8-bit NAND interface to a 16-bit
239 *bus interface, so all data reads and writes must be 16-bit wide.
240 *Thus, we implement 16-bit versions of the read, write, and verify
241 *buffer functions.
242 */
243 static void
tmio_nand_write_buf(struct nand_chip * chip,const u_char * buf,int len)244 tmio_nand_write_buf(struct nand_chip *chip, const u_char *buf, int len)
245 {
246 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
247
248 tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
249 }
250
tmio_nand_read_buf(struct nand_chip * chip,u_char * buf,int len)251 static void tmio_nand_read_buf(struct nand_chip *chip, u_char *buf, int len)
252 {
253 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
254
255 tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
256 }
257
tmio_nand_enable_hwecc(struct nand_chip * chip,int mode)258 static void tmio_nand_enable_hwecc(struct nand_chip *chip, int mode)
259 {
260 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
261
262 tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE);
263 tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */
264 tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE);
265 }
266
tmio_nand_calculate_ecc(struct nand_chip * chip,const u_char * dat,u_char * ecc_code)267 static int tmio_nand_calculate_ecc(struct nand_chip *chip, const u_char *dat,
268 u_char *ecc_code)
269 {
270 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
271 unsigned int ecc;
272
273 tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE);
274
275 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
276 ecc_code[1] = ecc; /* 000-255 LP7-0 */
277 ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */
278 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
279 ecc_code[2] = ecc; /* 000-255 CP5-0,11b */
280 ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */
281 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
282 ecc_code[3] = ecc; /* 256-511 LP15-8 */
283 ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */
284
285 tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE);
286 return 0;
287 }
288
tmio_nand_correct_data(struct nand_chip * chip,unsigned char * buf,unsigned char * read_ecc,unsigned char * calc_ecc)289 static int tmio_nand_correct_data(struct nand_chip *chip, unsigned char *buf,
290 unsigned char *read_ecc,
291 unsigned char *calc_ecc)
292 {
293 int r0, r1;
294
295 /* assume ecc.size = 512 and ecc.bytes = 6 */
296 r0 = __nand_correct_data(buf, read_ecc, calc_ecc, 256, false);
297 if (r0 < 0)
298 return r0;
299 r1 = __nand_correct_data(buf + 256, read_ecc + 3, calc_ecc + 3, 256,
300 false);
301 if (r1 < 0)
302 return r1;
303 return r0 + r1;
304 }
305
tmio_hw_init(struct platform_device * dev,struct tmio_nand * tmio)306 static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio)
307 {
308 const struct mfd_cell *cell = mfd_get_cell(dev);
309 int ret;
310
311 if (cell->enable) {
312 ret = cell->enable(dev);
313 if (ret)
314 return ret;
315 }
316
317 /* (4Ch) CLKRUN Enable 1st spcrunc */
318 tmio_iowrite8(0x81, tmio->ccr + CCR_ICC);
319
320 /* (10h)BaseAddress 0x1000 spba.spba2 */
321 tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE);
322 tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2);
323
324 /* (04h)Command Register I/O spcmd */
325 tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND);
326
327 /* (62h) Power Supply Control ssmpwc */
328 /* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */
329 tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC);
330
331 /* (63h) Detect Control ssmdtc */
332 tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC);
333
334 /* Interrupt status register clear sintst */
335 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
336
337 /* After power supply, Media are reset smode */
338 tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE);
339 tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE);
340 tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA);
341
342 /* Standby Mode smode */
343 tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE);
344
345 mdelay(5);
346
347 return 0;
348 }
349
tmio_hw_stop(struct platform_device * dev,struct tmio_nand * tmio)350 static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio)
351 {
352 const struct mfd_cell *cell = mfd_get_cell(dev);
353
354 tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE);
355 if (cell->disable)
356 cell->disable(dev);
357 }
358
tmio_attach_chip(struct nand_chip * chip)359 static int tmio_attach_chip(struct nand_chip *chip)
360 {
361 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
362 return 0;
363
364 chip->ecc.size = 512;
365 chip->ecc.bytes = 6;
366 chip->ecc.strength = 2;
367 chip->ecc.hwctl = tmio_nand_enable_hwecc;
368 chip->ecc.calculate = tmio_nand_calculate_ecc;
369 chip->ecc.correct = tmio_nand_correct_data;
370
371 return 0;
372 }
373
374 static const struct nand_controller_ops tmio_ops = {
375 .attach_chip = tmio_attach_chip,
376 };
377
tmio_probe(struct platform_device * dev)378 static int tmio_probe(struct platform_device *dev)
379 {
380 struct tmio_nand_data *data = dev_get_platdata(&dev->dev);
381 struct resource *fcr = platform_get_resource(dev,
382 IORESOURCE_MEM, 0);
383 struct resource *ccr = platform_get_resource(dev,
384 IORESOURCE_MEM, 1);
385 int irq = platform_get_irq(dev, 0);
386 struct tmio_nand *tmio;
387 struct mtd_info *mtd;
388 struct nand_chip *nand_chip;
389 int retval;
390
391 if (data == NULL)
392 dev_warn(&dev->dev, "NULL platform data!\n");
393
394 tmio = devm_kzalloc(&dev->dev, sizeof(*tmio), GFP_KERNEL);
395 if (!tmio)
396 return -ENOMEM;
397
398 init_completion(&tmio->comp);
399
400 tmio->dev = dev;
401
402 platform_set_drvdata(dev, tmio);
403 nand_chip = &tmio->chip;
404 mtd = nand_to_mtd(nand_chip);
405 mtd->name = "tmio-nand";
406 mtd->dev.parent = &dev->dev;
407
408 nand_controller_init(&tmio->controller);
409 tmio->controller.ops = &tmio_ops;
410 nand_chip->controller = &tmio->controller;
411
412 tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr));
413 if (!tmio->ccr)
414 return -EIO;
415
416 tmio->fcr_base = fcr->start & 0xfffff;
417 tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr));
418 if (!tmio->fcr)
419 return -EIO;
420
421 retval = tmio_hw_init(dev, tmio);
422 if (retval)
423 return retval;
424
425 /* Set address of NAND IO lines */
426 nand_chip->legacy.IO_ADDR_R = tmio->fcr;
427 nand_chip->legacy.IO_ADDR_W = tmio->fcr;
428
429 /* Set address of hardware control function */
430 nand_chip->legacy.cmd_ctrl = tmio_nand_hwcontrol;
431 nand_chip->legacy.dev_ready = tmio_nand_dev_ready;
432 nand_chip->legacy.read_byte = tmio_nand_read_byte;
433 nand_chip->legacy.write_buf = tmio_nand_write_buf;
434 nand_chip->legacy.read_buf = tmio_nand_read_buf;
435
436 if (data)
437 nand_chip->badblock_pattern = data->badblock_pattern;
438
439 /* 15 us command delay time */
440 nand_chip->legacy.chip_delay = 15;
441
442 retval = devm_request_irq(&dev->dev, irq, &tmio_irq, 0,
443 dev_name(&dev->dev), tmio);
444 if (retval) {
445 dev_err(&dev->dev, "request_irq error %d\n", retval);
446 goto err_irq;
447 }
448
449 tmio->irq = irq;
450 nand_chip->legacy.waitfunc = tmio_nand_wait;
451
452 /* Scan to find existence of the device */
453 retval = nand_scan(nand_chip, 1);
454 if (retval)
455 goto err_irq;
456
457 /* Register the partitions */
458 retval = mtd_device_parse_register(mtd,
459 data ? data->part_parsers : NULL,
460 NULL,
461 data ? data->partition : NULL,
462 data ? data->num_partitions : 0);
463 if (!retval)
464 return retval;
465
466 nand_cleanup(nand_chip);
467
468 err_irq:
469 tmio_hw_stop(dev, tmio);
470 return retval;
471 }
472
tmio_remove(struct platform_device * dev)473 static int tmio_remove(struct platform_device *dev)
474 {
475 struct tmio_nand *tmio = platform_get_drvdata(dev);
476 struct nand_chip *chip = &tmio->chip;
477 int ret;
478
479 ret = mtd_device_unregister(nand_to_mtd(chip));
480 WARN_ON(ret);
481 nand_cleanup(chip);
482 tmio_hw_stop(dev, tmio);
483 return 0;
484 }
485
486 #ifdef CONFIG_PM
tmio_suspend(struct platform_device * dev,pm_message_t state)487 static int tmio_suspend(struct platform_device *dev, pm_message_t state)
488 {
489 const struct mfd_cell *cell = mfd_get_cell(dev);
490
491 if (cell->suspend)
492 cell->suspend(dev);
493
494 tmio_hw_stop(dev, platform_get_drvdata(dev));
495 return 0;
496 }
497
tmio_resume(struct platform_device * dev)498 static int tmio_resume(struct platform_device *dev)
499 {
500 const struct mfd_cell *cell = mfd_get_cell(dev);
501
502 /* FIXME - is this required or merely another attack of the broken
503 * SHARP platform? Looks suspicious.
504 */
505 tmio_hw_init(dev, platform_get_drvdata(dev));
506
507 if (cell->resume)
508 cell->resume(dev);
509
510 return 0;
511 }
512 #else
513 #define tmio_suspend NULL
514 #define tmio_resume NULL
515 #endif
516
517 static struct platform_driver tmio_driver = {
518 .driver.name = "tmio-nand",
519 .driver.owner = THIS_MODULE,
520 .probe = tmio_probe,
521 .remove = tmio_remove,
522 .suspend = tmio_suspend,
523 .resume = tmio_resume,
524 };
525
526 module_platform_driver(tmio_driver);
527
528 MODULE_LICENSE("GPL v2");
529 MODULE_AUTHOR("Ian Molton, Dirk Opfer, Chris Humbert, Dmitry Baryshkov");
530 MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller");
531 MODULE_ALIAS("platform:tmio-nand");
532