1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Intel PCH/PCU SPI flash driver.
4 *
5 * Copyright (C) 2016, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 */
8
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/sizes.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/mtd/spi-nor.h>
18 #include <linux/platform_data/intel-spi.h>
19
20 #include "intel-spi.h"
21
22 /* Offsets are from @ispi->base */
23 #define BFPREG 0x00
24
25 #define HSFSTS_CTL 0x04
26 #define HSFSTS_CTL_FSMIE BIT(31)
27 #define HSFSTS_CTL_FDBC_SHIFT 24
28 #define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT)
29
30 #define HSFSTS_CTL_FCYCLE_SHIFT 17
31 #define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT)
32 /* HW sequencer opcodes */
33 #define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT)
34 #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
35 #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
36 #define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
37 #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
38 #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
39 #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
40
41 #define HSFSTS_CTL_FGO BIT(16)
42 #define HSFSTS_CTL_FLOCKDN BIT(15)
43 #define HSFSTS_CTL_FDV BIT(14)
44 #define HSFSTS_CTL_SCIP BIT(5)
45 #define HSFSTS_CTL_AEL BIT(2)
46 #define HSFSTS_CTL_FCERR BIT(1)
47 #define HSFSTS_CTL_FDONE BIT(0)
48
49 #define FADDR 0x08
50 #define DLOCK 0x0c
51 #define FDATA(n) (0x10 + ((n) * 4))
52
53 #define FRACC 0x50
54
55 #define FREG(n) (0x54 + ((n) * 4))
56 #define FREG_BASE_MASK 0x3fff
57 #define FREG_LIMIT_SHIFT 16
58 #define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT)
59
60 /* Offset is from @ispi->pregs */
61 #define PR(n) ((n) * 4)
62 #define PR_WPE BIT(31)
63 #define PR_LIMIT_SHIFT 16
64 #define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT)
65 #define PR_RPE BIT(15)
66 #define PR_BASE_MASK 0x3fff
67
68 /* Offsets are from @ispi->sregs */
69 #define SSFSTS_CTL 0x00
70 #define SSFSTS_CTL_FSMIE BIT(23)
71 #define SSFSTS_CTL_DS BIT(22)
72 #define SSFSTS_CTL_DBC_SHIFT 16
73 #define SSFSTS_CTL_SPOP BIT(11)
74 #define SSFSTS_CTL_ACS BIT(10)
75 #define SSFSTS_CTL_SCGO BIT(9)
76 #define SSFSTS_CTL_COP_SHIFT 12
77 #define SSFSTS_CTL_FRS BIT(7)
78 #define SSFSTS_CTL_DOFRS BIT(6)
79 #define SSFSTS_CTL_AEL BIT(4)
80 #define SSFSTS_CTL_FCERR BIT(3)
81 #define SSFSTS_CTL_FDONE BIT(2)
82 #define SSFSTS_CTL_SCIP BIT(0)
83
84 #define PREOP_OPTYPE 0x04
85 #define OPMENU0 0x08
86 #define OPMENU1 0x0c
87
88 #define OPTYPE_READ_NO_ADDR 0
89 #define OPTYPE_WRITE_NO_ADDR 1
90 #define OPTYPE_READ_WITH_ADDR 2
91 #define OPTYPE_WRITE_WITH_ADDR 3
92
93 /* CPU specifics */
94 #define BYT_PR 0x74
95 #define BYT_SSFSTS_CTL 0x90
96 #define BYT_BCR 0xfc
97 #define BYT_BCR_WPD BIT(0)
98 #define BYT_FREG_NUM 5
99 #define BYT_PR_NUM 5
100
101 #define LPT_PR 0x74
102 #define LPT_SSFSTS_CTL 0x90
103 #define LPT_FREG_NUM 5
104 #define LPT_PR_NUM 5
105
106 #define BXT_PR 0x84
107 #define BXT_SSFSTS_CTL 0xa0
108 #define BXT_FREG_NUM 12
109 #define BXT_PR_NUM 6
110
111 #define CNL_PR 0x84
112 #define CNL_FREG_NUM 6
113 #define CNL_PR_NUM 5
114
115 #define LVSCC 0xc4
116 #define UVSCC 0xc8
117 #define ERASE_OPCODE_SHIFT 8
118 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
119 #define ERASE_64K_OPCODE_SHIFT 16
120 #define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
121
122 #define INTEL_SPI_TIMEOUT 5000 /* ms */
123 #define INTEL_SPI_FIFO_SZ 64
124
125 /**
126 * struct intel_spi - Driver private data
127 * @dev: Device pointer
128 * @info: Pointer to board specific info
129 * @nor: SPI NOR layer structure
130 * @base: Beginning of MMIO space
131 * @pregs: Start of protection registers
132 * @sregs: Start of software sequencer registers
133 * @nregions: Maximum number of regions
134 * @pr_num: Maximum number of protected range registers
135 * @writeable: Is the chip writeable
136 * @locked: Is SPI setting locked
137 * @swseq_reg: Use SW sequencer in register reads/writes
138 * @swseq_erase: Use SW sequencer in erase operation
139 * @erase_64k: 64k erase supported
140 * @atomic_preopcode: Holds preopcode when atomic sequence is requested
141 * @opcodes: Opcodes which are supported. This are programmed by BIOS
142 * before it locks down the controller.
143 */
144 struct intel_spi {
145 struct device *dev;
146 const struct intel_spi_boardinfo *info;
147 struct spi_nor nor;
148 void __iomem *base;
149 void __iomem *pregs;
150 void __iomem *sregs;
151 size_t nregions;
152 size_t pr_num;
153 bool writeable;
154 bool locked;
155 bool swseq_reg;
156 bool swseq_erase;
157 bool erase_64k;
158 u8 atomic_preopcode;
159 u8 opcodes[8];
160 };
161
162 static bool writeable;
163 module_param(writeable, bool, 0);
164 MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)");
165
intel_spi_dump_regs(struct intel_spi * ispi)166 static void intel_spi_dump_regs(struct intel_spi *ispi)
167 {
168 u32 value;
169 int i;
170
171 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));
172
173 value = readl(ispi->base + HSFSTS_CTL);
174 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);
175 if (value & HSFSTS_CTL_FLOCKDN)
176 dev_dbg(ispi->dev, "-> Locked\n");
177
178 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));
179 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));
180
181 for (i = 0; i < 16; i++)
182 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",
183 i, readl(ispi->base + FDATA(i)));
184
185 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));
186
187 for (i = 0; i < ispi->nregions; i++)
188 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,
189 readl(ispi->base + FREG(i)));
190 for (i = 0; i < ispi->pr_num; i++)
191 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
192 readl(ispi->pregs + PR(i)));
193
194 if (ispi->sregs) {
195 value = readl(ispi->sregs + SSFSTS_CTL);
196 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
197 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
198 readl(ispi->sregs + PREOP_OPTYPE));
199 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n",
200 readl(ispi->sregs + OPMENU0));
201 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n",
202 readl(ispi->sregs + OPMENU1));
203 }
204
205 if (ispi->info->type == INTEL_SPI_BYT)
206 dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR));
207
208 dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));
209 dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));
210
211 dev_dbg(ispi->dev, "Protected regions:\n");
212 for (i = 0; i < ispi->pr_num; i++) {
213 u32 base, limit;
214
215 value = readl(ispi->pregs + PR(i));
216 if (!(value & (PR_WPE | PR_RPE)))
217 continue;
218
219 limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
220 base = value & PR_BASE_MASK;
221
222 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
223 i, base << 12, (limit << 12) | 0xfff,
224 value & PR_WPE ? 'W' : '.',
225 value & PR_RPE ? 'R' : '.');
226 }
227
228 dev_dbg(ispi->dev, "Flash regions:\n");
229 for (i = 0; i < ispi->nregions; i++) {
230 u32 region, base, limit;
231
232 region = readl(ispi->base + FREG(i));
233 base = region & FREG_BASE_MASK;
234 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
235
236 if (base >= limit || (i > 0 && limit == 0))
237 dev_dbg(ispi->dev, " %02d disabled\n", i);
238 else
239 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",
240 i, base << 12, (limit << 12) | 0xfff);
241 }
242
243 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
244 ispi->swseq_reg ? 'S' : 'H');
245 dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",
246 ispi->swseq_erase ? 'S' : 'H');
247 }
248
249 /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */
intel_spi_read_block(struct intel_spi * ispi,void * buf,size_t size)250 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)
251 {
252 size_t bytes;
253 int i = 0;
254
255 if (size > INTEL_SPI_FIFO_SZ)
256 return -EINVAL;
257
258 while (size > 0) {
259 bytes = min_t(size_t, size, 4);
260 memcpy_fromio(buf, ispi->base + FDATA(i), bytes);
261 size -= bytes;
262 buf += bytes;
263 i++;
264 }
265
266 return 0;
267 }
268
269 /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */
intel_spi_write_block(struct intel_spi * ispi,const void * buf,size_t size)270 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,
271 size_t size)
272 {
273 size_t bytes;
274 int i = 0;
275
276 if (size > INTEL_SPI_FIFO_SZ)
277 return -EINVAL;
278
279 while (size > 0) {
280 bytes = min_t(size_t, size, 4);
281 memcpy_toio(ispi->base + FDATA(i), buf, bytes);
282 size -= bytes;
283 buf += bytes;
284 i++;
285 }
286
287 return 0;
288 }
289
intel_spi_wait_hw_busy(struct intel_spi * ispi)290 static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
291 {
292 u32 val;
293
294 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
295 !(val & HSFSTS_CTL_SCIP), 0,
296 INTEL_SPI_TIMEOUT * 1000);
297 }
298
intel_spi_wait_sw_busy(struct intel_spi * ispi)299 static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
300 {
301 u32 val;
302
303 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
304 !(val & SSFSTS_CTL_SCIP), 0,
305 INTEL_SPI_TIMEOUT * 1000);
306 }
307
intel_spi_init(struct intel_spi * ispi)308 static int intel_spi_init(struct intel_spi *ispi)
309 {
310 u32 opmenu0, opmenu1, lvscc, uvscc, val;
311 int i;
312
313 switch (ispi->info->type) {
314 case INTEL_SPI_BYT:
315 ispi->sregs = ispi->base + BYT_SSFSTS_CTL;
316 ispi->pregs = ispi->base + BYT_PR;
317 ispi->nregions = BYT_FREG_NUM;
318 ispi->pr_num = BYT_PR_NUM;
319 ispi->swseq_reg = true;
320
321 if (writeable) {
322 /* Disable write protection */
323 val = readl(ispi->base + BYT_BCR);
324 if (!(val & BYT_BCR_WPD)) {
325 val |= BYT_BCR_WPD;
326 writel(val, ispi->base + BYT_BCR);
327 val = readl(ispi->base + BYT_BCR);
328 }
329
330 ispi->writeable = !!(val & BYT_BCR_WPD);
331 }
332
333 break;
334
335 case INTEL_SPI_LPT:
336 ispi->sregs = ispi->base + LPT_SSFSTS_CTL;
337 ispi->pregs = ispi->base + LPT_PR;
338 ispi->nregions = LPT_FREG_NUM;
339 ispi->pr_num = LPT_PR_NUM;
340 ispi->swseq_reg = true;
341 break;
342
343 case INTEL_SPI_BXT:
344 ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
345 ispi->pregs = ispi->base + BXT_PR;
346 ispi->nregions = BXT_FREG_NUM;
347 ispi->pr_num = BXT_PR_NUM;
348 ispi->erase_64k = true;
349 break;
350
351 case INTEL_SPI_CNL:
352 ispi->sregs = NULL;
353 ispi->pregs = ispi->base + CNL_PR;
354 ispi->nregions = CNL_FREG_NUM;
355 ispi->pr_num = CNL_PR_NUM;
356 break;
357
358 default:
359 return -EINVAL;
360 }
361
362 /* Disable #SMI generation from HW sequencer */
363 val = readl(ispi->base + HSFSTS_CTL);
364 val &= ~HSFSTS_CTL_FSMIE;
365 writel(val, ispi->base + HSFSTS_CTL);
366
367 /*
368 * Determine whether erase operation should use HW or SW sequencer.
369 *
370 * The HW sequencer has a predefined list of opcodes, with only the
371 * erase opcode being programmable in LVSCC and UVSCC registers.
372 * If these registers don't contain a valid erase opcode, erase
373 * cannot be done using HW sequencer.
374 */
375 lvscc = readl(ispi->base + LVSCC);
376 uvscc = readl(ispi->base + UVSCC);
377 if (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK))
378 ispi->swseq_erase = true;
379 /* SPI controller on Intel BXT supports 64K erase opcode */
380 if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)
381 if (!(lvscc & ERASE_64K_OPCODE_MASK) ||
382 !(uvscc & ERASE_64K_OPCODE_MASK))
383 ispi->erase_64k = false;
384
385 if (ispi->sregs == NULL && (ispi->swseq_reg || ispi->swseq_erase)) {
386 dev_err(ispi->dev, "software sequencer not supported, but required\n");
387 return -EINVAL;
388 }
389
390 /*
391 * Some controllers can only do basic operations using hardware
392 * sequencer. All other operations are supposed to be carried out
393 * using software sequencer.
394 */
395 if (ispi->swseq_reg) {
396 /* Disable #SMI generation from SW sequencer */
397 val = readl(ispi->sregs + SSFSTS_CTL);
398 val &= ~SSFSTS_CTL_FSMIE;
399 writel(val, ispi->sregs + SSFSTS_CTL);
400 }
401
402 /* Check controller's lock status */
403 val = readl(ispi->base + HSFSTS_CTL);
404 ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);
405
406 if (ispi->locked && ispi->sregs) {
407 /*
408 * BIOS programs allowed opcodes and then locks down the
409 * register. So read back what opcodes it decided to support.
410 * That's the set we are going to support as well.
411 */
412 opmenu0 = readl(ispi->sregs + OPMENU0);
413 opmenu1 = readl(ispi->sregs + OPMENU1);
414
415 if (opmenu0 && opmenu1) {
416 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {
417 ispi->opcodes[i] = opmenu0 >> i * 8;
418 ispi->opcodes[i + 4] = opmenu1 >> i * 8;
419 }
420 }
421 }
422
423 intel_spi_dump_regs(ispi);
424
425 return 0;
426 }
427
intel_spi_opcode_index(struct intel_spi * ispi,u8 opcode,int optype)428 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)
429 {
430 int i;
431 int preop;
432
433 if (ispi->locked) {
434 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)
435 if (ispi->opcodes[i] == opcode)
436 return i;
437
438 return -EINVAL;
439 }
440
441 /* The lock is off, so just use index 0 */
442 writel(opcode, ispi->sregs + OPMENU0);
443 preop = readw(ispi->sregs + PREOP_OPTYPE);
444 writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);
445
446 return 0;
447 }
448
intel_spi_hw_cycle(struct intel_spi * ispi,u8 opcode,size_t len)449 static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len)
450 {
451 u32 val, status;
452 int ret;
453
454 val = readl(ispi->base + HSFSTS_CTL);
455 val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);
456
457 switch (opcode) {
458 case SPINOR_OP_RDID:
459 val |= HSFSTS_CTL_FCYCLE_RDID;
460 break;
461 case SPINOR_OP_WRSR:
462 val |= HSFSTS_CTL_FCYCLE_WRSR;
463 break;
464 case SPINOR_OP_RDSR:
465 val |= HSFSTS_CTL_FCYCLE_RDSR;
466 break;
467 default:
468 return -EINVAL;
469 }
470
471 if (len > INTEL_SPI_FIFO_SZ)
472 return -EINVAL;
473
474 val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;
475 val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
476 val |= HSFSTS_CTL_FGO;
477 writel(val, ispi->base + HSFSTS_CTL);
478
479 ret = intel_spi_wait_hw_busy(ispi);
480 if (ret)
481 return ret;
482
483 status = readl(ispi->base + HSFSTS_CTL);
484 if (status & HSFSTS_CTL_FCERR)
485 return -EIO;
486 else if (status & HSFSTS_CTL_AEL)
487 return -EACCES;
488
489 return 0;
490 }
491
intel_spi_sw_cycle(struct intel_spi * ispi,u8 opcode,size_t len,int optype)492 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len,
493 int optype)
494 {
495 u32 val = 0, status;
496 u8 atomic_preopcode;
497 int ret;
498
499 ret = intel_spi_opcode_index(ispi, opcode, optype);
500 if (ret < 0)
501 return ret;
502
503 if (len > INTEL_SPI_FIFO_SZ)
504 return -EINVAL;
505
506 /*
507 * Always clear it after each SW sequencer operation regardless
508 * of whether it is successful or not.
509 */
510 atomic_preopcode = ispi->atomic_preopcode;
511 ispi->atomic_preopcode = 0;
512
513 /* Only mark 'Data Cycle' bit when there is data to be transferred */
514 if (len > 0)
515 val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;
516 val |= ret << SSFSTS_CTL_COP_SHIFT;
517 val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;
518 val |= SSFSTS_CTL_SCGO;
519 if (atomic_preopcode) {
520 u16 preop;
521
522 switch (optype) {
523 case OPTYPE_WRITE_NO_ADDR:
524 case OPTYPE_WRITE_WITH_ADDR:
525 /* Pick matching preopcode for the atomic sequence */
526 preop = readw(ispi->sregs + PREOP_OPTYPE);
527 if ((preop & 0xff) == atomic_preopcode)
528 ; /* Do nothing */
529 else if ((preop >> 8) == atomic_preopcode)
530 val |= SSFSTS_CTL_SPOP;
531 else
532 return -EINVAL;
533
534 /* Enable atomic sequence */
535 val |= SSFSTS_CTL_ACS;
536 break;
537
538 default:
539 return -EINVAL;
540 }
541
542 }
543 writel(val, ispi->sregs + SSFSTS_CTL);
544
545 ret = intel_spi_wait_sw_busy(ispi);
546 if (ret)
547 return ret;
548
549 status = readl(ispi->sregs + SSFSTS_CTL);
550 if (status & SSFSTS_CTL_FCERR)
551 return -EIO;
552 else if (status & SSFSTS_CTL_AEL)
553 return -EACCES;
554
555 return 0;
556 }
557
intel_spi_read_reg(struct spi_nor * nor,u8 opcode,u8 * buf,size_t len)558 static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
559 size_t len)
560 {
561 struct intel_spi *ispi = nor->priv;
562 int ret;
563
564 /* Address of the first chip */
565 writel(0, ispi->base + FADDR);
566
567 if (ispi->swseq_reg)
568 ret = intel_spi_sw_cycle(ispi, opcode, len,
569 OPTYPE_READ_NO_ADDR);
570 else
571 ret = intel_spi_hw_cycle(ispi, opcode, len);
572
573 if (ret)
574 return ret;
575
576 return intel_spi_read_block(ispi, buf, len);
577 }
578
intel_spi_write_reg(struct spi_nor * nor,u8 opcode,const u8 * buf,size_t len)579 static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
580 size_t len)
581 {
582 struct intel_spi *ispi = nor->priv;
583 int ret;
584
585 /*
586 * This is handled with atomic operation and preop code in Intel
587 * controller so we only verify that it is available. If the
588 * controller is not locked, program the opcode to the PREOP
589 * register for later use.
590 *
591 * When hardware sequencer is used there is no need to program
592 * any opcodes (it handles them automatically as part of a command).
593 */
594 if (opcode == SPINOR_OP_WREN) {
595 u16 preop;
596
597 if (!ispi->swseq_reg)
598 return 0;
599
600 preop = readw(ispi->sregs + PREOP_OPTYPE);
601 if ((preop & 0xff) != opcode && (preop >> 8) != opcode) {
602 if (ispi->locked)
603 return -EINVAL;
604 writel(opcode, ispi->sregs + PREOP_OPTYPE);
605 }
606
607 /*
608 * This enables atomic sequence on next SW sycle. Will
609 * be cleared after next operation.
610 */
611 ispi->atomic_preopcode = opcode;
612 return 0;
613 }
614
615 /*
616 * We hope that HW sequencer will do the right thing automatically and
617 * with the SW sequencer we cannot use preopcode anyway, so just ignore
618 * the Write Disable operation and pretend it was completed
619 * successfully.
620 */
621 if (opcode == SPINOR_OP_WRDI)
622 return 0;
623
624 writel(0, ispi->base + FADDR);
625
626 /* Write the value beforehand */
627 ret = intel_spi_write_block(ispi, buf, len);
628 if (ret)
629 return ret;
630
631 if (ispi->swseq_reg)
632 return intel_spi_sw_cycle(ispi, opcode, len,
633 OPTYPE_WRITE_NO_ADDR);
634 return intel_spi_hw_cycle(ispi, opcode, len);
635 }
636
intel_spi_read(struct spi_nor * nor,loff_t from,size_t len,u_char * read_buf)637 static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
638 u_char *read_buf)
639 {
640 struct intel_spi *ispi = nor->priv;
641 size_t block_size, retlen = 0;
642 u32 val, status;
643 ssize_t ret;
644
645 /*
646 * Atomic sequence is not expected with HW sequencer reads. Make
647 * sure it is cleared regardless.
648 */
649 if (WARN_ON_ONCE(ispi->atomic_preopcode))
650 ispi->atomic_preopcode = 0;
651
652 switch (nor->read_opcode) {
653 case SPINOR_OP_READ:
654 case SPINOR_OP_READ_FAST:
655 case SPINOR_OP_READ_4B:
656 case SPINOR_OP_READ_FAST_4B:
657 break;
658 default:
659 return -EINVAL;
660 }
661
662 while (len > 0) {
663 block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
664
665 /* Read cannot cross 4K boundary */
666 block_size = min_t(loff_t, from + block_size,
667 round_up(from + 1, SZ_4K)) - from;
668
669 writel(from, ispi->base + FADDR);
670
671 val = readl(ispi->base + HSFSTS_CTL);
672 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
673 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
674 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
675 val |= HSFSTS_CTL_FCYCLE_READ;
676 val |= HSFSTS_CTL_FGO;
677 writel(val, ispi->base + HSFSTS_CTL);
678
679 ret = intel_spi_wait_hw_busy(ispi);
680 if (ret)
681 return ret;
682
683 status = readl(ispi->base + HSFSTS_CTL);
684 if (status & HSFSTS_CTL_FCERR)
685 ret = -EIO;
686 else if (status & HSFSTS_CTL_AEL)
687 ret = -EACCES;
688
689 if (ret < 0) {
690 dev_err(ispi->dev, "read error: %llx: %#x\n", from,
691 status);
692 return ret;
693 }
694
695 ret = intel_spi_read_block(ispi, read_buf, block_size);
696 if (ret)
697 return ret;
698
699 len -= block_size;
700 from += block_size;
701 retlen += block_size;
702 read_buf += block_size;
703 }
704
705 return retlen;
706 }
707
intel_spi_write(struct spi_nor * nor,loff_t to,size_t len,const u_char * write_buf)708 static ssize_t intel_spi_write(struct spi_nor *nor, loff_t to, size_t len,
709 const u_char *write_buf)
710 {
711 struct intel_spi *ispi = nor->priv;
712 size_t block_size, retlen = 0;
713 u32 val, status;
714 ssize_t ret;
715
716 /* Not needed with HW sequencer write, make sure it is cleared */
717 ispi->atomic_preopcode = 0;
718
719 while (len > 0) {
720 block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
721
722 /* Write cannot cross 4K boundary */
723 block_size = min_t(loff_t, to + block_size,
724 round_up(to + 1, SZ_4K)) - to;
725
726 writel(to, ispi->base + FADDR);
727
728 val = readl(ispi->base + HSFSTS_CTL);
729 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
730 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
731 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
732 val |= HSFSTS_CTL_FCYCLE_WRITE;
733
734 ret = intel_spi_write_block(ispi, write_buf, block_size);
735 if (ret) {
736 dev_err(ispi->dev, "failed to write block\n");
737 return ret;
738 }
739
740 /* Start the write now */
741 val |= HSFSTS_CTL_FGO;
742 writel(val, ispi->base + HSFSTS_CTL);
743
744 ret = intel_spi_wait_hw_busy(ispi);
745 if (ret) {
746 dev_err(ispi->dev, "timeout\n");
747 return ret;
748 }
749
750 status = readl(ispi->base + HSFSTS_CTL);
751 if (status & HSFSTS_CTL_FCERR)
752 ret = -EIO;
753 else if (status & HSFSTS_CTL_AEL)
754 ret = -EACCES;
755
756 if (ret < 0) {
757 dev_err(ispi->dev, "write error: %llx: %#x\n", to,
758 status);
759 return ret;
760 }
761
762 len -= block_size;
763 to += block_size;
764 retlen += block_size;
765 write_buf += block_size;
766 }
767
768 return retlen;
769 }
770
intel_spi_erase(struct spi_nor * nor,loff_t offs)771 static int intel_spi_erase(struct spi_nor *nor, loff_t offs)
772 {
773 size_t erase_size, len = nor->mtd.erasesize;
774 struct intel_spi *ispi = nor->priv;
775 u32 val, status, cmd;
776 int ret;
777
778 /* If the hardware can do 64k erase use that when possible */
779 if (len >= SZ_64K && ispi->erase_64k) {
780 cmd = HSFSTS_CTL_FCYCLE_ERASE_64K;
781 erase_size = SZ_64K;
782 } else {
783 cmd = HSFSTS_CTL_FCYCLE_ERASE;
784 erase_size = SZ_4K;
785 }
786
787 if (ispi->swseq_erase) {
788 while (len > 0) {
789 writel(offs, ispi->base + FADDR);
790
791 ret = intel_spi_sw_cycle(ispi, nor->erase_opcode,
792 0, OPTYPE_WRITE_WITH_ADDR);
793 if (ret)
794 return ret;
795
796 offs += erase_size;
797 len -= erase_size;
798 }
799
800 return 0;
801 }
802
803 /* Not needed with HW sequencer erase, make sure it is cleared */
804 ispi->atomic_preopcode = 0;
805
806 while (len > 0) {
807 writel(offs, ispi->base + FADDR);
808
809 val = readl(ispi->base + HSFSTS_CTL);
810 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
811 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
812 val |= cmd;
813 val |= HSFSTS_CTL_FGO;
814 writel(val, ispi->base + HSFSTS_CTL);
815
816 ret = intel_spi_wait_hw_busy(ispi);
817 if (ret)
818 return ret;
819
820 status = readl(ispi->base + HSFSTS_CTL);
821 if (status & HSFSTS_CTL_FCERR)
822 return -EIO;
823 else if (status & HSFSTS_CTL_AEL)
824 return -EACCES;
825
826 offs += erase_size;
827 len -= erase_size;
828 }
829
830 return 0;
831 }
832
intel_spi_is_protected(const struct intel_spi * ispi,unsigned int base,unsigned int limit)833 static bool intel_spi_is_protected(const struct intel_spi *ispi,
834 unsigned int base, unsigned int limit)
835 {
836 int i;
837
838 for (i = 0; i < ispi->pr_num; i++) {
839 u32 pr_base, pr_limit, pr_value;
840
841 pr_value = readl(ispi->pregs + PR(i));
842 if (!(pr_value & (PR_WPE | PR_RPE)))
843 continue;
844
845 pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
846 pr_base = pr_value & PR_BASE_MASK;
847
848 if (pr_base >= base && pr_limit <= limit)
849 return true;
850 }
851
852 return false;
853 }
854
855 /*
856 * There will be a single partition holding all enabled flash regions. We
857 * call this "BIOS".
858 */
intel_spi_fill_partition(struct intel_spi * ispi,struct mtd_partition * part)859 static void intel_spi_fill_partition(struct intel_spi *ispi,
860 struct mtd_partition *part)
861 {
862 u64 end;
863 int i;
864
865 memset(part, 0, sizeof(*part));
866
867 /* Start from the mandatory descriptor region */
868 part->size = 4096;
869 part->name = "BIOS";
870
871 /*
872 * Now try to find where this partition ends based on the flash
873 * region registers.
874 */
875 for (i = 1; i < ispi->nregions; i++) {
876 u32 region, base, limit;
877
878 region = readl(ispi->base + FREG(i));
879 base = region & FREG_BASE_MASK;
880 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
881
882 if (base >= limit || limit == 0)
883 continue;
884
885 /*
886 * If any of the regions have protection bits set, make the
887 * whole partition read-only to be on the safe side.
888 */
889 if (intel_spi_is_protected(ispi, base, limit))
890 ispi->writeable = false;
891
892 end = (limit << 12) + 4096;
893 if (end > part->size)
894 part->size = end;
895 }
896 }
897
898 static const struct spi_nor_controller_ops intel_spi_controller_ops = {
899 .read_reg = intel_spi_read_reg,
900 .write_reg = intel_spi_write_reg,
901 .read = intel_spi_read,
902 .write = intel_spi_write,
903 .erase = intel_spi_erase,
904 };
905
intel_spi_probe(struct device * dev,struct resource * mem,const struct intel_spi_boardinfo * info)906 struct intel_spi *intel_spi_probe(struct device *dev,
907 struct resource *mem, const struct intel_spi_boardinfo *info)
908 {
909 const struct spi_nor_hwcaps hwcaps = {
910 .mask = SNOR_HWCAPS_READ |
911 SNOR_HWCAPS_READ_FAST |
912 SNOR_HWCAPS_PP,
913 };
914 struct mtd_partition part;
915 struct intel_spi *ispi;
916 int ret;
917
918 if (!info || !mem)
919 return ERR_PTR(-EINVAL);
920
921 ispi = devm_kzalloc(dev, sizeof(*ispi), GFP_KERNEL);
922 if (!ispi)
923 return ERR_PTR(-ENOMEM);
924
925 ispi->base = devm_ioremap_resource(dev, mem);
926 if (IS_ERR(ispi->base))
927 return ERR_CAST(ispi->base);
928
929 ispi->dev = dev;
930 ispi->info = info;
931 ispi->writeable = info->writeable;
932
933 ret = intel_spi_init(ispi);
934 if (ret)
935 return ERR_PTR(ret);
936
937 ispi->nor.dev = ispi->dev;
938 ispi->nor.priv = ispi;
939 ispi->nor.controller_ops = &intel_spi_controller_ops;
940
941 ret = spi_nor_scan(&ispi->nor, NULL, &hwcaps);
942 if (ret) {
943 dev_info(dev, "failed to locate the chip\n");
944 return ERR_PTR(ret);
945 }
946
947 intel_spi_fill_partition(ispi, &part);
948
949 /* Prevent writes if not explicitly enabled */
950 if (!ispi->writeable || !writeable)
951 ispi->nor.mtd.flags &= ~MTD_WRITEABLE;
952
953 ret = mtd_device_register(&ispi->nor.mtd, &part, 1);
954 if (ret)
955 return ERR_PTR(ret);
956
957 return ispi;
958 }
959 EXPORT_SYMBOL_GPL(intel_spi_probe);
960
intel_spi_remove(struct intel_spi * ispi)961 int intel_spi_remove(struct intel_spi *ispi)
962 {
963 return mtd_device_unregister(&ispi->nor.mtd);
964 }
965 EXPORT_SYMBOL_GPL(intel_spi_remove);
966
967 MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver");
968 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
969 MODULE_LICENSE("GPL v2");
970