1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Broadcom Starfighter 2 DSA switch driver
4 *
5 * Copyright (C) 2014, Broadcom Corporation
6 */
7
8 #include <linux/list.h>
9 #include <linux/module.h>
10 #include <linux/netdevice.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <linux/phy.h>
14 #include <linux/phy_fixed.h>
15 #include <linux/phylink.h>
16 #include <linux/mii.h>
17 #include <linux/clk.h>
18 #include <linux/of.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_address.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <net/dsa.h>
24 #include <linux/ethtool.h>
25 #include <linux/if_bridge.h>
26 #include <linux/brcmphy.h>
27 #include <linux/etherdevice.h>
28 #include <linux/platform_data/b53.h>
29
30 #include "bcm_sf2.h"
31 #include "bcm_sf2_regs.h"
32 #include "b53/b53_priv.h"
33 #include "b53/b53_regs.h"
34
35 /* Return the number of active ports, not counting the IMP (CPU) port */
bcm_sf2_num_active_ports(struct dsa_switch * ds)36 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
37 {
38 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
39 unsigned int port, count = 0;
40
41 for (port = 0; port < ds->num_ports; port++) {
42 if (dsa_is_cpu_port(ds, port))
43 continue;
44 if (priv->port_sts[port].enabled)
45 count++;
46 }
47
48 return count;
49 }
50
bcm_sf2_recalc_clock(struct dsa_switch * ds)51 static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
52 {
53 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
54 unsigned long new_rate;
55 unsigned int ports_active;
56 /* Frequenty in Mhz */
57 static const unsigned long rate_table[] = {
58 59220000,
59 60820000,
60 62500000,
61 62500000,
62 };
63
64 ports_active = bcm_sf2_num_active_ports(ds);
65 if (ports_active == 0 || !priv->clk_mdiv)
66 return;
67
68 /* If we overflow our table, just use the recommended operational
69 * frequency
70 */
71 if (ports_active > ARRAY_SIZE(rate_table))
72 new_rate = 90000000;
73 else
74 new_rate = rate_table[ports_active - 1];
75 clk_set_rate(priv->clk_mdiv, new_rate);
76 }
77
bcm_sf2_imp_setup(struct dsa_switch * ds,int port)78 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
79 {
80 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
81 unsigned int i;
82 u32 reg, offset;
83
84 /* Enable the port memories */
85 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
86 reg &= ~P_TXQ_PSM_VDD(port);
87 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
88
89 /* Enable forwarding */
90 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
91
92 /* Enable IMP port in dumb mode */
93 reg = core_readl(priv, CORE_SWITCH_CTRL);
94 reg |= MII_DUMB_FWDG_EN;
95 core_writel(priv, reg, CORE_SWITCH_CTRL);
96
97 /* Configure Traffic Class to QoS mapping, allow each priority to map
98 * to a different queue number
99 */
100 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
101 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
102 reg |= i << (PRT_TO_QID_SHIFT * i);
103 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
104
105 b53_brcm_hdr_setup(ds, port);
106
107 if (port == 8) {
108 if (priv->type == BCM7445_DEVICE_ID)
109 offset = CORE_STS_OVERRIDE_IMP;
110 else
111 offset = CORE_STS_OVERRIDE_IMP2;
112
113 /* Force link status for IMP port */
114 reg = core_readl(priv, offset);
115 reg |= (MII_SW_OR | LINK_STS);
116 reg &= ~GMII_SPEED_UP_2G;
117 core_writel(priv, reg, offset);
118
119 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
120 reg = core_readl(priv, CORE_IMP_CTL);
121 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
122 reg &= ~(RX_DIS | TX_DIS);
123 core_writel(priv, reg, CORE_IMP_CTL);
124 } else {
125 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
126 reg &= ~(RX_DIS | TX_DIS);
127 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
128 }
129
130 priv->port_sts[port].enabled = true;
131 }
132
bcm_sf2_gphy_enable_set(struct dsa_switch * ds,bool enable)133 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
134 {
135 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
136 u32 reg;
137
138 reg = reg_readl(priv, REG_SPHY_CNTRL);
139 if (enable) {
140 reg |= PHY_RESET;
141 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
142 reg_writel(priv, reg, REG_SPHY_CNTRL);
143 udelay(21);
144 reg = reg_readl(priv, REG_SPHY_CNTRL);
145 reg &= ~PHY_RESET;
146 } else {
147 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
148 reg_writel(priv, reg, REG_SPHY_CNTRL);
149 mdelay(1);
150 reg |= CK25_DIS;
151 }
152 reg_writel(priv, reg, REG_SPHY_CNTRL);
153
154 /* Use PHY-driven LED signaling */
155 if (!enable) {
156 reg = reg_readl(priv, REG_LED_CNTRL(0));
157 reg |= SPDLNK_SRC_SEL;
158 reg_writel(priv, reg, REG_LED_CNTRL(0));
159 }
160 }
161
bcm_sf2_port_intr_enable(struct bcm_sf2_priv * priv,int port)162 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
163 int port)
164 {
165 unsigned int off;
166
167 switch (port) {
168 case 7:
169 off = P7_IRQ_OFF;
170 break;
171 case 0:
172 /* Port 0 interrupts are located on the first bank */
173 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
174 return;
175 default:
176 off = P_IRQ_OFF(port);
177 break;
178 }
179
180 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
181 }
182
bcm_sf2_port_intr_disable(struct bcm_sf2_priv * priv,int port)183 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
184 int port)
185 {
186 unsigned int off;
187
188 switch (port) {
189 case 7:
190 off = P7_IRQ_OFF;
191 break;
192 case 0:
193 /* Port 0 interrupts are located on the first bank */
194 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
195 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
196 return;
197 default:
198 off = P_IRQ_OFF(port);
199 break;
200 }
201
202 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
203 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
204 }
205
bcm_sf2_port_setup(struct dsa_switch * ds,int port,struct phy_device * phy)206 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
207 struct phy_device *phy)
208 {
209 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
210 unsigned int i;
211 u32 reg;
212
213 if (!dsa_is_user_port(ds, port))
214 return 0;
215
216 priv->port_sts[port].enabled = true;
217
218 bcm_sf2_recalc_clock(ds);
219
220 /* Clear the memory power down */
221 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
222 reg &= ~P_TXQ_PSM_VDD(port);
223 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
224
225 /* Enable Broadcom tags for that port if requested */
226 if (priv->brcm_tag_mask & BIT(port))
227 b53_brcm_hdr_setup(ds, port);
228
229 /* Configure Traffic Class to QoS mapping, allow each priority to map
230 * to a different queue number
231 */
232 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
233 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
234 reg |= i << (PRT_TO_QID_SHIFT * i);
235 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
236
237 /* Re-enable the GPHY and re-apply workarounds */
238 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
239 bcm_sf2_gphy_enable_set(ds, true);
240 if (phy) {
241 /* if phy_stop() has been called before, phy
242 * will be in halted state, and phy_start()
243 * will call resume.
244 *
245 * the resume path does not configure back
246 * autoneg settings, and since we hard reset
247 * the phy manually here, we need to reset the
248 * state machine also.
249 */
250 phy->state = PHY_READY;
251 phy_init_hw(phy);
252 }
253 }
254
255 /* Enable MoCA port interrupts to get notified */
256 if (port == priv->moca_port)
257 bcm_sf2_port_intr_enable(priv, port);
258
259 /* Set per-queue pause threshold to 32 */
260 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
261
262 /* Set ACB threshold to 24 */
263 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
264 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
265 SF2_NUM_EGRESS_QUEUES + i));
266 reg &= ~XOFF_THRESHOLD_MASK;
267 reg |= 24;
268 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
269 SF2_NUM_EGRESS_QUEUES + i));
270 }
271
272 return b53_enable_port(ds, port, phy);
273 }
274
bcm_sf2_port_disable(struct dsa_switch * ds,int port)275 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
276 {
277 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
278 u32 reg;
279
280 /* Disable learning while in WoL mode */
281 if (priv->wol_ports_mask & (1 << port)) {
282 reg = core_readl(priv, CORE_DIS_LEARN);
283 reg |= BIT(port);
284 core_writel(priv, reg, CORE_DIS_LEARN);
285 return;
286 }
287
288 if (port == priv->moca_port)
289 bcm_sf2_port_intr_disable(priv, port);
290
291 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
292 bcm_sf2_gphy_enable_set(ds, false);
293
294 b53_disable_port(ds, port);
295
296 /* Power down the port memory */
297 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
298 reg |= P_TXQ_PSM_VDD(port);
299 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
300
301 priv->port_sts[port].enabled = false;
302
303 bcm_sf2_recalc_clock(ds);
304 }
305
306
bcm_sf2_sw_indir_rw(struct bcm_sf2_priv * priv,int op,int addr,int regnum,u16 val)307 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
308 int regnum, u16 val)
309 {
310 int ret = 0;
311 u32 reg;
312
313 reg = reg_readl(priv, REG_SWITCH_CNTRL);
314 reg |= MDIO_MASTER_SEL;
315 reg_writel(priv, reg, REG_SWITCH_CNTRL);
316
317 /* Page << 8 | offset */
318 reg = 0x70;
319 reg <<= 2;
320 core_writel(priv, addr, reg);
321
322 /* Page << 8 | offset */
323 reg = 0x80 << 8 | regnum << 1;
324 reg <<= 2;
325
326 if (op)
327 ret = core_readl(priv, reg);
328 else
329 core_writel(priv, val, reg);
330
331 reg = reg_readl(priv, REG_SWITCH_CNTRL);
332 reg &= ~MDIO_MASTER_SEL;
333 reg_writel(priv, reg, REG_SWITCH_CNTRL);
334
335 return ret & 0xffff;
336 }
337
bcm_sf2_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)338 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
339 {
340 struct bcm_sf2_priv *priv = bus->priv;
341
342 /* Intercept reads from Broadcom pseudo-PHY address, else, send
343 * them to our master MDIO bus controller
344 */
345 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
346 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
347 else
348 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
349 }
350
bcm_sf2_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)351 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
352 u16 val)
353 {
354 struct bcm_sf2_priv *priv = bus->priv;
355
356 /* Intercept writes to the Broadcom pseudo-PHY address, else,
357 * send them to our master MDIO bus controller
358 */
359 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
360 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
361 else
362 return mdiobus_write_nested(priv->master_mii_bus, addr,
363 regnum, val);
364 }
365
bcm_sf2_switch_0_isr(int irq,void * dev_id)366 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
367 {
368 struct dsa_switch *ds = dev_id;
369 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
370
371 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
372 ~priv->irq0_mask;
373 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
374
375 return IRQ_HANDLED;
376 }
377
bcm_sf2_switch_1_isr(int irq,void * dev_id)378 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
379 {
380 struct dsa_switch *ds = dev_id;
381 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
382
383 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
384 ~priv->irq1_mask;
385 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
386
387 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
388 priv->port_sts[7].link = true;
389 dsa_port_phylink_mac_change(ds, 7, true);
390 }
391 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
392 priv->port_sts[7].link = false;
393 dsa_port_phylink_mac_change(ds, 7, false);
394 }
395
396 return IRQ_HANDLED;
397 }
398
bcm_sf2_sw_rst(struct bcm_sf2_priv * priv)399 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
400 {
401 unsigned int timeout = 1000;
402 u32 reg;
403 int ret;
404
405 /* The watchdog reset does not work on 7278, we need to hit the
406 * "external" reset line through the reset controller.
407 */
408 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) {
409 ret = reset_control_assert(priv->rcdev);
410 if (ret)
411 return ret;
412
413 return reset_control_deassert(priv->rcdev);
414 }
415
416 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
417 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
418 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
419
420 do {
421 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
422 if (!(reg & SOFTWARE_RESET))
423 break;
424
425 usleep_range(1000, 2000);
426 } while (timeout-- > 0);
427
428 if (timeout == 0)
429 return -ETIMEDOUT;
430
431 return 0;
432 }
433
bcm_sf2_intr_disable(struct bcm_sf2_priv * priv)434 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
435 {
436 intrl2_0_mask_set(priv, 0xffffffff);
437 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
438 intrl2_1_mask_set(priv, 0xffffffff);
439 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
440 }
441
bcm_sf2_identify_ports(struct bcm_sf2_priv * priv,struct device_node * dn)442 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
443 struct device_node *dn)
444 {
445 struct device_node *port;
446 unsigned int port_num;
447 struct property *prop;
448 phy_interface_t mode;
449 int err;
450
451 priv->moca_port = -1;
452
453 for_each_available_child_of_node(dn, port) {
454 if (of_property_read_u32(port, "reg", &port_num))
455 continue;
456
457 /* Internal PHYs get assigned a specific 'phy-mode' property
458 * value: "internal" to help flag them before MDIO probing
459 * has completed, since they might be turned off at that
460 * time
461 */
462 err = of_get_phy_mode(port, &mode);
463 if (err)
464 continue;
465
466 if (mode == PHY_INTERFACE_MODE_INTERNAL)
467 priv->int_phy_mask |= 1 << port_num;
468
469 if (mode == PHY_INTERFACE_MODE_MOCA)
470 priv->moca_port = port_num;
471
472 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
473 priv->brcm_tag_mask |= 1 << port_num;
474
475 /* Ensure that port 5 is not picked up as a DSA CPU port
476 * flavour but a regular port instead. We should be using
477 * devlink to be able to set the port flavour.
478 */
479 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) {
480 prop = of_find_property(port, "ethernet", NULL);
481 if (prop)
482 of_remove_property(port, prop);
483 }
484 }
485 }
486
bcm_sf2_mdio_register(struct dsa_switch * ds)487 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
488 {
489 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
490 struct device_node *dn, *child;
491 struct phy_device *phydev;
492 struct property *prop;
493 static int index;
494 int err, reg;
495
496 /* Find our integrated MDIO bus node */
497 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
498 priv->master_mii_bus = of_mdio_find_bus(dn);
499 if (!priv->master_mii_bus) {
500 of_node_put(dn);
501 return -EPROBE_DEFER;
502 }
503
504 get_device(&priv->master_mii_bus->dev);
505 priv->master_mii_dn = dn;
506
507 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
508 if (!priv->slave_mii_bus) {
509 of_node_put(dn);
510 return -ENOMEM;
511 }
512
513 priv->slave_mii_bus->priv = priv;
514 priv->slave_mii_bus->name = "sf2 slave mii";
515 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
516 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
517 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
518 index++);
519 priv->slave_mii_bus->dev.of_node = dn;
520
521 /* Include the pseudo-PHY address to divert reads towards our
522 * workaround. This is only required for 7445D0, since 7445E0
523 * disconnects the internal switch pseudo-PHY such that we can use the
524 * regular SWITCH_MDIO master controller instead.
525 *
526 * Here we flag the pseudo PHY as needing special treatment and would
527 * otherwise make all other PHY read/writes go to the master MDIO bus
528 * controller that comes with this switch backed by the "mdio-unimac"
529 * driver.
530 */
531 if (of_machine_is_compatible("brcm,bcm7445d0"))
532 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0);
533 else
534 priv->indir_phy_mask = 0;
535
536 ds->phys_mii_mask = priv->indir_phy_mask;
537 ds->slave_mii_bus = priv->slave_mii_bus;
538 priv->slave_mii_bus->parent = ds->dev->parent;
539 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
540
541 /* We need to make sure that of_phy_connect() will not work by
542 * removing the 'phandle' and 'linux,phandle' properties and
543 * unregister the existing PHY device that was already registered.
544 */
545 for_each_available_child_of_node(dn, child) {
546 if (of_property_read_u32(child, "reg", ®) ||
547 reg >= PHY_MAX_ADDR)
548 continue;
549
550 if (!(priv->indir_phy_mask & BIT(reg)))
551 continue;
552
553 prop = of_find_property(child, "phandle", NULL);
554 if (prop)
555 of_remove_property(child, prop);
556
557 prop = of_find_property(child, "linux,phandle", NULL);
558 if (prop)
559 of_remove_property(child, prop);
560
561 phydev = of_phy_find_device(child);
562 if (phydev)
563 phy_device_remove(phydev);
564 }
565
566 err = mdiobus_register(priv->slave_mii_bus);
567 if (err && dn)
568 of_node_put(dn);
569
570 return err;
571 }
572
bcm_sf2_mdio_unregister(struct bcm_sf2_priv * priv)573 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
574 {
575 mdiobus_unregister(priv->slave_mii_bus);
576 of_node_put(priv->master_mii_dn);
577 }
578
bcm_sf2_sw_get_phy_flags(struct dsa_switch * ds,int port)579 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
580 {
581 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
582
583 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
584 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
585 * the REG_PHY_REVISION register layout is.
586 */
587 if (priv->int_phy_mask & BIT(port))
588 return priv->hw_params.gphy_rev;
589 else
590 return 0;
591 }
592
bcm_sf2_sw_validate(struct dsa_switch * ds,int port,unsigned long * supported,struct phylink_link_state * state)593 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
594 unsigned long *supported,
595 struct phylink_link_state *state)
596 {
597 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
598 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
599
600 if (!phy_interface_mode_is_rgmii(state->interface) &&
601 state->interface != PHY_INTERFACE_MODE_MII &&
602 state->interface != PHY_INTERFACE_MODE_REVMII &&
603 state->interface != PHY_INTERFACE_MODE_GMII &&
604 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
605 state->interface != PHY_INTERFACE_MODE_MOCA) {
606 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
607 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
608 dev_err(ds->dev,
609 "Unsupported interface: %d for port %d\n",
610 state->interface, port);
611 return;
612 }
613
614 /* Allow all the expected bits */
615 phylink_set(mask, Autoneg);
616 phylink_set_port_modes(mask);
617 phylink_set(mask, Pause);
618 phylink_set(mask, Asym_Pause);
619
620 /* With the exclusion of MII and Reverse MII, we support Gigabit,
621 * including Half duplex
622 */
623 if (state->interface != PHY_INTERFACE_MODE_MII &&
624 state->interface != PHY_INTERFACE_MODE_REVMII) {
625 phylink_set(mask, 1000baseT_Full);
626 phylink_set(mask, 1000baseT_Half);
627 }
628
629 phylink_set(mask, 10baseT_Half);
630 phylink_set(mask, 10baseT_Full);
631 phylink_set(mask, 100baseT_Half);
632 phylink_set(mask, 100baseT_Full);
633
634 bitmap_and(supported, supported, mask,
635 __ETHTOOL_LINK_MODE_MASK_NBITS);
636 bitmap_and(state->advertising, state->advertising, mask,
637 __ETHTOOL_LINK_MODE_MASK_NBITS);
638 }
639
bcm_sf2_sw_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)640 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
641 unsigned int mode,
642 const struct phylink_link_state *state)
643 {
644 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
645 u32 id_mode_dis = 0, port_mode;
646 u32 reg;
647
648 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
649 return;
650
651 switch (state->interface) {
652 case PHY_INTERFACE_MODE_RGMII:
653 id_mode_dis = 1;
654 fallthrough;
655 case PHY_INTERFACE_MODE_RGMII_TXID:
656 port_mode = EXT_GPHY;
657 break;
658 case PHY_INTERFACE_MODE_MII:
659 port_mode = EXT_EPHY;
660 break;
661 case PHY_INTERFACE_MODE_REVMII:
662 port_mode = EXT_REVMII;
663 break;
664 default:
665 /* Nothing required for all other PHYs: internal and MoCA */
666 return;
667 }
668
669 /* Clear id_mode_dis bit, and the existing port mode, let
670 * RGMII_MODE_EN bet set by mac_link_{up,down}
671 */
672 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
673 reg &= ~ID_MODE_DIS;
674 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
675
676 reg |= port_mode;
677 if (id_mode_dis)
678 reg |= ID_MODE_DIS;
679
680 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
681 }
682
bcm_sf2_sw_mac_link_set(struct dsa_switch * ds,int port,phy_interface_t interface,bool link)683 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
684 phy_interface_t interface, bool link)
685 {
686 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
687 u32 reg;
688
689 if (!phy_interface_mode_is_rgmii(interface) &&
690 interface != PHY_INTERFACE_MODE_MII &&
691 interface != PHY_INTERFACE_MODE_REVMII)
692 return;
693
694 /* If the link is down, just disable the interface to conserve power */
695 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
696 if (link)
697 reg |= RGMII_MODE_EN;
698 else
699 reg &= ~RGMII_MODE_EN;
700 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
701 }
702
bcm_sf2_sw_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)703 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
704 unsigned int mode,
705 phy_interface_t interface)
706 {
707 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
708 u32 reg, offset;
709
710 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
711 if (priv->type == BCM7445_DEVICE_ID)
712 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
713 else
714 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
715
716 reg = core_readl(priv, offset);
717 reg &= ~LINK_STS;
718 core_writel(priv, reg, offset);
719 }
720
721 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
722 }
723
bcm_sf2_sw_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)724 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
725 unsigned int mode,
726 phy_interface_t interface,
727 struct phy_device *phydev,
728 int speed, int duplex,
729 bool tx_pause, bool rx_pause)
730 {
731 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
732 struct ethtool_eee *p = &priv->dev->ports[port].eee;
733 u32 reg, offset;
734
735 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
736
737 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
738 if (priv->type == BCM7445_DEVICE_ID)
739 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
740 else
741 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
742
743 if (interface == PHY_INTERFACE_MODE_RGMII ||
744 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
745 interface == PHY_INTERFACE_MODE_MII ||
746 interface == PHY_INTERFACE_MODE_REVMII) {
747 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
748 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
749
750 if (tx_pause)
751 reg |= TX_PAUSE_EN;
752 if (rx_pause)
753 reg |= RX_PAUSE_EN;
754
755 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
756 }
757
758 reg = SW_OVERRIDE | LINK_STS;
759 switch (speed) {
760 case SPEED_1000:
761 reg |= SPDSTS_1000 << SPEED_SHIFT;
762 break;
763 case SPEED_100:
764 reg |= SPDSTS_100 << SPEED_SHIFT;
765 break;
766 }
767
768 if (duplex == DUPLEX_FULL)
769 reg |= DUPLX_MODE;
770
771 core_writel(priv, reg, offset);
772 }
773
774 if (mode == MLO_AN_PHY && phydev)
775 p->eee_enabled = b53_eee_init(ds, port, phydev);
776 }
777
bcm_sf2_sw_fixed_state(struct dsa_switch * ds,int port,struct phylink_link_state * status)778 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
779 struct phylink_link_state *status)
780 {
781 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
782
783 status->link = false;
784
785 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
786 * which means that we need to force the link at the port override
787 * level to get the data to flow. We do use what the interrupt handler
788 * did determine before.
789 *
790 * For the other ports, we just force the link status, since this is
791 * a fixed PHY device.
792 */
793 if (port == priv->moca_port) {
794 status->link = priv->port_sts[port].link;
795 /* For MoCA interfaces, also force a link down notification
796 * since some version of the user-space daemon (mocad) use
797 * cmd->autoneg to force the link, which messes up the PHY
798 * state machine and make it go in PHY_FORCING state instead.
799 */
800 if (!status->link)
801 netif_carrier_off(dsa_to_port(ds, port)->slave);
802 status->duplex = DUPLEX_FULL;
803 } else {
804 status->link = true;
805 }
806 }
807
bcm_sf2_enable_acb(struct dsa_switch * ds)808 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
809 {
810 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
811 u32 reg;
812
813 /* Enable ACB globally */
814 reg = acb_readl(priv, ACB_CONTROL);
815 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
816 acb_writel(priv, reg, ACB_CONTROL);
817 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
818 reg |= ACB_EN | ACB_ALGORITHM;
819 acb_writel(priv, reg, ACB_CONTROL);
820 }
821
bcm_sf2_sw_suspend(struct dsa_switch * ds)822 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
823 {
824 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
825 unsigned int port;
826
827 bcm_sf2_intr_disable(priv);
828
829 /* Disable all ports physically present including the IMP
830 * port, the other ones have already been disabled during
831 * bcm_sf2_sw_setup
832 */
833 for (port = 0; port < ds->num_ports; port++) {
834 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
835 bcm_sf2_port_disable(ds, port);
836 }
837
838 if (!priv->wol_ports_mask)
839 clk_disable_unprepare(priv->clk);
840
841 return 0;
842 }
843
bcm_sf2_sw_resume(struct dsa_switch * ds)844 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
845 {
846 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
847 int ret;
848
849 if (!priv->wol_ports_mask)
850 clk_prepare_enable(priv->clk);
851
852 ret = bcm_sf2_sw_rst(priv);
853 if (ret) {
854 pr_err("%s: failed to software reset switch\n", __func__);
855 return ret;
856 }
857
858 ret = bcm_sf2_cfp_resume(ds);
859 if (ret)
860 return ret;
861
862 if (priv->hw_params.num_gphy == 1)
863 bcm_sf2_gphy_enable_set(ds, true);
864
865 ds->ops->setup(ds);
866
867 return 0;
868 }
869
bcm_sf2_sw_get_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)870 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
871 struct ethtool_wolinfo *wol)
872 {
873 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
874 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
875 struct ethtool_wolinfo pwol = { };
876
877 /* Get the parent device WoL settings */
878 if (p->ethtool_ops->get_wol)
879 p->ethtool_ops->get_wol(p, &pwol);
880
881 /* Advertise the parent device supported settings */
882 wol->supported = pwol.supported;
883 memset(&wol->sopass, 0, sizeof(wol->sopass));
884
885 if (pwol.wolopts & WAKE_MAGICSECURE)
886 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
887
888 if (priv->wol_ports_mask & (1 << port))
889 wol->wolopts = pwol.wolopts;
890 else
891 wol->wolopts = 0;
892 }
893
bcm_sf2_sw_set_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)894 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
895 struct ethtool_wolinfo *wol)
896 {
897 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
898 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
899 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
900 struct ethtool_wolinfo pwol = { };
901
902 if (p->ethtool_ops->get_wol)
903 p->ethtool_ops->get_wol(p, &pwol);
904 if (wol->wolopts & ~pwol.supported)
905 return -EINVAL;
906
907 if (wol->wolopts)
908 priv->wol_ports_mask |= (1 << port);
909 else
910 priv->wol_ports_mask &= ~(1 << port);
911
912 /* If we have at least one port enabled, make sure the CPU port
913 * is also enabled. If the CPU port is the last one enabled, we disable
914 * it since this configuration does not make sense.
915 */
916 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
917 priv->wol_ports_mask |= (1 << cpu_port);
918 else
919 priv->wol_ports_mask &= ~(1 << cpu_port);
920
921 return p->ethtool_ops->set_wol(p, wol);
922 }
923
bcm_sf2_sw_setup(struct dsa_switch * ds)924 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
925 {
926 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
927 unsigned int port;
928
929 /* Enable all valid ports and disable those unused */
930 for (port = 0; port < priv->hw_params.num_ports; port++) {
931 /* IMP port receives special treatment */
932 if (dsa_is_user_port(ds, port))
933 bcm_sf2_port_setup(ds, port, NULL);
934 else if (dsa_is_cpu_port(ds, port))
935 bcm_sf2_imp_setup(ds, port);
936 else
937 bcm_sf2_port_disable(ds, port);
938 }
939
940 b53_configure_vlan(ds);
941 bcm_sf2_enable_acb(ds);
942
943 return b53_setup_devlink_resources(ds);
944 }
945
bcm_sf2_sw_teardown(struct dsa_switch * ds)946 static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
947 {
948 dsa_devlink_resources_unregister(ds);
949 }
950
951 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
952 * register basis so we need to translate that into an address that the
953 * bus-glue understands.
954 */
955 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
956
bcm_sf2_core_read8(struct b53_device * dev,u8 page,u8 reg,u8 * val)957 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
958 u8 *val)
959 {
960 struct bcm_sf2_priv *priv = dev->priv;
961
962 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
963
964 return 0;
965 }
966
bcm_sf2_core_read16(struct b53_device * dev,u8 page,u8 reg,u16 * val)967 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
968 u16 *val)
969 {
970 struct bcm_sf2_priv *priv = dev->priv;
971
972 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
973
974 return 0;
975 }
976
bcm_sf2_core_read32(struct b53_device * dev,u8 page,u8 reg,u32 * val)977 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
978 u32 *val)
979 {
980 struct bcm_sf2_priv *priv = dev->priv;
981
982 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
983
984 return 0;
985 }
986
bcm_sf2_core_read64(struct b53_device * dev,u8 page,u8 reg,u64 * val)987 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
988 u64 *val)
989 {
990 struct bcm_sf2_priv *priv = dev->priv;
991
992 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
993
994 return 0;
995 }
996
bcm_sf2_core_write8(struct b53_device * dev,u8 page,u8 reg,u8 value)997 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
998 u8 value)
999 {
1000 struct bcm_sf2_priv *priv = dev->priv;
1001
1002 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1003
1004 return 0;
1005 }
1006
bcm_sf2_core_write16(struct b53_device * dev,u8 page,u8 reg,u16 value)1007 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
1008 u16 value)
1009 {
1010 struct bcm_sf2_priv *priv = dev->priv;
1011
1012 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1013
1014 return 0;
1015 }
1016
bcm_sf2_core_write32(struct b53_device * dev,u8 page,u8 reg,u32 value)1017 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1018 u32 value)
1019 {
1020 struct bcm_sf2_priv *priv = dev->priv;
1021
1022 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1023
1024 return 0;
1025 }
1026
bcm_sf2_core_write64(struct b53_device * dev,u8 page,u8 reg,u64 value)1027 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1028 u64 value)
1029 {
1030 struct bcm_sf2_priv *priv = dev->priv;
1031
1032 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1033
1034 return 0;
1035 }
1036
1037 static const struct b53_io_ops bcm_sf2_io_ops = {
1038 .read8 = bcm_sf2_core_read8,
1039 .read16 = bcm_sf2_core_read16,
1040 .read32 = bcm_sf2_core_read32,
1041 .read48 = bcm_sf2_core_read64,
1042 .read64 = bcm_sf2_core_read64,
1043 .write8 = bcm_sf2_core_write8,
1044 .write16 = bcm_sf2_core_write16,
1045 .write32 = bcm_sf2_core_write32,
1046 .write48 = bcm_sf2_core_write64,
1047 .write64 = bcm_sf2_core_write64,
1048 };
1049
bcm_sf2_sw_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1050 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
1051 u32 stringset, uint8_t *data)
1052 {
1053 int cnt = b53_get_sset_count(ds, port, stringset);
1054
1055 b53_get_strings(ds, port, stringset, data);
1056 bcm_sf2_cfp_get_strings(ds, port, stringset,
1057 data + cnt * ETH_GSTRING_LEN);
1058 }
1059
bcm_sf2_sw_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1060 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
1061 uint64_t *data)
1062 {
1063 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
1064
1065 b53_get_ethtool_stats(ds, port, data);
1066 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
1067 }
1068
bcm_sf2_sw_get_sset_count(struct dsa_switch * ds,int port,int sset)1069 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
1070 int sset)
1071 {
1072 int cnt = b53_get_sset_count(ds, port, sset);
1073
1074 if (cnt < 0)
1075 return cnt;
1076
1077 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
1078
1079 return cnt;
1080 }
1081
1082 static const struct dsa_switch_ops bcm_sf2_ops = {
1083 .get_tag_protocol = b53_get_tag_protocol,
1084 .setup = bcm_sf2_sw_setup,
1085 .teardown = bcm_sf2_sw_teardown,
1086 .get_strings = bcm_sf2_sw_get_strings,
1087 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1088 .get_sset_count = bcm_sf2_sw_get_sset_count,
1089 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
1090 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1091 .phylink_validate = bcm_sf2_sw_validate,
1092 .phylink_mac_config = bcm_sf2_sw_mac_config,
1093 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
1094 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
1095 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
1096 .suspend = bcm_sf2_sw_suspend,
1097 .resume = bcm_sf2_sw_resume,
1098 .get_wol = bcm_sf2_sw_get_wol,
1099 .set_wol = bcm_sf2_sw_set_wol,
1100 .port_enable = bcm_sf2_port_setup,
1101 .port_disable = bcm_sf2_port_disable,
1102 .get_mac_eee = b53_get_mac_eee,
1103 .set_mac_eee = b53_set_mac_eee,
1104 .port_bridge_join = b53_br_join,
1105 .port_bridge_leave = b53_br_leave,
1106 .port_stp_state_set = b53_br_set_stp_state,
1107 .port_fast_age = b53_br_fast_age,
1108 .port_vlan_filtering = b53_vlan_filtering,
1109 .port_vlan_prepare = b53_vlan_prepare,
1110 .port_vlan_add = b53_vlan_add,
1111 .port_vlan_del = b53_vlan_del,
1112 .port_fdb_dump = b53_fdb_dump,
1113 .port_fdb_add = b53_fdb_add,
1114 .port_fdb_del = b53_fdb_del,
1115 .get_rxnfc = bcm_sf2_get_rxnfc,
1116 .set_rxnfc = bcm_sf2_set_rxnfc,
1117 .port_mirror_add = b53_mirror_add,
1118 .port_mirror_del = b53_mirror_del,
1119 .port_mdb_prepare = b53_mdb_prepare,
1120 .port_mdb_add = b53_mdb_add,
1121 .port_mdb_del = b53_mdb_del,
1122 };
1123
1124 struct bcm_sf2_of_data {
1125 u32 type;
1126 const u16 *reg_offsets;
1127 unsigned int core_reg_align;
1128 unsigned int num_cfp_rules;
1129 };
1130
1131 /* Register offsets for the SWITCH_REG_* block */
1132 static const u16 bcm_sf2_7445_reg_offsets[] = {
1133 [REG_SWITCH_CNTRL] = 0x00,
1134 [REG_SWITCH_STATUS] = 0x04,
1135 [REG_DIR_DATA_WRITE] = 0x08,
1136 [REG_DIR_DATA_READ] = 0x0C,
1137 [REG_SWITCH_REVISION] = 0x18,
1138 [REG_PHY_REVISION] = 0x1C,
1139 [REG_SPHY_CNTRL] = 0x2C,
1140 [REG_RGMII_0_CNTRL] = 0x34,
1141 [REG_RGMII_1_CNTRL] = 0x40,
1142 [REG_RGMII_2_CNTRL] = 0x4c,
1143 [REG_LED_0_CNTRL] = 0x90,
1144 [REG_LED_1_CNTRL] = 0x94,
1145 [REG_LED_2_CNTRL] = 0x98,
1146 };
1147
1148 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1149 .type = BCM7445_DEVICE_ID,
1150 .core_reg_align = 0,
1151 .reg_offsets = bcm_sf2_7445_reg_offsets,
1152 .num_cfp_rules = 256,
1153 };
1154
1155 static const u16 bcm_sf2_7278_reg_offsets[] = {
1156 [REG_SWITCH_CNTRL] = 0x00,
1157 [REG_SWITCH_STATUS] = 0x04,
1158 [REG_DIR_DATA_WRITE] = 0x08,
1159 [REG_DIR_DATA_READ] = 0x0c,
1160 [REG_SWITCH_REVISION] = 0x10,
1161 [REG_PHY_REVISION] = 0x14,
1162 [REG_SPHY_CNTRL] = 0x24,
1163 [REG_RGMII_0_CNTRL] = 0xe0,
1164 [REG_RGMII_1_CNTRL] = 0xec,
1165 [REG_RGMII_2_CNTRL] = 0xf8,
1166 [REG_LED_0_CNTRL] = 0x40,
1167 [REG_LED_1_CNTRL] = 0x4c,
1168 [REG_LED_2_CNTRL] = 0x58,
1169 };
1170
1171 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1172 .type = BCM7278_DEVICE_ID,
1173 .core_reg_align = 1,
1174 .reg_offsets = bcm_sf2_7278_reg_offsets,
1175 .num_cfp_rules = 128,
1176 };
1177
1178 static const struct of_device_id bcm_sf2_of_match[] = {
1179 { .compatible = "brcm,bcm7445-switch-v4.0",
1180 .data = &bcm_sf2_7445_data
1181 },
1182 { .compatible = "brcm,bcm7278-switch-v4.0",
1183 .data = &bcm_sf2_7278_data
1184 },
1185 { .compatible = "brcm,bcm7278-switch-v4.8",
1186 .data = &bcm_sf2_7278_data
1187 },
1188 { /* sentinel */ },
1189 };
1190 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1191
bcm_sf2_sw_probe(struct platform_device * pdev)1192 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1193 {
1194 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1195 struct device_node *dn = pdev->dev.of_node;
1196 const struct of_device_id *of_id = NULL;
1197 const struct bcm_sf2_of_data *data;
1198 struct b53_platform_data *pdata;
1199 struct dsa_switch_ops *ops;
1200 struct device_node *ports;
1201 struct bcm_sf2_priv *priv;
1202 struct b53_device *dev;
1203 struct dsa_switch *ds;
1204 void __iomem **base;
1205 unsigned int i;
1206 u32 reg, rev;
1207 int ret;
1208
1209 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1210 if (!priv)
1211 return -ENOMEM;
1212
1213 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1214 if (!ops)
1215 return -ENOMEM;
1216
1217 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1218 if (!dev)
1219 return -ENOMEM;
1220
1221 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1222 if (!pdata)
1223 return -ENOMEM;
1224
1225 of_id = of_match_node(bcm_sf2_of_match, dn);
1226 if (!of_id || !of_id->data)
1227 return -EINVAL;
1228
1229 data = of_id->data;
1230
1231 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1232 priv->type = data->type;
1233 priv->reg_offsets = data->reg_offsets;
1234 priv->core_reg_align = data->core_reg_align;
1235 priv->num_cfp_rules = data->num_cfp_rules;
1236
1237 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
1238 "switch");
1239 if (PTR_ERR(priv->rcdev) == -EPROBE_DEFER)
1240 return PTR_ERR(priv->rcdev);
1241
1242 /* Auto-detection using standard registers will not work, so
1243 * provide an indication of what kind of device we are for
1244 * b53_common to work with
1245 */
1246 pdata->chip_id = priv->type;
1247 dev->pdata = pdata;
1248
1249 priv->dev = dev;
1250 ds = dev->ds;
1251 ds->ops = &bcm_sf2_ops;
1252
1253 /* Advertise the 8 egress queues */
1254 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1255
1256 dev_set_drvdata(&pdev->dev, priv);
1257
1258 spin_lock_init(&priv->indir_lock);
1259 mutex_init(&priv->cfp.lock);
1260 INIT_LIST_HEAD(&priv->cfp.rules_list);
1261
1262 /* CFP rule #0 cannot be used for specific classifications, flag it as
1263 * permanently used
1264 */
1265 set_bit(0, priv->cfp.used);
1266 set_bit(0, priv->cfp.unique);
1267
1268 /* Balance of_node_put() done by of_find_node_by_name() */
1269 of_node_get(dn);
1270 ports = of_find_node_by_name(dn, "ports");
1271 if (ports) {
1272 bcm_sf2_identify_ports(priv, ports);
1273 of_node_put(ports);
1274 }
1275
1276 priv->irq0 = irq_of_parse_and_map(dn, 0);
1277 priv->irq1 = irq_of_parse_and_map(dn, 1);
1278
1279 base = &priv->core;
1280 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1281 *base = devm_platform_ioremap_resource(pdev, i);
1282 if (IS_ERR(*base)) {
1283 pr_err("unable to find register: %s\n", reg_names[i]);
1284 return PTR_ERR(*base);
1285 }
1286 base++;
1287 }
1288
1289 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch");
1290 if (IS_ERR(priv->clk))
1291 return PTR_ERR(priv->clk);
1292
1293 clk_prepare_enable(priv->clk);
1294
1295 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv");
1296 if (IS_ERR(priv->clk_mdiv)) {
1297 ret = PTR_ERR(priv->clk_mdiv);
1298 goto out_clk;
1299 }
1300
1301 clk_prepare_enable(priv->clk_mdiv);
1302
1303 ret = bcm_sf2_sw_rst(priv);
1304 if (ret) {
1305 pr_err("unable to software reset switch: %d\n", ret);
1306 goto out_clk_mdiv;
1307 }
1308
1309 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1310
1311 ret = bcm_sf2_mdio_register(ds);
1312 if (ret) {
1313 pr_err("failed to register MDIO bus\n");
1314 goto out_clk_mdiv;
1315 }
1316
1317 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1318
1319 ret = bcm_sf2_cfp_rst(priv);
1320 if (ret) {
1321 pr_err("failed to reset CFP\n");
1322 goto out_mdio;
1323 }
1324
1325 /* Disable all interrupts and request them */
1326 bcm_sf2_intr_disable(priv);
1327
1328 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1329 "switch_0", ds);
1330 if (ret < 0) {
1331 pr_err("failed to request switch_0 IRQ\n");
1332 goto out_mdio;
1333 }
1334
1335 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1336 "switch_1", ds);
1337 if (ret < 0) {
1338 pr_err("failed to request switch_1 IRQ\n");
1339 goto out_mdio;
1340 }
1341
1342 /* Reset the MIB counters */
1343 reg = core_readl(priv, CORE_GMNCFGCFG);
1344 reg |= RST_MIB_CNT;
1345 core_writel(priv, reg, CORE_GMNCFGCFG);
1346 reg &= ~RST_MIB_CNT;
1347 core_writel(priv, reg, CORE_GMNCFGCFG);
1348
1349 /* Get the maximum number of ports for this switch */
1350 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1351 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1352 priv->hw_params.num_ports = DSA_MAX_PORTS;
1353
1354 /* Assume a single GPHY setup if we can't read that property */
1355 if (of_property_read_u32(dn, "brcm,num-gphy",
1356 &priv->hw_params.num_gphy))
1357 priv->hw_params.num_gphy = 1;
1358
1359 rev = reg_readl(priv, REG_SWITCH_REVISION);
1360 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1361 SWITCH_TOP_REV_MASK;
1362 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1363
1364 rev = reg_readl(priv, REG_PHY_REVISION);
1365 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1366
1367 ret = b53_switch_register(dev);
1368 if (ret)
1369 goto out_mdio;
1370
1371 dev_info(&pdev->dev,
1372 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1373 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1374 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1375 priv->irq0, priv->irq1);
1376
1377 return 0;
1378
1379 out_mdio:
1380 bcm_sf2_mdio_unregister(priv);
1381 out_clk_mdiv:
1382 clk_disable_unprepare(priv->clk_mdiv);
1383 out_clk:
1384 clk_disable_unprepare(priv->clk);
1385 return ret;
1386 }
1387
bcm_sf2_sw_remove(struct platform_device * pdev)1388 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1389 {
1390 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1391
1392 priv->wol_ports_mask = 0;
1393 /* Disable interrupts */
1394 bcm_sf2_intr_disable(priv);
1395 dsa_unregister_switch(priv->dev->ds);
1396 bcm_sf2_cfp_exit(priv->dev->ds);
1397 bcm_sf2_mdio_unregister(priv);
1398 clk_disable_unprepare(priv->clk_mdiv);
1399 clk_disable_unprepare(priv->clk);
1400 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev))
1401 reset_control_assert(priv->rcdev);
1402
1403 return 0;
1404 }
1405
bcm_sf2_sw_shutdown(struct platform_device * pdev)1406 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1407 {
1408 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1409
1410 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1411 * successful MDIO bus scan to occur. If we did turn off the GPHY
1412 * before (e.g: port_disable), this will also power it back on.
1413 *
1414 * Do not rely on kexec_in_progress, just power the PHY on.
1415 */
1416 if (priv->hw_params.num_gphy == 1)
1417 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1418 }
1419
1420 #ifdef CONFIG_PM_SLEEP
bcm_sf2_suspend(struct device * dev)1421 static int bcm_sf2_suspend(struct device *dev)
1422 {
1423 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1424
1425 return dsa_switch_suspend(priv->dev->ds);
1426 }
1427
bcm_sf2_resume(struct device * dev)1428 static int bcm_sf2_resume(struct device *dev)
1429 {
1430 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1431
1432 return dsa_switch_resume(priv->dev->ds);
1433 }
1434 #endif /* CONFIG_PM_SLEEP */
1435
1436 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1437 bcm_sf2_suspend, bcm_sf2_resume);
1438
1439
1440 static struct platform_driver bcm_sf2_driver = {
1441 .probe = bcm_sf2_sw_probe,
1442 .remove = bcm_sf2_sw_remove,
1443 .shutdown = bcm_sf2_sw_shutdown,
1444 .driver = {
1445 .name = "brcm-sf2",
1446 .of_match_table = bcm_sf2_of_match,
1447 .pm = &bcm_sf2_pm_ops,
1448 },
1449 };
1450 module_platform_driver(bcm_sf2_driver);
1451
1452 MODULE_AUTHOR("Broadcom Corporation");
1453 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1454 MODULE_LICENSE("GPL");
1455 MODULE_ALIAS("platform:brcm-sf2");
1456