1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Cadence MACB/GEM Ethernet Controller driver
4 *
5 * Copyright (C) 2004-2006 Atmel Corporation
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/phylink.h>
28 #include <linux/of.h>
29 #include <linux/of_device.h>
30 #include <linux/of_gpio.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
33 #include <linux/ip.h>
34 #include <linux/udp.h>
35 #include <linux/tcp.h>
36 #include <linux/iopoll.h>
37 #include <linux/pm_runtime.h>
38 #include "macb.h"
39
40 /* This structure is only used for MACB on SiFive FU540 devices */
41 struct sifive_fu540_macb_mgmt {
42 void __iomem *reg;
43 unsigned long rate;
44 struct clk_hw hw;
45 };
46
47 #define MACB_RX_BUFFER_SIZE 128
48 #define RX_BUFFER_MULTIPLE 64 /* bytes */
49
50 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
51 #define MIN_RX_RING_SIZE 64
52 #define MAX_RX_RING_SIZE 8192
53 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
54 * (bp)->rx_ring_size)
55
56 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
57 #define MIN_TX_RING_SIZE 64
58 #define MAX_TX_RING_SIZE 4096
59 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
60 * (bp)->tx_ring_size)
61
62 /* level of occupied TX descriptors under which we wake up TX process */
63 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
64
65 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
66 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
67 | MACB_BIT(ISR_RLE) \
68 | MACB_BIT(TXERR))
69 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
70 | MACB_BIT(TXUBR))
71
72 /* Max length of transmit frame must be a multiple of 8 bytes */
73 #define MACB_TX_LEN_ALIGN 8
74 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
75 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
76 * false amba_error in TX path from the DMA assuming there is not enough
77 * space in the SRAM (16KB) even when there is.
78 */
79 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
80
81 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
82 #define MACB_NETIF_LSO NETIF_F_TSO
83
84 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
85 #define MACB_WOL_ENABLED (0x1 << 1)
86
87 /* Graceful stop timeouts in us. We should allow up to
88 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
89 */
90 #define MACB_HALT_TIMEOUT 1230
91
92 #define MACB_PM_TIMEOUT 100 /* ms */
93
94 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
95
96 /* DMA buffer descriptor might be different size
97 * depends on hardware configuration:
98 *
99 * 1. dma address width 32 bits:
100 * word 1: 32 bit address of Data Buffer
101 * word 2: control
102 *
103 * 2. dma address width 64 bits:
104 * word 1: 32 bit address of Data Buffer
105 * word 2: control
106 * word 3: upper 32 bit address of Data Buffer
107 * word 4: unused
108 *
109 * 3. dma address width 32 bits with hardware timestamping:
110 * word 1: 32 bit address of Data Buffer
111 * word 2: control
112 * word 3: timestamp word 1
113 * word 4: timestamp word 2
114 *
115 * 4. dma address width 64 bits with hardware timestamping:
116 * word 1: 32 bit address of Data Buffer
117 * word 2: control
118 * word 3: upper 32 bit address of Data Buffer
119 * word 4: unused
120 * word 5: timestamp word 1
121 * word 6: timestamp word 2
122 */
macb_dma_desc_get_size(struct macb * bp)123 static unsigned int macb_dma_desc_get_size(struct macb *bp)
124 {
125 #ifdef MACB_EXT_DESC
126 unsigned int desc_size;
127
128 switch (bp->hw_dma_cap) {
129 case HW_DMA_CAP_64B:
130 desc_size = sizeof(struct macb_dma_desc)
131 + sizeof(struct macb_dma_desc_64);
132 break;
133 case HW_DMA_CAP_PTP:
134 desc_size = sizeof(struct macb_dma_desc)
135 + sizeof(struct macb_dma_desc_ptp);
136 break;
137 case HW_DMA_CAP_64B_PTP:
138 desc_size = sizeof(struct macb_dma_desc)
139 + sizeof(struct macb_dma_desc_64)
140 + sizeof(struct macb_dma_desc_ptp);
141 break;
142 default:
143 desc_size = sizeof(struct macb_dma_desc);
144 }
145 return desc_size;
146 #endif
147 return sizeof(struct macb_dma_desc);
148 }
149
macb_adj_dma_desc_idx(struct macb * bp,unsigned int desc_idx)150 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
151 {
152 #ifdef MACB_EXT_DESC
153 switch (bp->hw_dma_cap) {
154 case HW_DMA_CAP_64B:
155 case HW_DMA_CAP_PTP:
156 desc_idx <<= 1;
157 break;
158 case HW_DMA_CAP_64B_PTP:
159 desc_idx *= 3;
160 break;
161 default:
162 break;
163 }
164 #endif
165 return desc_idx;
166 }
167
168 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
macb_64b_desc(struct macb * bp,struct macb_dma_desc * desc)169 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
170 {
171 return (struct macb_dma_desc_64 *)((void *)desc
172 + sizeof(struct macb_dma_desc));
173 }
174 #endif
175
176 /* Ring buffer accessors */
macb_tx_ring_wrap(struct macb * bp,unsigned int index)177 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
178 {
179 return index & (bp->tx_ring_size - 1);
180 }
181
macb_tx_desc(struct macb_queue * queue,unsigned int index)182 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
183 unsigned int index)
184 {
185 index = macb_tx_ring_wrap(queue->bp, index);
186 index = macb_adj_dma_desc_idx(queue->bp, index);
187 return &queue->tx_ring[index];
188 }
189
macb_tx_skb(struct macb_queue * queue,unsigned int index)190 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
191 unsigned int index)
192 {
193 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
194 }
195
macb_tx_dma(struct macb_queue * queue,unsigned int index)196 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
197 {
198 dma_addr_t offset;
199
200 offset = macb_tx_ring_wrap(queue->bp, index) *
201 macb_dma_desc_get_size(queue->bp);
202
203 return queue->tx_ring_dma + offset;
204 }
205
macb_rx_ring_wrap(struct macb * bp,unsigned int index)206 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
207 {
208 return index & (bp->rx_ring_size - 1);
209 }
210
macb_rx_desc(struct macb_queue * queue,unsigned int index)211 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
212 {
213 index = macb_rx_ring_wrap(queue->bp, index);
214 index = macb_adj_dma_desc_idx(queue->bp, index);
215 return &queue->rx_ring[index];
216 }
217
macb_rx_buffer(struct macb_queue * queue,unsigned int index)218 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
219 {
220 return queue->rx_buffers + queue->bp->rx_buffer_size *
221 macb_rx_ring_wrap(queue->bp, index);
222 }
223
224 /* I/O accessors */
hw_readl_native(struct macb * bp,int offset)225 static u32 hw_readl_native(struct macb *bp, int offset)
226 {
227 return __raw_readl(bp->regs + offset);
228 }
229
hw_writel_native(struct macb * bp,int offset,u32 value)230 static void hw_writel_native(struct macb *bp, int offset, u32 value)
231 {
232 __raw_writel(value, bp->regs + offset);
233 }
234
hw_readl(struct macb * bp,int offset)235 static u32 hw_readl(struct macb *bp, int offset)
236 {
237 return readl_relaxed(bp->regs + offset);
238 }
239
hw_writel(struct macb * bp,int offset,u32 value)240 static void hw_writel(struct macb *bp, int offset, u32 value)
241 {
242 writel_relaxed(value, bp->regs + offset);
243 }
244
245 /* Find the CPU endianness by using the loopback bit of NCR register. When the
246 * CPU is in big endian we need to program swapped mode for management
247 * descriptor access.
248 */
hw_is_native_io(void __iomem * addr)249 static bool hw_is_native_io(void __iomem *addr)
250 {
251 u32 value = MACB_BIT(LLB);
252
253 __raw_writel(value, addr + MACB_NCR);
254 value = __raw_readl(addr + MACB_NCR);
255
256 /* Write 0 back to disable everything */
257 __raw_writel(0, addr + MACB_NCR);
258
259 return value == MACB_BIT(LLB);
260 }
261
hw_is_gem(void __iomem * addr,bool native_io)262 static bool hw_is_gem(void __iomem *addr, bool native_io)
263 {
264 u32 id;
265
266 if (native_io)
267 id = __raw_readl(addr + MACB_MID);
268 else
269 id = readl_relaxed(addr + MACB_MID);
270
271 return MACB_BFEXT(IDNUM, id) >= 0x2;
272 }
273
macb_set_hwaddr(struct macb * bp)274 static void macb_set_hwaddr(struct macb *bp)
275 {
276 u32 bottom;
277 u16 top;
278
279 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
280 macb_or_gem_writel(bp, SA1B, bottom);
281 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
282 macb_or_gem_writel(bp, SA1T, top);
283
284 /* Clear unused address register sets */
285 macb_or_gem_writel(bp, SA2B, 0);
286 macb_or_gem_writel(bp, SA2T, 0);
287 macb_or_gem_writel(bp, SA3B, 0);
288 macb_or_gem_writel(bp, SA3T, 0);
289 macb_or_gem_writel(bp, SA4B, 0);
290 macb_or_gem_writel(bp, SA4T, 0);
291 }
292
macb_get_hwaddr(struct macb * bp)293 static void macb_get_hwaddr(struct macb *bp)
294 {
295 u32 bottom;
296 u16 top;
297 u8 addr[6];
298 int i;
299
300 /* Check all 4 address register for valid address */
301 for (i = 0; i < 4; i++) {
302 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
303 top = macb_or_gem_readl(bp, SA1T + i * 8);
304
305 addr[0] = bottom & 0xff;
306 addr[1] = (bottom >> 8) & 0xff;
307 addr[2] = (bottom >> 16) & 0xff;
308 addr[3] = (bottom >> 24) & 0xff;
309 addr[4] = top & 0xff;
310 addr[5] = (top >> 8) & 0xff;
311
312 if (is_valid_ether_addr(addr)) {
313 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
314 return;
315 }
316 }
317
318 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
319 eth_hw_addr_random(bp->dev);
320 }
321
macb_mdio_wait_for_idle(struct macb * bp)322 static int macb_mdio_wait_for_idle(struct macb *bp)
323 {
324 u32 val;
325
326 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
327 1, MACB_MDIO_TIMEOUT);
328 }
329
macb_mdio_read(struct mii_bus * bus,int mii_id,int regnum)330 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
331 {
332 struct macb *bp = bus->priv;
333 int status;
334
335 status = pm_runtime_get_sync(&bp->pdev->dev);
336 if (status < 0) {
337 pm_runtime_put_noidle(&bp->pdev->dev);
338 goto mdio_pm_exit;
339 }
340
341 status = macb_mdio_wait_for_idle(bp);
342 if (status < 0)
343 goto mdio_read_exit;
344
345 if (regnum & MII_ADDR_C45) {
346 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
347 | MACB_BF(RW, MACB_MAN_C45_ADDR)
348 | MACB_BF(PHYA, mii_id)
349 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
350 | MACB_BF(DATA, regnum & 0xFFFF)
351 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
352
353 status = macb_mdio_wait_for_idle(bp);
354 if (status < 0)
355 goto mdio_read_exit;
356
357 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
358 | MACB_BF(RW, MACB_MAN_C45_READ)
359 | MACB_BF(PHYA, mii_id)
360 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
361 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
362 } else {
363 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
364 | MACB_BF(RW, MACB_MAN_C22_READ)
365 | MACB_BF(PHYA, mii_id)
366 | MACB_BF(REGA, regnum)
367 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
368 }
369
370 status = macb_mdio_wait_for_idle(bp);
371 if (status < 0)
372 goto mdio_read_exit;
373
374 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
375
376 mdio_read_exit:
377 pm_runtime_mark_last_busy(&bp->pdev->dev);
378 pm_runtime_put_autosuspend(&bp->pdev->dev);
379 mdio_pm_exit:
380 return status;
381 }
382
macb_mdio_write(struct mii_bus * bus,int mii_id,int regnum,u16 value)383 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
384 u16 value)
385 {
386 struct macb *bp = bus->priv;
387 int status;
388
389 status = pm_runtime_get_sync(&bp->pdev->dev);
390 if (status < 0) {
391 pm_runtime_put_noidle(&bp->pdev->dev);
392 goto mdio_pm_exit;
393 }
394
395 status = macb_mdio_wait_for_idle(bp);
396 if (status < 0)
397 goto mdio_write_exit;
398
399 if (regnum & MII_ADDR_C45) {
400 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
401 | MACB_BF(RW, MACB_MAN_C45_ADDR)
402 | MACB_BF(PHYA, mii_id)
403 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
404 | MACB_BF(DATA, regnum & 0xFFFF)
405 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
406
407 status = macb_mdio_wait_for_idle(bp);
408 if (status < 0)
409 goto mdio_write_exit;
410
411 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
412 | MACB_BF(RW, MACB_MAN_C45_WRITE)
413 | MACB_BF(PHYA, mii_id)
414 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
415 | MACB_BF(CODE, MACB_MAN_C45_CODE)
416 | MACB_BF(DATA, value)));
417 } else {
418 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
419 | MACB_BF(RW, MACB_MAN_C22_WRITE)
420 | MACB_BF(PHYA, mii_id)
421 | MACB_BF(REGA, regnum)
422 | MACB_BF(CODE, MACB_MAN_C22_CODE)
423 | MACB_BF(DATA, value)));
424 }
425
426 status = macb_mdio_wait_for_idle(bp);
427 if (status < 0)
428 goto mdio_write_exit;
429
430 mdio_write_exit:
431 pm_runtime_mark_last_busy(&bp->pdev->dev);
432 pm_runtime_put_autosuspend(&bp->pdev->dev);
433 mdio_pm_exit:
434 return status;
435 }
436
macb_init_buffers(struct macb * bp)437 static void macb_init_buffers(struct macb *bp)
438 {
439 struct macb_queue *queue;
440 unsigned int q;
441
442 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
443 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
444 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
445 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
446 queue_writel(queue, RBQPH,
447 upper_32_bits(queue->rx_ring_dma));
448 #endif
449 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
450 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
451 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
452 queue_writel(queue, TBQPH,
453 upper_32_bits(queue->tx_ring_dma));
454 #endif
455 }
456 }
457
458 /**
459 * macb_set_tx_clk() - Set a clock to a new frequency
460 * @clk: Pointer to the clock to change
461 * @speed: New frequency in Hz
462 * @dev: Pointer to the struct net_device
463 */
macb_set_tx_clk(struct clk * clk,int speed,struct net_device * dev)464 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
465 {
466 long ferr, rate, rate_rounded;
467
468 if (!clk)
469 return;
470
471 switch (speed) {
472 case SPEED_10:
473 rate = 2500000;
474 break;
475 case SPEED_100:
476 rate = 25000000;
477 break;
478 case SPEED_1000:
479 rate = 125000000;
480 break;
481 default:
482 return;
483 }
484
485 rate_rounded = clk_round_rate(clk, rate);
486 if (rate_rounded < 0)
487 return;
488
489 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
490 * is not satisfied.
491 */
492 ferr = abs(rate_rounded - rate);
493 ferr = DIV_ROUND_UP(ferr, rate / 100000);
494 if (ferr > 5)
495 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
496 rate);
497
498 if (clk_set_rate(clk, rate_rounded))
499 netdev_err(dev, "adjusting tx_clk failed.\n");
500 }
501
macb_validate(struct phylink_config * config,unsigned long * supported,struct phylink_link_state * state)502 static void macb_validate(struct phylink_config *config,
503 unsigned long *supported,
504 struct phylink_link_state *state)
505 {
506 struct net_device *ndev = to_net_dev(config->dev);
507 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
508 struct macb *bp = netdev_priv(ndev);
509
510 /* We only support MII, RMII, GMII, RGMII & SGMII. */
511 if (state->interface != PHY_INTERFACE_MODE_NA &&
512 state->interface != PHY_INTERFACE_MODE_MII &&
513 state->interface != PHY_INTERFACE_MODE_RMII &&
514 state->interface != PHY_INTERFACE_MODE_GMII &&
515 state->interface != PHY_INTERFACE_MODE_SGMII &&
516 !phy_interface_mode_is_rgmii(state->interface)) {
517 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
518 return;
519 }
520
521 if (!macb_is_gem(bp) &&
522 (state->interface == PHY_INTERFACE_MODE_GMII ||
523 phy_interface_mode_is_rgmii(state->interface))) {
524 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
525 return;
526 }
527
528 phylink_set_port_modes(mask);
529 phylink_set(mask, Autoneg);
530 phylink_set(mask, Asym_Pause);
531
532 phylink_set(mask, 10baseT_Half);
533 phylink_set(mask, 10baseT_Full);
534 phylink_set(mask, 100baseT_Half);
535 phylink_set(mask, 100baseT_Full);
536
537 if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
538 (state->interface == PHY_INTERFACE_MODE_NA ||
539 state->interface == PHY_INTERFACE_MODE_GMII ||
540 state->interface == PHY_INTERFACE_MODE_SGMII ||
541 phy_interface_mode_is_rgmii(state->interface))) {
542 phylink_set(mask, 1000baseT_Full);
543 phylink_set(mask, 1000baseX_Full);
544
545 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
546 phylink_set(mask, 1000baseT_Half);
547 }
548
549 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
550 bitmap_and(state->advertising, state->advertising, mask,
551 __ETHTOOL_LINK_MODE_MASK_NBITS);
552 }
553
macb_mac_pcs_get_state(struct phylink_config * config,struct phylink_link_state * state)554 static void macb_mac_pcs_get_state(struct phylink_config *config,
555 struct phylink_link_state *state)
556 {
557 state->link = 0;
558 }
559
macb_mac_an_restart(struct phylink_config * config)560 static void macb_mac_an_restart(struct phylink_config *config)
561 {
562 /* Not supported */
563 }
564
macb_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)565 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
566 const struct phylink_link_state *state)
567 {
568 struct net_device *ndev = to_net_dev(config->dev);
569 struct macb *bp = netdev_priv(ndev);
570 unsigned long flags;
571 u32 old_ctrl, ctrl;
572
573 spin_lock_irqsave(&bp->lock, flags);
574
575 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
576
577 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
578 if (state->interface == PHY_INTERFACE_MODE_RMII)
579 ctrl |= MACB_BIT(RM9200_RMII);
580 } else if (macb_is_gem(bp)) {
581 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
582
583 if (state->interface == PHY_INTERFACE_MODE_SGMII)
584 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
585 }
586
587 /* Apply the new configuration, if any */
588 if (old_ctrl ^ ctrl)
589 macb_or_gem_writel(bp, NCFGR, ctrl);
590
591 spin_unlock_irqrestore(&bp->lock, flags);
592 }
593
macb_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)594 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
595 phy_interface_t interface)
596 {
597 struct net_device *ndev = to_net_dev(config->dev);
598 struct macb *bp = netdev_priv(ndev);
599 struct macb_queue *queue;
600 unsigned int q;
601 u32 ctrl;
602
603 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
604 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
605 queue_writel(queue, IDR,
606 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
607
608 /* Disable Rx and Tx */
609 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
610 macb_writel(bp, NCR, ctrl);
611
612 netif_tx_stop_all_queues(ndev);
613 }
614
macb_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)615 static void macb_mac_link_up(struct phylink_config *config,
616 struct phy_device *phy,
617 unsigned int mode, phy_interface_t interface,
618 int speed, int duplex,
619 bool tx_pause, bool rx_pause)
620 {
621 struct net_device *ndev = to_net_dev(config->dev);
622 struct macb *bp = netdev_priv(ndev);
623 struct macb_queue *queue;
624 unsigned long flags;
625 unsigned int q;
626 u32 ctrl;
627
628 spin_lock_irqsave(&bp->lock, flags);
629
630 ctrl = macb_or_gem_readl(bp, NCFGR);
631
632 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
633
634 if (speed == SPEED_100)
635 ctrl |= MACB_BIT(SPD);
636
637 if (duplex)
638 ctrl |= MACB_BIT(FD);
639
640 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
641 ctrl &= ~MACB_BIT(PAE);
642 if (macb_is_gem(bp)) {
643 ctrl &= ~GEM_BIT(GBE);
644
645 if (speed == SPEED_1000)
646 ctrl |= GEM_BIT(GBE);
647 }
648
649 if (rx_pause)
650 ctrl |= MACB_BIT(PAE);
651
652 macb_set_tx_clk(bp->tx_clk, speed, ndev);
653
654 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
655 * cleared the pipeline and control registers.
656 */
657 bp->macbgem_ops.mog_init_rings(bp);
658 macb_init_buffers(bp);
659
660 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
661 queue_writel(queue, IER,
662 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
663 }
664
665 macb_or_gem_writel(bp, NCFGR, ctrl);
666
667 spin_unlock_irqrestore(&bp->lock, flags);
668
669 /* Enable Rx and Tx */
670 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
671
672 netif_tx_wake_all_queues(ndev);
673 }
674
675 static const struct phylink_mac_ops macb_phylink_ops = {
676 .validate = macb_validate,
677 .mac_pcs_get_state = macb_mac_pcs_get_state,
678 .mac_an_restart = macb_mac_an_restart,
679 .mac_config = macb_mac_config,
680 .mac_link_down = macb_mac_link_down,
681 .mac_link_up = macb_mac_link_up,
682 };
683
macb_phy_handle_exists(struct device_node * dn)684 static bool macb_phy_handle_exists(struct device_node *dn)
685 {
686 dn = of_parse_phandle(dn, "phy-handle", 0);
687 of_node_put(dn);
688 return dn != NULL;
689 }
690
macb_phylink_connect(struct macb * bp)691 static int macb_phylink_connect(struct macb *bp)
692 {
693 struct device_node *dn = bp->pdev->dev.of_node;
694 struct net_device *dev = bp->dev;
695 struct phy_device *phydev;
696 int ret;
697
698 if (dn)
699 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
700
701 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
702 phydev = phy_find_first(bp->mii_bus);
703 if (!phydev) {
704 netdev_err(dev, "no PHY found\n");
705 return -ENXIO;
706 }
707
708 /* attach the mac to the phy */
709 ret = phylink_connect_phy(bp->phylink, phydev);
710 }
711
712 if (ret) {
713 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
714 return ret;
715 }
716
717 phylink_start(bp->phylink);
718
719 return 0;
720 }
721
722 /* based on au1000_eth. c*/
macb_mii_probe(struct net_device * dev)723 static int macb_mii_probe(struct net_device *dev)
724 {
725 struct macb *bp = netdev_priv(dev);
726
727 bp->phylink_config.dev = &dev->dev;
728 bp->phylink_config.type = PHYLINK_NETDEV;
729
730 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
731 bp->phy_interface, &macb_phylink_ops);
732 if (IS_ERR(bp->phylink)) {
733 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
734 PTR_ERR(bp->phylink));
735 return PTR_ERR(bp->phylink);
736 }
737
738 return 0;
739 }
740
macb_mdiobus_register(struct macb * bp)741 static int macb_mdiobus_register(struct macb *bp)
742 {
743 struct device_node *child, *np = bp->pdev->dev.of_node;
744
745 if (of_phy_is_fixed_link(np))
746 return mdiobus_register(bp->mii_bus);
747
748 /* Only create the PHY from the device tree if at least one PHY is
749 * described. Otherwise scan the entire MDIO bus. We do this to support
750 * old device tree that did not follow the best practices and did not
751 * describe their network PHYs.
752 */
753 for_each_available_child_of_node(np, child)
754 if (of_mdiobus_child_is_phy(child)) {
755 /* The loop increments the child refcount,
756 * decrement it before returning.
757 */
758 of_node_put(child);
759
760 return of_mdiobus_register(bp->mii_bus, np);
761 }
762
763 return mdiobus_register(bp->mii_bus);
764 }
765
macb_mii_init(struct macb * bp)766 static int macb_mii_init(struct macb *bp)
767 {
768 int err = -ENXIO;
769
770 /* Enable management port */
771 macb_writel(bp, NCR, MACB_BIT(MPE));
772
773 bp->mii_bus = mdiobus_alloc();
774 if (!bp->mii_bus) {
775 err = -ENOMEM;
776 goto err_out;
777 }
778
779 bp->mii_bus->name = "MACB_mii_bus";
780 bp->mii_bus->read = &macb_mdio_read;
781 bp->mii_bus->write = &macb_mdio_write;
782 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
783 bp->pdev->name, bp->pdev->id);
784 bp->mii_bus->priv = bp;
785 bp->mii_bus->parent = &bp->pdev->dev;
786
787 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
788
789 err = macb_mdiobus_register(bp);
790 if (err)
791 goto err_out_free_mdiobus;
792
793 err = macb_mii_probe(bp->dev);
794 if (err)
795 goto err_out_unregister_bus;
796
797 return 0;
798
799 err_out_unregister_bus:
800 mdiobus_unregister(bp->mii_bus);
801 err_out_free_mdiobus:
802 mdiobus_free(bp->mii_bus);
803 err_out:
804 return err;
805 }
806
macb_update_stats(struct macb * bp)807 static void macb_update_stats(struct macb *bp)
808 {
809 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
810 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
811 int offset = MACB_PFR;
812
813 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
814
815 for (; p < end; p++, offset += 4)
816 *p += bp->macb_reg_readl(bp, offset);
817 }
818
macb_halt_tx(struct macb * bp)819 static int macb_halt_tx(struct macb *bp)
820 {
821 unsigned long halt_time, timeout;
822 u32 status;
823
824 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
825
826 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
827 do {
828 halt_time = jiffies;
829 status = macb_readl(bp, TSR);
830 if (!(status & MACB_BIT(TGO)))
831 return 0;
832
833 udelay(250);
834 } while (time_before(halt_time, timeout));
835
836 return -ETIMEDOUT;
837 }
838
macb_tx_unmap(struct macb * bp,struct macb_tx_skb * tx_skb)839 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
840 {
841 if (tx_skb->mapping) {
842 if (tx_skb->mapped_as_page)
843 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
844 tx_skb->size, DMA_TO_DEVICE);
845 else
846 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
847 tx_skb->size, DMA_TO_DEVICE);
848 tx_skb->mapping = 0;
849 }
850
851 if (tx_skb->skb) {
852 dev_kfree_skb_any(tx_skb->skb);
853 tx_skb->skb = NULL;
854 }
855 }
856
macb_set_addr(struct macb * bp,struct macb_dma_desc * desc,dma_addr_t addr)857 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
858 {
859 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
860 struct macb_dma_desc_64 *desc_64;
861
862 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
863 desc_64 = macb_64b_desc(bp, desc);
864 desc_64->addrh = upper_32_bits(addr);
865 /* The low bits of RX address contain the RX_USED bit, clearing
866 * of which allows packet RX. Make sure the high bits are also
867 * visible to HW at that point.
868 */
869 dma_wmb();
870 }
871 #endif
872 desc->addr = lower_32_bits(addr);
873 }
874
macb_get_addr(struct macb * bp,struct macb_dma_desc * desc)875 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
876 {
877 dma_addr_t addr = 0;
878 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
879 struct macb_dma_desc_64 *desc_64;
880
881 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
882 desc_64 = macb_64b_desc(bp, desc);
883 addr = ((u64)(desc_64->addrh) << 32);
884 }
885 #endif
886 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
887 return addr;
888 }
889
macb_tx_error_task(struct work_struct * work)890 static void macb_tx_error_task(struct work_struct *work)
891 {
892 struct macb_queue *queue = container_of(work, struct macb_queue,
893 tx_error_task);
894 struct macb *bp = queue->bp;
895 struct macb_tx_skb *tx_skb;
896 struct macb_dma_desc *desc;
897 struct sk_buff *skb;
898 unsigned int tail;
899 unsigned long flags;
900
901 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
902 (unsigned int)(queue - bp->queues),
903 queue->tx_tail, queue->tx_head);
904
905 /* Prevent the queue IRQ handlers from running: each of them may call
906 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
907 * As explained below, we have to halt the transmission before updating
908 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
909 * network engine about the macb/gem being halted.
910 */
911 spin_lock_irqsave(&bp->lock, flags);
912
913 /* Make sure nobody is trying to queue up new packets */
914 netif_tx_stop_all_queues(bp->dev);
915
916 /* Stop transmission now
917 * (in case we have just queued new packets)
918 * macb/gem must be halted to write TBQP register
919 */
920 if (macb_halt_tx(bp))
921 /* Just complain for now, reinitializing TX path can be good */
922 netdev_err(bp->dev, "BUG: halt tx timed out\n");
923
924 /* Treat frames in TX queue including the ones that caused the error.
925 * Free transmit buffers in upper layer.
926 */
927 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
928 u32 ctrl;
929
930 desc = macb_tx_desc(queue, tail);
931 ctrl = desc->ctrl;
932 tx_skb = macb_tx_skb(queue, tail);
933 skb = tx_skb->skb;
934
935 if (ctrl & MACB_BIT(TX_USED)) {
936 /* skb is set for the last buffer of the frame */
937 while (!skb) {
938 macb_tx_unmap(bp, tx_skb);
939 tail++;
940 tx_skb = macb_tx_skb(queue, tail);
941 skb = tx_skb->skb;
942 }
943
944 /* ctrl still refers to the first buffer descriptor
945 * since it's the only one written back by the hardware
946 */
947 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
948 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
949 macb_tx_ring_wrap(bp, tail),
950 skb->data);
951 bp->dev->stats.tx_packets++;
952 queue->stats.tx_packets++;
953 bp->dev->stats.tx_bytes += skb->len;
954 queue->stats.tx_bytes += skb->len;
955 }
956 } else {
957 /* "Buffers exhausted mid-frame" errors may only happen
958 * if the driver is buggy, so complain loudly about
959 * those. Statistics are updated by hardware.
960 */
961 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
962 netdev_err(bp->dev,
963 "BUG: TX buffers exhausted mid-frame\n");
964
965 desc->ctrl = ctrl | MACB_BIT(TX_USED);
966 }
967
968 macb_tx_unmap(bp, tx_skb);
969 }
970
971 /* Set end of TX queue */
972 desc = macb_tx_desc(queue, 0);
973 macb_set_addr(bp, desc, 0);
974 desc->ctrl = MACB_BIT(TX_USED);
975
976 /* Make descriptor updates visible to hardware */
977 wmb();
978
979 /* Reinitialize the TX desc queue */
980 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
981 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
982 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
983 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
984 #endif
985 /* Make TX ring reflect state of hardware */
986 queue->tx_head = 0;
987 queue->tx_tail = 0;
988
989 /* Housework before enabling TX IRQ */
990 macb_writel(bp, TSR, macb_readl(bp, TSR));
991 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
992
993 /* Now we are ready to start transmission again */
994 netif_tx_start_all_queues(bp->dev);
995 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
996
997 spin_unlock_irqrestore(&bp->lock, flags);
998 }
999
macb_tx_interrupt(struct macb_queue * queue)1000 static void macb_tx_interrupt(struct macb_queue *queue)
1001 {
1002 unsigned int tail;
1003 unsigned int head;
1004 u32 status;
1005 struct macb *bp = queue->bp;
1006 u16 queue_index = queue - bp->queues;
1007
1008 status = macb_readl(bp, TSR);
1009 macb_writel(bp, TSR, status);
1010
1011 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1012 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1013
1014 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
1015 (unsigned long)status);
1016
1017 head = queue->tx_head;
1018 for (tail = queue->tx_tail; tail != head; tail++) {
1019 struct macb_tx_skb *tx_skb;
1020 struct sk_buff *skb;
1021 struct macb_dma_desc *desc;
1022 u32 ctrl;
1023
1024 desc = macb_tx_desc(queue, tail);
1025
1026 /* Make hw descriptor updates visible to CPU */
1027 rmb();
1028
1029 ctrl = desc->ctrl;
1030
1031 /* TX_USED bit is only set by hardware on the very first buffer
1032 * descriptor of the transmitted frame.
1033 */
1034 if (!(ctrl & MACB_BIT(TX_USED)))
1035 break;
1036
1037 /* Process all buffers of the current transmitted frame */
1038 for (;; tail++) {
1039 tx_skb = macb_tx_skb(queue, tail);
1040 skb = tx_skb->skb;
1041
1042 /* First, update TX stats if needed */
1043 if (skb) {
1044 if (unlikely(skb_shinfo(skb)->tx_flags &
1045 SKBTX_HW_TSTAMP) &&
1046 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1047 /* skb now belongs to timestamp buffer
1048 * and will be removed later
1049 */
1050 tx_skb->skb = NULL;
1051 }
1052 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1053 macb_tx_ring_wrap(bp, tail),
1054 skb->data);
1055 bp->dev->stats.tx_packets++;
1056 queue->stats.tx_packets++;
1057 bp->dev->stats.tx_bytes += skb->len;
1058 queue->stats.tx_bytes += skb->len;
1059 }
1060
1061 /* Now we can safely release resources */
1062 macb_tx_unmap(bp, tx_skb);
1063
1064 /* skb is set only for the last buffer of the frame.
1065 * WARNING: at this point skb has been freed by
1066 * macb_tx_unmap().
1067 */
1068 if (skb)
1069 break;
1070 }
1071 }
1072
1073 queue->tx_tail = tail;
1074 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1075 CIRC_CNT(queue->tx_head, queue->tx_tail,
1076 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1077 netif_wake_subqueue(bp->dev, queue_index);
1078 }
1079
gem_rx_refill(struct macb_queue * queue)1080 static void gem_rx_refill(struct macb_queue *queue)
1081 {
1082 unsigned int entry;
1083 struct sk_buff *skb;
1084 dma_addr_t paddr;
1085 struct macb *bp = queue->bp;
1086 struct macb_dma_desc *desc;
1087
1088 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1089 bp->rx_ring_size) > 0) {
1090 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1091
1092 /* Make hw descriptor updates visible to CPU */
1093 rmb();
1094
1095 queue->rx_prepared_head++;
1096 desc = macb_rx_desc(queue, entry);
1097
1098 if (!queue->rx_skbuff[entry]) {
1099 /* allocate sk_buff for this free entry in ring */
1100 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1101 if (unlikely(!skb)) {
1102 netdev_err(bp->dev,
1103 "Unable to allocate sk_buff\n");
1104 break;
1105 }
1106
1107 /* now fill corresponding descriptor entry */
1108 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1109 bp->rx_buffer_size,
1110 DMA_FROM_DEVICE);
1111 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1112 dev_kfree_skb(skb);
1113 break;
1114 }
1115
1116 queue->rx_skbuff[entry] = skb;
1117
1118 if (entry == bp->rx_ring_size - 1)
1119 paddr |= MACB_BIT(RX_WRAP);
1120 desc->ctrl = 0;
1121 /* Setting addr clears RX_USED and allows reception,
1122 * make sure ctrl is cleared first to avoid a race.
1123 */
1124 dma_wmb();
1125 macb_set_addr(bp, desc, paddr);
1126
1127 /* properly align Ethernet header */
1128 skb_reserve(skb, NET_IP_ALIGN);
1129 } else {
1130 desc->ctrl = 0;
1131 dma_wmb();
1132 desc->addr &= ~MACB_BIT(RX_USED);
1133 }
1134 }
1135
1136 /* Make descriptor updates visible to hardware */
1137 wmb();
1138
1139 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1140 queue, queue->rx_prepared_head, queue->rx_tail);
1141 }
1142
1143 /* Mark DMA descriptors from begin up to and not including end as unused */
discard_partial_frame(struct macb_queue * queue,unsigned int begin,unsigned int end)1144 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1145 unsigned int end)
1146 {
1147 unsigned int frag;
1148
1149 for (frag = begin; frag != end; frag++) {
1150 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1151
1152 desc->addr &= ~MACB_BIT(RX_USED);
1153 }
1154
1155 /* Make descriptor updates visible to hardware */
1156 wmb();
1157
1158 /* When this happens, the hardware stats registers for
1159 * whatever caused this is updated, so we don't have to record
1160 * anything.
1161 */
1162 }
1163
gem_rx(struct macb_queue * queue,struct napi_struct * napi,int budget)1164 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1165 int budget)
1166 {
1167 struct macb *bp = queue->bp;
1168 unsigned int len;
1169 unsigned int entry;
1170 struct sk_buff *skb;
1171 struct macb_dma_desc *desc;
1172 int count = 0;
1173
1174 while (count < budget) {
1175 u32 ctrl;
1176 dma_addr_t addr;
1177 bool rxused;
1178
1179 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1180 desc = macb_rx_desc(queue, entry);
1181
1182 /* Make hw descriptor updates visible to CPU */
1183 rmb();
1184
1185 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1186 addr = macb_get_addr(bp, desc);
1187
1188 if (!rxused)
1189 break;
1190
1191 /* Ensure ctrl is at least as up-to-date as rxused */
1192 dma_rmb();
1193
1194 ctrl = desc->ctrl;
1195
1196 queue->rx_tail++;
1197 count++;
1198
1199 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1200 netdev_err(bp->dev,
1201 "not whole frame pointed by descriptor\n");
1202 bp->dev->stats.rx_dropped++;
1203 queue->stats.rx_dropped++;
1204 break;
1205 }
1206 skb = queue->rx_skbuff[entry];
1207 if (unlikely(!skb)) {
1208 netdev_err(bp->dev,
1209 "inconsistent Rx descriptor chain\n");
1210 bp->dev->stats.rx_dropped++;
1211 queue->stats.rx_dropped++;
1212 break;
1213 }
1214 /* now everything is ready for receiving packet */
1215 queue->rx_skbuff[entry] = NULL;
1216 len = ctrl & bp->rx_frm_len_mask;
1217
1218 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1219
1220 skb_put(skb, len);
1221 dma_unmap_single(&bp->pdev->dev, addr,
1222 bp->rx_buffer_size, DMA_FROM_DEVICE);
1223
1224 skb->protocol = eth_type_trans(skb, bp->dev);
1225 skb_checksum_none_assert(skb);
1226 if (bp->dev->features & NETIF_F_RXCSUM &&
1227 !(bp->dev->flags & IFF_PROMISC) &&
1228 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1229 skb->ip_summed = CHECKSUM_UNNECESSARY;
1230
1231 bp->dev->stats.rx_packets++;
1232 queue->stats.rx_packets++;
1233 bp->dev->stats.rx_bytes += skb->len;
1234 queue->stats.rx_bytes += skb->len;
1235
1236 gem_ptp_do_rxstamp(bp, skb, desc);
1237
1238 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1239 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1240 skb->len, skb->csum);
1241 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1242 skb_mac_header(skb), 16, true);
1243 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1244 skb->data, 32, true);
1245 #endif
1246
1247 napi_gro_receive(napi, skb);
1248 }
1249
1250 gem_rx_refill(queue);
1251
1252 return count;
1253 }
1254
macb_rx_frame(struct macb_queue * queue,struct napi_struct * napi,unsigned int first_frag,unsigned int last_frag)1255 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1256 unsigned int first_frag, unsigned int last_frag)
1257 {
1258 unsigned int len;
1259 unsigned int frag;
1260 unsigned int offset;
1261 struct sk_buff *skb;
1262 struct macb_dma_desc *desc;
1263 struct macb *bp = queue->bp;
1264
1265 desc = macb_rx_desc(queue, last_frag);
1266 len = desc->ctrl & bp->rx_frm_len_mask;
1267
1268 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1269 macb_rx_ring_wrap(bp, first_frag),
1270 macb_rx_ring_wrap(bp, last_frag), len);
1271
1272 /* The ethernet header starts NET_IP_ALIGN bytes into the
1273 * first buffer. Since the header is 14 bytes, this makes the
1274 * payload word-aligned.
1275 *
1276 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1277 * the two padding bytes into the skb so that we avoid hitting
1278 * the slowpath in memcpy(), and pull them off afterwards.
1279 */
1280 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1281 if (!skb) {
1282 bp->dev->stats.rx_dropped++;
1283 for (frag = first_frag; ; frag++) {
1284 desc = macb_rx_desc(queue, frag);
1285 desc->addr &= ~MACB_BIT(RX_USED);
1286 if (frag == last_frag)
1287 break;
1288 }
1289
1290 /* Make descriptor updates visible to hardware */
1291 wmb();
1292
1293 return 1;
1294 }
1295
1296 offset = 0;
1297 len += NET_IP_ALIGN;
1298 skb_checksum_none_assert(skb);
1299 skb_put(skb, len);
1300
1301 for (frag = first_frag; ; frag++) {
1302 unsigned int frag_len = bp->rx_buffer_size;
1303
1304 if (offset + frag_len > len) {
1305 if (unlikely(frag != last_frag)) {
1306 dev_kfree_skb_any(skb);
1307 return -1;
1308 }
1309 frag_len = len - offset;
1310 }
1311 skb_copy_to_linear_data_offset(skb, offset,
1312 macb_rx_buffer(queue, frag),
1313 frag_len);
1314 offset += bp->rx_buffer_size;
1315 desc = macb_rx_desc(queue, frag);
1316 desc->addr &= ~MACB_BIT(RX_USED);
1317
1318 if (frag == last_frag)
1319 break;
1320 }
1321
1322 /* Make descriptor updates visible to hardware */
1323 wmb();
1324
1325 __skb_pull(skb, NET_IP_ALIGN);
1326 skb->protocol = eth_type_trans(skb, bp->dev);
1327
1328 bp->dev->stats.rx_packets++;
1329 bp->dev->stats.rx_bytes += skb->len;
1330 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1331 skb->len, skb->csum);
1332 napi_gro_receive(napi, skb);
1333
1334 return 0;
1335 }
1336
macb_init_rx_ring(struct macb_queue * queue)1337 static inline void macb_init_rx_ring(struct macb_queue *queue)
1338 {
1339 struct macb *bp = queue->bp;
1340 dma_addr_t addr;
1341 struct macb_dma_desc *desc = NULL;
1342 int i;
1343
1344 addr = queue->rx_buffers_dma;
1345 for (i = 0; i < bp->rx_ring_size; i++) {
1346 desc = macb_rx_desc(queue, i);
1347 macb_set_addr(bp, desc, addr);
1348 desc->ctrl = 0;
1349 addr += bp->rx_buffer_size;
1350 }
1351 desc->addr |= MACB_BIT(RX_WRAP);
1352 queue->rx_tail = 0;
1353 }
1354
macb_rx(struct macb_queue * queue,struct napi_struct * napi,int budget)1355 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1356 int budget)
1357 {
1358 struct macb *bp = queue->bp;
1359 bool reset_rx_queue = false;
1360 int received = 0;
1361 unsigned int tail;
1362 int first_frag = -1;
1363
1364 for (tail = queue->rx_tail; budget > 0; tail++) {
1365 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1366 u32 ctrl;
1367
1368 /* Make hw descriptor updates visible to CPU */
1369 rmb();
1370
1371 if (!(desc->addr & MACB_BIT(RX_USED)))
1372 break;
1373
1374 /* Ensure ctrl is at least as up-to-date as addr */
1375 dma_rmb();
1376
1377 ctrl = desc->ctrl;
1378
1379 if (ctrl & MACB_BIT(RX_SOF)) {
1380 if (first_frag != -1)
1381 discard_partial_frame(queue, first_frag, tail);
1382 first_frag = tail;
1383 }
1384
1385 if (ctrl & MACB_BIT(RX_EOF)) {
1386 int dropped;
1387
1388 if (unlikely(first_frag == -1)) {
1389 reset_rx_queue = true;
1390 continue;
1391 }
1392
1393 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1394 first_frag = -1;
1395 if (unlikely(dropped < 0)) {
1396 reset_rx_queue = true;
1397 continue;
1398 }
1399 if (!dropped) {
1400 received++;
1401 budget--;
1402 }
1403 }
1404 }
1405
1406 if (unlikely(reset_rx_queue)) {
1407 unsigned long flags;
1408 u32 ctrl;
1409
1410 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1411
1412 spin_lock_irqsave(&bp->lock, flags);
1413
1414 ctrl = macb_readl(bp, NCR);
1415 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1416
1417 macb_init_rx_ring(queue);
1418 queue_writel(queue, RBQP, queue->rx_ring_dma);
1419
1420 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1421
1422 spin_unlock_irqrestore(&bp->lock, flags);
1423 return received;
1424 }
1425
1426 if (first_frag != -1)
1427 queue->rx_tail = first_frag;
1428 else
1429 queue->rx_tail = tail;
1430
1431 return received;
1432 }
1433
macb_poll(struct napi_struct * napi,int budget)1434 static int macb_poll(struct napi_struct *napi, int budget)
1435 {
1436 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1437 struct macb *bp = queue->bp;
1438 int work_done;
1439 u32 status;
1440
1441 status = macb_readl(bp, RSR);
1442 macb_writel(bp, RSR, status);
1443
1444 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1445 (unsigned long)status, budget);
1446
1447 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1448 if (work_done < budget) {
1449 napi_complete_done(napi, work_done);
1450
1451 /* Packets received while interrupts were disabled */
1452 status = macb_readl(bp, RSR);
1453 if (status) {
1454 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1455 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1456 napi_reschedule(napi);
1457 } else {
1458 queue_writel(queue, IER, bp->rx_intr_mask);
1459 }
1460 }
1461
1462 /* TODO: Handle errors */
1463
1464 return work_done;
1465 }
1466
macb_hresp_error_task(struct tasklet_struct * t)1467 static void macb_hresp_error_task(struct tasklet_struct *t)
1468 {
1469 struct macb *bp = from_tasklet(bp, t, hresp_err_tasklet);
1470 struct net_device *dev = bp->dev;
1471 struct macb_queue *queue;
1472 unsigned int q;
1473 u32 ctrl;
1474
1475 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1476 queue_writel(queue, IDR, bp->rx_intr_mask |
1477 MACB_TX_INT_FLAGS |
1478 MACB_BIT(HRESP));
1479 }
1480 ctrl = macb_readl(bp, NCR);
1481 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1482 macb_writel(bp, NCR, ctrl);
1483
1484 netif_tx_stop_all_queues(dev);
1485 netif_carrier_off(dev);
1486
1487 bp->macbgem_ops.mog_init_rings(bp);
1488
1489 /* Initialize TX and RX buffers */
1490 macb_init_buffers(bp);
1491
1492 /* Enable interrupts */
1493 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1494 queue_writel(queue, IER,
1495 bp->rx_intr_mask |
1496 MACB_TX_INT_FLAGS |
1497 MACB_BIT(HRESP));
1498
1499 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1500 macb_writel(bp, NCR, ctrl);
1501
1502 netif_carrier_on(dev);
1503 netif_tx_start_all_queues(dev);
1504 }
1505
macb_tx_restart(struct macb_queue * queue)1506 static void macb_tx_restart(struct macb_queue *queue)
1507 {
1508 unsigned int head = queue->tx_head;
1509 unsigned int tail = queue->tx_tail;
1510 struct macb *bp = queue->bp;
1511
1512 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1513 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1514
1515 if (head == tail)
1516 return;
1517
1518 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1519 }
1520
macb_wol_interrupt(int irq,void * dev_id)1521 static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1522 {
1523 struct macb_queue *queue = dev_id;
1524 struct macb *bp = queue->bp;
1525 u32 status;
1526
1527 status = queue_readl(queue, ISR);
1528
1529 if (unlikely(!status))
1530 return IRQ_NONE;
1531
1532 spin_lock(&bp->lock);
1533
1534 if (status & MACB_BIT(WOL)) {
1535 queue_writel(queue, IDR, MACB_BIT(WOL));
1536 macb_writel(bp, WOL, 0);
1537 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1538 (unsigned int)(queue - bp->queues),
1539 (unsigned long)status);
1540 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1541 queue_writel(queue, ISR, MACB_BIT(WOL));
1542 pm_wakeup_event(&bp->pdev->dev, 0);
1543 }
1544
1545 spin_unlock(&bp->lock);
1546
1547 return IRQ_HANDLED;
1548 }
1549
gem_wol_interrupt(int irq,void * dev_id)1550 static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1551 {
1552 struct macb_queue *queue = dev_id;
1553 struct macb *bp = queue->bp;
1554 u32 status;
1555
1556 status = queue_readl(queue, ISR);
1557
1558 if (unlikely(!status))
1559 return IRQ_NONE;
1560
1561 spin_lock(&bp->lock);
1562
1563 if (status & GEM_BIT(WOL)) {
1564 queue_writel(queue, IDR, GEM_BIT(WOL));
1565 gem_writel(bp, WOL, 0);
1566 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1567 (unsigned int)(queue - bp->queues),
1568 (unsigned long)status);
1569 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1570 queue_writel(queue, ISR, GEM_BIT(WOL));
1571 pm_wakeup_event(&bp->pdev->dev, 0);
1572 }
1573
1574 spin_unlock(&bp->lock);
1575
1576 return IRQ_HANDLED;
1577 }
1578
macb_interrupt(int irq,void * dev_id)1579 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1580 {
1581 struct macb_queue *queue = dev_id;
1582 struct macb *bp = queue->bp;
1583 struct net_device *dev = bp->dev;
1584 u32 status, ctrl;
1585
1586 status = queue_readl(queue, ISR);
1587
1588 if (unlikely(!status))
1589 return IRQ_NONE;
1590
1591 spin_lock(&bp->lock);
1592
1593 while (status) {
1594 /* close possible race with dev_close */
1595 if (unlikely(!netif_running(dev))) {
1596 queue_writel(queue, IDR, -1);
1597 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1598 queue_writel(queue, ISR, -1);
1599 break;
1600 }
1601
1602 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1603 (unsigned int)(queue - bp->queues),
1604 (unsigned long)status);
1605
1606 if (status & bp->rx_intr_mask) {
1607 /* There's no point taking any more interrupts
1608 * until we have processed the buffers. The
1609 * scheduling call may fail if the poll routine
1610 * is already scheduled, so disable interrupts
1611 * now.
1612 */
1613 queue_writel(queue, IDR, bp->rx_intr_mask);
1614 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1615 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1616
1617 if (napi_schedule_prep(&queue->napi)) {
1618 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1619 __napi_schedule(&queue->napi);
1620 }
1621 }
1622
1623 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1624 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1625 schedule_work(&queue->tx_error_task);
1626
1627 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1628 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1629
1630 break;
1631 }
1632
1633 if (status & MACB_BIT(TCOMP))
1634 macb_tx_interrupt(queue);
1635
1636 if (status & MACB_BIT(TXUBR))
1637 macb_tx_restart(queue);
1638
1639 /* Link change detection isn't possible with RMII, so we'll
1640 * add that if/when we get our hands on a full-blown MII PHY.
1641 */
1642
1643 /* There is a hardware issue under heavy load where DMA can
1644 * stop, this causes endless "used buffer descriptor read"
1645 * interrupts but it can be cleared by re-enabling RX. See
1646 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1647 * section 16.7.4 for details. RXUBR is only enabled for
1648 * these two versions.
1649 */
1650 if (status & MACB_BIT(RXUBR)) {
1651 ctrl = macb_readl(bp, NCR);
1652 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1653 wmb();
1654 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1655
1656 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1657 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1658 }
1659
1660 if (status & MACB_BIT(ISR_ROVR)) {
1661 /* We missed at least one packet */
1662 if (macb_is_gem(bp))
1663 bp->hw_stats.gem.rx_overruns++;
1664 else
1665 bp->hw_stats.macb.rx_overruns++;
1666
1667 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1668 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1669 }
1670
1671 if (status & MACB_BIT(HRESP)) {
1672 tasklet_schedule(&bp->hresp_err_tasklet);
1673 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1674
1675 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1676 queue_writel(queue, ISR, MACB_BIT(HRESP));
1677 }
1678 status = queue_readl(queue, ISR);
1679 }
1680
1681 spin_unlock(&bp->lock);
1682
1683 return IRQ_HANDLED;
1684 }
1685
1686 #ifdef CONFIG_NET_POLL_CONTROLLER
1687 /* Polling receive - used by netconsole and other diagnostic tools
1688 * to allow network i/o with interrupts disabled.
1689 */
macb_poll_controller(struct net_device * dev)1690 static void macb_poll_controller(struct net_device *dev)
1691 {
1692 struct macb *bp = netdev_priv(dev);
1693 struct macb_queue *queue;
1694 unsigned long flags;
1695 unsigned int q;
1696
1697 local_irq_save(flags);
1698 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1699 macb_interrupt(dev->irq, queue);
1700 local_irq_restore(flags);
1701 }
1702 #endif
1703
macb_tx_map(struct macb * bp,struct macb_queue * queue,struct sk_buff * skb,unsigned int hdrlen)1704 static unsigned int macb_tx_map(struct macb *bp,
1705 struct macb_queue *queue,
1706 struct sk_buff *skb,
1707 unsigned int hdrlen)
1708 {
1709 dma_addr_t mapping;
1710 unsigned int len, entry, i, tx_head = queue->tx_head;
1711 struct macb_tx_skb *tx_skb = NULL;
1712 struct macb_dma_desc *desc;
1713 unsigned int offset, size, count = 0;
1714 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1715 unsigned int eof = 1, mss_mfs = 0;
1716 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1717
1718 /* LSO */
1719 if (skb_shinfo(skb)->gso_size != 0) {
1720 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1721 /* UDP - UFO */
1722 lso_ctrl = MACB_LSO_UFO_ENABLE;
1723 else
1724 /* TCP - TSO */
1725 lso_ctrl = MACB_LSO_TSO_ENABLE;
1726 }
1727
1728 /* First, map non-paged data */
1729 len = skb_headlen(skb);
1730
1731 /* first buffer length */
1732 size = hdrlen;
1733
1734 offset = 0;
1735 while (len) {
1736 entry = macb_tx_ring_wrap(bp, tx_head);
1737 tx_skb = &queue->tx_skb[entry];
1738
1739 mapping = dma_map_single(&bp->pdev->dev,
1740 skb->data + offset,
1741 size, DMA_TO_DEVICE);
1742 if (dma_mapping_error(&bp->pdev->dev, mapping))
1743 goto dma_error;
1744
1745 /* Save info to properly release resources */
1746 tx_skb->skb = NULL;
1747 tx_skb->mapping = mapping;
1748 tx_skb->size = size;
1749 tx_skb->mapped_as_page = false;
1750
1751 len -= size;
1752 offset += size;
1753 count++;
1754 tx_head++;
1755
1756 size = min(len, bp->max_tx_length);
1757 }
1758
1759 /* Then, map paged data from fragments */
1760 for (f = 0; f < nr_frags; f++) {
1761 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1762
1763 len = skb_frag_size(frag);
1764 offset = 0;
1765 while (len) {
1766 size = min(len, bp->max_tx_length);
1767 entry = macb_tx_ring_wrap(bp, tx_head);
1768 tx_skb = &queue->tx_skb[entry];
1769
1770 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1771 offset, size, DMA_TO_DEVICE);
1772 if (dma_mapping_error(&bp->pdev->dev, mapping))
1773 goto dma_error;
1774
1775 /* Save info to properly release resources */
1776 tx_skb->skb = NULL;
1777 tx_skb->mapping = mapping;
1778 tx_skb->size = size;
1779 tx_skb->mapped_as_page = true;
1780
1781 len -= size;
1782 offset += size;
1783 count++;
1784 tx_head++;
1785 }
1786 }
1787
1788 /* Should never happen */
1789 if (unlikely(!tx_skb)) {
1790 netdev_err(bp->dev, "BUG! empty skb!\n");
1791 return 0;
1792 }
1793
1794 /* This is the last buffer of the frame: save socket buffer */
1795 tx_skb->skb = skb;
1796
1797 /* Update TX ring: update buffer descriptors in reverse order
1798 * to avoid race condition
1799 */
1800
1801 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1802 * to set the end of TX queue
1803 */
1804 i = tx_head;
1805 entry = macb_tx_ring_wrap(bp, i);
1806 ctrl = MACB_BIT(TX_USED);
1807 desc = macb_tx_desc(queue, entry);
1808 desc->ctrl = ctrl;
1809
1810 if (lso_ctrl) {
1811 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1812 /* include header and FCS in value given to h/w */
1813 mss_mfs = skb_shinfo(skb)->gso_size +
1814 skb_transport_offset(skb) +
1815 ETH_FCS_LEN;
1816 else /* TSO */ {
1817 mss_mfs = skb_shinfo(skb)->gso_size;
1818 /* TCP Sequence Number Source Select
1819 * can be set only for TSO
1820 */
1821 seq_ctrl = 0;
1822 }
1823 }
1824
1825 do {
1826 i--;
1827 entry = macb_tx_ring_wrap(bp, i);
1828 tx_skb = &queue->tx_skb[entry];
1829 desc = macb_tx_desc(queue, entry);
1830
1831 ctrl = (u32)tx_skb->size;
1832 if (eof) {
1833 ctrl |= MACB_BIT(TX_LAST);
1834 eof = 0;
1835 }
1836 if (unlikely(entry == (bp->tx_ring_size - 1)))
1837 ctrl |= MACB_BIT(TX_WRAP);
1838
1839 /* First descriptor is header descriptor */
1840 if (i == queue->tx_head) {
1841 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1842 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1843 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1844 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1845 ctrl |= MACB_BIT(TX_NOCRC);
1846 } else
1847 /* Only set MSS/MFS on payload descriptors
1848 * (second or later descriptor)
1849 */
1850 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1851
1852 /* Set TX buffer descriptor */
1853 macb_set_addr(bp, desc, tx_skb->mapping);
1854 /* desc->addr must be visible to hardware before clearing
1855 * 'TX_USED' bit in desc->ctrl.
1856 */
1857 wmb();
1858 desc->ctrl = ctrl;
1859 } while (i != queue->tx_head);
1860
1861 queue->tx_head = tx_head;
1862
1863 return count;
1864
1865 dma_error:
1866 netdev_err(bp->dev, "TX DMA map failed\n");
1867
1868 for (i = queue->tx_head; i != tx_head; i++) {
1869 tx_skb = macb_tx_skb(queue, i);
1870
1871 macb_tx_unmap(bp, tx_skb);
1872 }
1873
1874 return 0;
1875 }
1876
macb_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)1877 static netdev_features_t macb_features_check(struct sk_buff *skb,
1878 struct net_device *dev,
1879 netdev_features_t features)
1880 {
1881 unsigned int nr_frags, f;
1882 unsigned int hdrlen;
1883
1884 /* Validate LSO compatibility */
1885
1886 /* there is only one buffer or protocol is not UDP */
1887 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
1888 return features;
1889
1890 /* length of header */
1891 hdrlen = skb_transport_offset(skb);
1892
1893 /* For UFO only:
1894 * When software supplies two or more payload buffers all payload buffers
1895 * apart from the last must be a multiple of 8 bytes in size.
1896 */
1897 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1898 return features & ~MACB_NETIF_LSO;
1899
1900 nr_frags = skb_shinfo(skb)->nr_frags;
1901 /* No need to check last fragment */
1902 nr_frags--;
1903 for (f = 0; f < nr_frags; f++) {
1904 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1905
1906 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1907 return features & ~MACB_NETIF_LSO;
1908 }
1909 return features;
1910 }
1911
macb_clear_csum(struct sk_buff * skb)1912 static inline int macb_clear_csum(struct sk_buff *skb)
1913 {
1914 /* no change for packets without checksum offloading */
1915 if (skb->ip_summed != CHECKSUM_PARTIAL)
1916 return 0;
1917
1918 /* make sure we can modify the header */
1919 if (unlikely(skb_cow_head(skb, 0)))
1920 return -1;
1921
1922 /* initialize checksum field
1923 * This is required - at least for Zynq, which otherwise calculates
1924 * wrong UDP header checksums for UDP packets with UDP data len <=2
1925 */
1926 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1927 return 0;
1928 }
1929
macb_pad_and_fcs(struct sk_buff ** skb,struct net_device * ndev)1930 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1931 {
1932 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
1933 skb_is_nonlinear(*skb);
1934 int padlen = ETH_ZLEN - (*skb)->len;
1935 int headroom = skb_headroom(*skb);
1936 int tailroom = skb_tailroom(*skb);
1937 struct sk_buff *nskb;
1938 u32 fcs;
1939
1940 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1941 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1942 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1943 return 0;
1944
1945 if (padlen <= 0) {
1946 /* FCS could be appeded to tailroom. */
1947 if (tailroom >= ETH_FCS_LEN)
1948 goto add_fcs;
1949 /* FCS could be appeded by moving data to headroom. */
1950 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
1951 padlen = 0;
1952 /* No room for FCS, need to reallocate skb. */
1953 else
1954 padlen = ETH_FCS_LEN;
1955 } else {
1956 /* Add room for FCS. */
1957 padlen += ETH_FCS_LEN;
1958 }
1959
1960 if (!cloned && headroom + tailroom >= padlen) {
1961 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
1962 skb_set_tail_pointer(*skb, (*skb)->len);
1963 } else {
1964 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1965 if (!nskb)
1966 return -ENOMEM;
1967
1968 dev_consume_skb_any(*skb);
1969 *skb = nskb;
1970 }
1971
1972 if (padlen > ETH_FCS_LEN)
1973 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
1974
1975 add_fcs:
1976 /* set FCS to packet */
1977 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
1978 fcs = ~fcs;
1979
1980 skb_put_u8(*skb, fcs & 0xff);
1981 skb_put_u8(*skb, (fcs >> 8) & 0xff);
1982 skb_put_u8(*skb, (fcs >> 16) & 0xff);
1983 skb_put_u8(*skb, (fcs >> 24) & 0xff);
1984
1985 return 0;
1986 }
1987
macb_start_xmit(struct sk_buff * skb,struct net_device * dev)1988 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1989 {
1990 u16 queue_index = skb_get_queue_mapping(skb);
1991 struct macb *bp = netdev_priv(dev);
1992 struct macb_queue *queue = &bp->queues[queue_index];
1993 unsigned long flags;
1994 unsigned int desc_cnt, nr_frags, frag_size, f;
1995 unsigned int hdrlen;
1996 bool is_lso;
1997 netdev_tx_t ret = NETDEV_TX_OK;
1998
1999 if (macb_clear_csum(skb)) {
2000 dev_kfree_skb_any(skb);
2001 return ret;
2002 }
2003
2004 if (macb_pad_and_fcs(&skb, dev)) {
2005 dev_kfree_skb_any(skb);
2006 return ret;
2007 }
2008
2009 is_lso = (skb_shinfo(skb)->gso_size != 0);
2010
2011 if (is_lso) {
2012 /* length of headers */
2013 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2014 /* only queue eth + ip headers separately for UDP */
2015 hdrlen = skb_transport_offset(skb);
2016 else
2017 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
2018 if (skb_headlen(skb) < hdrlen) {
2019 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2020 /* if this is required, would need to copy to single buffer */
2021 return NETDEV_TX_BUSY;
2022 }
2023 } else
2024 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2025
2026 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
2027 netdev_vdbg(bp->dev,
2028 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2029 queue_index, skb->len, skb->head, skb->data,
2030 skb_tail_pointer(skb), skb_end_pointer(skb));
2031 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2032 skb->data, 16, true);
2033 #endif
2034
2035 /* Count how many TX buffer descriptors are needed to send this
2036 * socket buffer: skb fragments of jumbo frames may need to be
2037 * split into many buffer descriptors.
2038 */
2039 if (is_lso && (skb_headlen(skb) > hdrlen))
2040 /* extra header descriptor if also payload in first buffer */
2041 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2042 else
2043 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2044 nr_frags = skb_shinfo(skb)->nr_frags;
2045 for (f = 0; f < nr_frags; f++) {
2046 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2047 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2048 }
2049
2050 spin_lock_irqsave(&bp->lock, flags);
2051
2052 /* This is a hard error, log it. */
2053 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2054 bp->tx_ring_size) < desc_cnt) {
2055 netif_stop_subqueue(dev, queue_index);
2056 spin_unlock_irqrestore(&bp->lock, flags);
2057 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2058 queue->tx_head, queue->tx_tail);
2059 return NETDEV_TX_BUSY;
2060 }
2061
2062 /* Map socket buffer for DMA transfer */
2063 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2064 dev_kfree_skb_any(skb);
2065 goto unlock;
2066 }
2067
2068 /* Make newly initialized descriptor visible to hardware */
2069 wmb();
2070 skb_tx_timestamp(skb);
2071
2072 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2073
2074 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2075 netif_stop_subqueue(dev, queue_index);
2076
2077 unlock:
2078 spin_unlock_irqrestore(&bp->lock, flags);
2079
2080 return ret;
2081 }
2082
macb_init_rx_buffer_size(struct macb * bp,size_t size)2083 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2084 {
2085 if (!macb_is_gem(bp)) {
2086 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2087 } else {
2088 bp->rx_buffer_size = size;
2089
2090 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2091 netdev_dbg(bp->dev,
2092 "RX buffer must be multiple of %d bytes, expanding\n",
2093 RX_BUFFER_MULTIPLE);
2094 bp->rx_buffer_size =
2095 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2096 }
2097 }
2098
2099 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2100 bp->dev->mtu, bp->rx_buffer_size);
2101 }
2102
gem_free_rx_buffers(struct macb * bp)2103 static void gem_free_rx_buffers(struct macb *bp)
2104 {
2105 struct sk_buff *skb;
2106 struct macb_dma_desc *desc;
2107 struct macb_queue *queue;
2108 dma_addr_t addr;
2109 unsigned int q;
2110 int i;
2111
2112 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2113 if (!queue->rx_skbuff)
2114 continue;
2115
2116 for (i = 0; i < bp->rx_ring_size; i++) {
2117 skb = queue->rx_skbuff[i];
2118
2119 if (!skb)
2120 continue;
2121
2122 desc = macb_rx_desc(queue, i);
2123 addr = macb_get_addr(bp, desc);
2124
2125 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2126 DMA_FROM_DEVICE);
2127 dev_kfree_skb_any(skb);
2128 skb = NULL;
2129 }
2130
2131 kfree(queue->rx_skbuff);
2132 queue->rx_skbuff = NULL;
2133 }
2134 }
2135
macb_free_rx_buffers(struct macb * bp)2136 static void macb_free_rx_buffers(struct macb *bp)
2137 {
2138 struct macb_queue *queue = &bp->queues[0];
2139
2140 if (queue->rx_buffers) {
2141 dma_free_coherent(&bp->pdev->dev,
2142 bp->rx_ring_size * bp->rx_buffer_size,
2143 queue->rx_buffers, queue->rx_buffers_dma);
2144 queue->rx_buffers = NULL;
2145 }
2146 }
2147
macb_free_consistent(struct macb * bp)2148 static void macb_free_consistent(struct macb *bp)
2149 {
2150 struct macb_queue *queue;
2151 unsigned int q;
2152 int size;
2153
2154 bp->macbgem_ops.mog_free_rx_buffers(bp);
2155
2156 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2157 kfree(queue->tx_skb);
2158 queue->tx_skb = NULL;
2159 if (queue->tx_ring) {
2160 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2161 dma_free_coherent(&bp->pdev->dev, size,
2162 queue->tx_ring, queue->tx_ring_dma);
2163 queue->tx_ring = NULL;
2164 }
2165 if (queue->rx_ring) {
2166 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2167 dma_free_coherent(&bp->pdev->dev, size,
2168 queue->rx_ring, queue->rx_ring_dma);
2169 queue->rx_ring = NULL;
2170 }
2171 }
2172 }
2173
gem_alloc_rx_buffers(struct macb * bp)2174 static int gem_alloc_rx_buffers(struct macb *bp)
2175 {
2176 struct macb_queue *queue;
2177 unsigned int q;
2178 int size;
2179
2180 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2181 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2182 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2183 if (!queue->rx_skbuff)
2184 return -ENOMEM;
2185 else
2186 netdev_dbg(bp->dev,
2187 "Allocated %d RX struct sk_buff entries at %p\n",
2188 bp->rx_ring_size, queue->rx_skbuff);
2189 }
2190 return 0;
2191 }
2192
macb_alloc_rx_buffers(struct macb * bp)2193 static int macb_alloc_rx_buffers(struct macb *bp)
2194 {
2195 struct macb_queue *queue = &bp->queues[0];
2196 int size;
2197
2198 size = bp->rx_ring_size * bp->rx_buffer_size;
2199 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2200 &queue->rx_buffers_dma, GFP_KERNEL);
2201 if (!queue->rx_buffers)
2202 return -ENOMEM;
2203
2204 netdev_dbg(bp->dev,
2205 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2206 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2207 return 0;
2208 }
2209
macb_alloc_consistent(struct macb * bp)2210 static int macb_alloc_consistent(struct macb *bp)
2211 {
2212 struct macb_queue *queue;
2213 unsigned int q;
2214 int size;
2215
2216 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2217 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2218 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2219 &queue->tx_ring_dma,
2220 GFP_KERNEL);
2221 if (!queue->tx_ring)
2222 goto out_err;
2223 netdev_dbg(bp->dev,
2224 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2225 q, size, (unsigned long)queue->tx_ring_dma,
2226 queue->tx_ring);
2227
2228 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2229 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2230 if (!queue->tx_skb)
2231 goto out_err;
2232
2233 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2234 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2235 &queue->rx_ring_dma, GFP_KERNEL);
2236 if (!queue->rx_ring)
2237 goto out_err;
2238 netdev_dbg(bp->dev,
2239 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2240 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2241 }
2242 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2243 goto out_err;
2244
2245 return 0;
2246
2247 out_err:
2248 macb_free_consistent(bp);
2249 return -ENOMEM;
2250 }
2251
gem_init_rings(struct macb * bp)2252 static void gem_init_rings(struct macb *bp)
2253 {
2254 struct macb_queue *queue;
2255 struct macb_dma_desc *desc = NULL;
2256 unsigned int q;
2257 int i;
2258
2259 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2260 for (i = 0; i < bp->tx_ring_size; i++) {
2261 desc = macb_tx_desc(queue, i);
2262 macb_set_addr(bp, desc, 0);
2263 desc->ctrl = MACB_BIT(TX_USED);
2264 }
2265 desc->ctrl |= MACB_BIT(TX_WRAP);
2266 queue->tx_head = 0;
2267 queue->tx_tail = 0;
2268
2269 queue->rx_tail = 0;
2270 queue->rx_prepared_head = 0;
2271
2272 gem_rx_refill(queue);
2273 }
2274
2275 }
2276
macb_init_rings(struct macb * bp)2277 static void macb_init_rings(struct macb *bp)
2278 {
2279 int i;
2280 struct macb_dma_desc *desc = NULL;
2281
2282 macb_init_rx_ring(&bp->queues[0]);
2283
2284 for (i = 0; i < bp->tx_ring_size; i++) {
2285 desc = macb_tx_desc(&bp->queues[0], i);
2286 macb_set_addr(bp, desc, 0);
2287 desc->ctrl = MACB_BIT(TX_USED);
2288 }
2289 bp->queues[0].tx_head = 0;
2290 bp->queues[0].tx_tail = 0;
2291 desc->ctrl |= MACB_BIT(TX_WRAP);
2292 }
2293
macb_reset_hw(struct macb * bp)2294 static void macb_reset_hw(struct macb *bp)
2295 {
2296 struct macb_queue *queue;
2297 unsigned int q;
2298 u32 ctrl = macb_readl(bp, NCR);
2299
2300 /* Disable RX and TX (XXX: Should we halt the transmission
2301 * more gracefully?)
2302 */
2303 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2304
2305 /* Clear the stats registers (XXX: Update stats first?) */
2306 ctrl |= MACB_BIT(CLRSTAT);
2307
2308 macb_writel(bp, NCR, ctrl);
2309
2310 /* Clear all status flags */
2311 macb_writel(bp, TSR, -1);
2312 macb_writel(bp, RSR, -1);
2313
2314 /* Disable all interrupts */
2315 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2316 queue_writel(queue, IDR, -1);
2317 queue_readl(queue, ISR);
2318 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2319 queue_writel(queue, ISR, -1);
2320 }
2321 }
2322
gem_mdc_clk_div(struct macb * bp)2323 static u32 gem_mdc_clk_div(struct macb *bp)
2324 {
2325 u32 config;
2326 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2327
2328 if (pclk_hz <= 20000000)
2329 config = GEM_BF(CLK, GEM_CLK_DIV8);
2330 else if (pclk_hz <= 40000000)
2331 config = GEM_BF(CLK, GEM_CLK_DIV16);
2332 else if (pclk_hz <= 80000000)
2333 config = GEM_BF(CLK, GEM_CLK_DIV32);
2334 else if (pclk_hz <= 120000000)
2335 config = GEM_BF(CLK, GEM_CLK_DIV48);
2336 else if (pclk_hz <= 160000000)
2337 config = GEM_BF(CLK, GEM_CLK_DIV64);
2338 else
2339 config = GEM_BF(CLK, GEM_CLK_DIV96);
2340
2341 return config;
2342 }
2343
macb_mdc_clk_div(struct macb * bp)2344 static u32 macb_mdc_clk_div(struct macb *bp)
2345 {
2346 u32 config;
2347 unsigned long pclk_hz;
2348
2349 if (macb_is_gem(bp))
2350 return gem_mdc_clk_div(bp);
2351
2352 pclk_hz = clk_get_rate(bp->pclk);
2353 if (pclk_hz <= 20000000)
2354 config = MACB_BF(CLK, MACB_CLK_DIV8);
2355 else if (pclk_hz <= 40000000)
2356 config = MACB_BF(CLK, MACB_CLK_DIV16);
2357 else if (pclk_hz <= 80000000)
2358 config = MACB_BF(CLK, MACB_CLK_DIV32);
2359 else
2360 config = MACB_BF(CLK, MACB_CLK_DIV64);
2361
2362 return config;
2363 }
2364
2365 /* Get the DMA bus width field of the network configuration register that we
2366 * should program. We find the width from decoding the design configuration
2367 * register to find the maximum supported data bus width.
2368 */
macb_dbw(struct macb * bp)2369 static u32 macb_dbw(struct macb *bp)
2370 {
2371 if (!macb_is_gem(bp))
2372 return 0;
2373
2374 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2375 case 4:
2376 return GEM_BF(DBW, GEM_DBW128);
2377 case 2:
2378 return GEM_BF(DBW, GEM_DBW64);
2379 case 1:
2380 default:
2381 return GEM_BF(DBW, GEM_DBW32);
2382 }
2383 }
2384
2385 /* Configure the receive DMA engine
2386 * - use the correct receive buffer size
2387 * - set best burst length for DMA operations
2388 * (if not supported by FIFO, it will fallback to default)
2389 * - set both rx/tx packet buffers to full memory size
2390 * These are configurable parameters for GEM.
2391 */
macb_configure_dma(struct macb * bp)2392 static void macb_configure_dma(struct macb *bp)
2393 {
2394 struct macb_queue *queue;
2395 u32 buffer_size;
2396 unsigned int q;
2397 u32 dmacfg;
2398
2399 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2400 if (macb_is_gem(bp)) {
2401 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2402 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2403 if (q)
2404 queue_writel(queue, RBQS, buffer_size);
2405 else
2406 dmacfg |= GEM_BF(RXBS, buffer_size);
2407 }
2408 if (bp->dma_burst_length)
2409 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2410 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2411 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2412
2413 if (bp->native_io)
2414 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2415 else
2416 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2417
2418 if (bp->dev->features & NETIF_F_HW_CSUM)
2419 dmacfg |= GEM_BIT(TXCOEN);
2420 else
2421 dmacfg &= ~GEM_BIT(TXCOEN);
2422
2423 dmacfg &= ~GEM_BIT(ADDR64);
2424 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2425 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2426 dmacfg |= GEM_BIT(ADDR64);
2427 #endif
2428 #ifdef CONFIG_MACB_USE_HWSTAMP
2429 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2430 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2431 #endif
2432 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2433 dmacfg);
2434 gem_writel(bp, DMACFG, dmacfg);
2435 }
2436 }
2437
macb_init_hw(struct macb * bp)2438 static void macb_init_hw(struct macb *bp)
2439 {
2440 u32 config;
2441
2442 macb_reset_hw(bp);
2443 macb_set_hwaddr(bp);
2444
2445 config = macb_mdc_clk_div(bp);
2446 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2447 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2448 if (bp->caps & MACB_CAPS_JUMBO)
2449 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2450 else
2451 config |= MACB_BIT(BIG); /* Receive oversized frames */
2452 if (bp->dev->flags & IFF_PROMISC)
2453 config |= MACB_BIT(CAF); /* Copy All Frames */
2454 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2455 config |= GEM_BIT(RXCOEN);
2456 if (!(bp->dev->flags & IFF_BROADCAST))
2457 config |= MACB_BIT(NBC); /* No BroadCast */
2458 config |= macb_dbw(bp);
2459 macb_writel(bp, NCFGR, config);
2460 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2461 gem_writel(bp, JML, bp->jumbo_max_len);
2462 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2463 if (bp->caps & MACB_CAPS_JUMBO)
2464 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2465
2466 macb_configure_dma(bp);
2467 }
2468
2469 /* The hash address register is 64 bits long and takes up two
2470 * locations in the memory map. The least significant bits are stored
2471 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2472 *
2473 * The unicast hash enable and the multicast hash enable bits in the
2474 * network configuration register enable the reception of hash matched
2475 * frames. The destination address is reduced to a 6 bit index into
2476 * the 64 bit hash register using the following hash function. The
2477 * hash function is an exclusive or of every sixth bit of the
2478 * destination address.
2479 *
2480 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2481 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2482 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2483 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2484 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2485 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2486 *
2487 * da[0] represents the least significant bit of the first byte
2488 * received, that is, the multicast/unicast indicator, and da[47]
2489 * represents the most significant bit of the last byte received. If
2490 * the hash index, hi[n], points to a bit that is set in the hash
2491 * register then the frame will be matched according to whether the
2492 * frame is multicast or unicast. A multicast match will be signalled
2493 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2494 * index points to a bit set in the hash register. A unicast match
2495 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2496 * and the hash index points to a bit set in the hash register. To
2497 * receive all multicast frames, the hash register should be set with
2498 * all ones and the multicast hash enable bit should be set in the
2499 * network configuration register.
2500 */
2501
hash_bit_value(int bitnr,__u8 * addr)2502 static inline int hash_bit_value(int bitnr, __u8 *addr)
2503 {
2504 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2505 return 1;
2506 return 0;
2507 }
2508
2509 /* Return the hash index value for the specified address. */
hash_get_index(__u8 * addr)2510 static int hash_get_index(__u8 *addr)
2511 {
2512 int i, j, bitval;
2513 int hash_index = 0;
2514
2515 for (j = 0; j < 6; j++) {
2516 for (i = 0, bitval = 0; i < 8; i++)
2517 bitval ^= hash_bit_value(i * 6 + j, addr);
2518
2519 hash_index |= (bitval << j);
2520 }
2521
2522 return hash_index;
2523 }
2524
2525 /* Add multicast addresses to the internal multicast-hash table. */
macb_sethashtable(struct net_device * dev)2526 static void macb_sethashtable(struct net_device *dev)
2527 {
2528 struct netdev_hw_addr *ha;
2529 unsigned long mc_filter[2];
2530 unsigned int bitnr;
2531 struct macb *bp = netdev_priv(dev);
2532
2533 mc_filter[0] = 0;
2534 mc_filter[1] = 0;
2535
2536 netdev_for_each_mc_addr(ha, dev) {
2537 bitnr = hash_get_index(ha->addr);
2538 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2539 }
2540
2541 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2542 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2543 }
2544
2545 /* Enable/Disable promiscuous and multicast modes. */
macb_set_rx_mode(struct net_device * dev)2546 static void macb_set_rx_mode(struct net_device *dev)
2547 {
2548 unsigned long cfg;
2549 struct macb *bp = netdev_priv(dev);
2550
2551 cfg = macb_readl(bp, NCFGR);
2552
2553 if (dev->flags & IFF_PROMISC) {
2554 /* Enable promiscuous mode */
2555 cfg |= MACB_BIT(CAF);
2556
2557 /* Disable RX checksum offload */
2558 if (macb_is_gem(bp))
2559 cfg &= ~GEM_BIT(RXCOEN);
2560 } else {
2561 /* Disable promiscuous mode */
2562 cfg &= ~MACB_BIT(CAF);
2563
2564 /* Enable RX checksum offload only if requested */
2565 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2566 cfg |= GEM_BIT(RXCOEN);
2567 }
2568
2569 if (dev->flags & IFF_ALLMULTI) {
2570 /* Enable all multicast mode */
2571 macb_or_gem_writel(bp, HRB, -1);
2572 macb_or_gem_writel(bp, HRT, -1);
2573 cfg |= MACB_BIT(NCFGR_MTI);
2574 } else if (!netdev_mc_empty(dev)) {
2575 /* Enable specific multicasts */
2576 macb_sethashtable(dev);
2577 cfg |= MACB_BIT(NCFGR_MTI);
2578 } else if (dev->flags & (~IFF_ALLMULTI)) {
2579 /* Disable all multicast mode */
2580 macb_or_gem_writel(bp, HRB, 0);
2581 macb_or_gem_writel(bp, HRT, 0);
2582 cfg &= ~MACB_BIT(NCFGR_MTI);
2583 }
2584
2585 macb_writel(bp, NCFGR, cfg);
2586 }
2587
macb_open(struct net_device * dev)2588 static int macb_open(struct net_device *dev)
2589 {
2590 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2591 struct macb *bp = netdev_priv(dev);
2592 struct macb_queue *queue;
2593 unsigned int q;
2594 int err;
2595
2596 netdev_dbg(bp->dev, "open\n");
2597
2598 err = pm_runtime_get_sync(&bp->pdev->dev);
2599 if (err < 0)
2600 goto pm_exit;
2601
2602 /* RX buffers initialization */
2603 macb_init_rx_buffer_size(bp, bufsz);
2604
2605 err = macb_alloc_consistent(bp);
2606 if (err) {
2607 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2608 err);
2609 goto pm_exit;
2610 }
2611
2612 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2613 napi_enable(&queue->napi);
2614
2615 macb_init_hw(bp);
2616
2617 err = macb_phylink_connect(bp);
2618 if (err)
2619 goto reset_hw;
2620
2621 netif_tx_start_all_queues(dev);
2622
2623 if (bp->ptp_info)
2624 bp->ptp_info->ptp_init(dev);
2625
2626 return 0;
2627
2628 reset_hw:
2629 macb_reset_hw(bp);
2630 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2631 napi_disable(&queue->napi);
2632 macb_free_consistent(bp);
2633 pm_exit:
2634 pm_runtime_put_sync(&bp->pdev->dev);
2635 return err;
2636 }
2637
macb_close(struct net_device * dev)2638 static int macb_close(struct net_device *dev)
2639 {
2640 struct macb *bp = netdev_priv(dev);
2641 struct macb_queue *queue;
2642 unsigned long flags;
2643 unsigned int q;
2644
2645 netif_tx_stop_all_queues(dev);
2646
2647 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2648 napi_disable(&queue->napi);
2649
2650 phylink_stop(bp->phylink);
2651 phylink_disconnect_phy(bp->phylink);
2652
2653 spin_lock_irqsave(&bp->lock, flags);
2654 macb_reset_hw(bp);
2655 netif_carrier_off(dev);
2656 spin_unlock_irqrestore(&bp->lock, flags);
2657
2658 macb_free_consistent(bp);
2659
2660 if (bp->ptp_info)
2661 bp->ptp_info->ptp_remove(dev);
2662
2663 pm_runtime_put(&bp->pdev->dev);
2664
2665 return 0;
2666 }
2667
macb_change_mtu(struct net_device * dev,int new_mtu)2668 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2669 {
2670 if (netif_running(dev))
2671 return -EBUSY;
2672
2673 dev->mtu = new_mtu;
2674
2675 return 0;
2676 }
2677
gem_update_stats(struct macb * bp)2678 static void gem_update_stats(struct macb *bp)
2679 {
2680 struct macb_queue *queue;
2681 unsigned int i, q, idx;
2682 unsigned long *stat;
2683
2684 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2685
2686 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2687 u32 offset = gem_statistics[i].offset;
2688 u64 val = bp->macb_reg_readl(bp, offset);
2689
2690 bp->ethtool_stats[i] += val;
2691 *p += val;
2692
2693 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2694 /* Add GEM_OCTTXH, GEM_OCTRXH */
2695 val = bp->macb_reg_readl(bp, offset + 4);
2696 bp->ethtool_stats[i] += ((u64)val) << 32;
2697 *(++p) += val;
2698 }
2699 }
2700
2701 idx = GEM_STATS_LEN;
2702 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2703 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2704 bp->ethtool_stats[idx++] = *stat;
2705 }
2706
gem_get_stats(struct macb * bp)2707 static struct net_device_stats *gem_get_stats(struct macb *bp)
2708 {
2709 struct gem_stats *hwstat = &bp->hw_stats.gem;
2710 struct net_device_stats *nstat = &bp->dev->stats;
2711
2712 if (!netif_running(bp->dev))
2713 return nstat;
2714
2715 gem_update_stats(bp);
2716
2717 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2718 hwstat->rx_alignment_errors +
2719 hwstat->rx_resource_errors +
2720 hwstat->rx_overruns +
2721 hwstat->rx_oversize_frames +
2722 hwstat->rx_jabbers +
2723 hwstat->rx_undersized_frames +
2724 hwstat->rx_length_field_frame_errors);
2725 nstat->tx_errors = (hwstat->tx_late_collisions +
2726 hwstat->tx_excessive_collisions +
2727 hwstat->tx_underrun +
2728 hwstat->tx_carrier_sense_errors);
2729 nstat->multicast = hwstat->rx_multicast_frames;
2730 nstat->collisions = (hwstat->tx_single_collision_frames +
2731 hwstat->tx_multiple_collision_frames +
2732 hwstat->tx_excessive_collisions);
2733 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2734 hwstat->rx_jabbers +
2735 hwstat->rx_undersized_frames +
2736 hwstat->rx_length_field_frame_errors);
2737 nstat->rx_over_errors = hwstat->rx_resource_errors;
2738 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2739 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2740 nstat->rx_fifo_errors = hwstat->rx_overruns;
2741 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2742 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2743 nstat->tx_fifo_errors = hwstat->tx_underrun;
2744
2745 return nstat;
2746 }
2747
gem_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2748 static void gem_get_ethtool_stats(struct net_device *dev,
2749 struct ethtool_stats *stats, u64 *data)
2750 {
2751 struct macb *bp;
2752
2753 bp = netdev_priv(dev);
2754 gem_update_stats(bp);
2755 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2756 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2757 }
2758
gem_get_sset_count(struct net_device * dev,int sset)2759 static int gem_get_sset_count(struct net_device *dev, int sset)
2760 {
2761 struct macb *bp = netdev_priv(dev);
2762
2763 switch (sset) {
2764 case ETH_SS_STATS:
2765 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2766 default:
2767 return -EOPNOTSUPP;
2768 }
2769 }
2770
gem_get_ethtool_strings(struct net_device * dev,u32 sset,u8 * p)2771 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2772 {
2773 char stat_string[ETH_GSTRING_LEN];
2774 struct macb *bp = netdev_priv(dev);
2775 struct macb_queue *queue;
2776 unsigned int i;
2777 unsigned int q;
2778
2779 switch (sset) {
2780 case ETH_SS_STATS:
2781 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2782 memcpy(p, gem_statistics[i].stat_string,
2783 ETH_GSTRING_LEN);
2784
2785 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2786 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2787 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2788 q, queue_statistics[i].stat_string);
2789 memcpy(p, stat_string, ETH_GSTRING_LEN);
2790 }
2791 }
2792 break;
2793 }
2794 }
2795
macb_get_stats(struct net_device * dev)2796 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2797 {
2798 struct macb *bp = netdev_priv(dev);
2799 struct net_device_stats *nstat = &bp->dev->stats;
2800 struct macb_stats *hwstat = &bp->hw_stats.macb;
2801
2802 if (macb_is_gem(bp))
2803 return gem_get_stats(bp);
2804
2805 /* read stats from hardware */
2806 macb_update_stats(bp);
2807
2808 /* Convert HW stats into netdevice stats */
2809 nstat->rx_errors = (hwstat->rx_fcs_errors +
2810 hwstat->rx_align_errors +
2811 hwstat->rx_resource_errors +
2812 hwstat->rx_overruns +
2813 hwstat->rx_oversize_pkts +
2814 hwstat->rx_jabbers +
2815 hwstat->rx_undersize_pkts +
2816 hwstat->rx_length_mismatch);
2817 nstat->tx_errors = (hwstat->tx_late_cols +
2818 hwstat->tx_excessive_cols +
2819 hwstat->tx_underruns +
2820 hwstat->tx_carrier_errors +
2821 hwstat->sqe_test_errors);
2822 nstat->collisions = (hwstat->tx_single_cols +
2823 hwstat->tx_multiple_cols +
2824 hwstat->tx_excessive_cols);
2825 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2826 hwstat->rx_jabbers +
2827 hwstat->rx_undersize_pkts +
2828 hwstat->rx_length_mismatch);
2829 nstat->rx_over_errors = hwstat->rx_resource_errors +
2830 hwstat->rx_overruns;
2831 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2832 nstat->rx_frame_errors = hwstat->rx_align_errors;
2833 nstat->rx_fifo_errors = hwstat->rx_overruns;
2834 /* XXX: What does "missed" mean? */
2835 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2836 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2837 nstat->tx_fifo_errors = hwstat->tx_underruns;
2838 /* Don't know about heartbeat or window errors... */
2839
2840 return nstat;
2841 }
2842
macb_get_regs_len(struct net_device * netdev)2843 static int macb_get_regs_len(struct net_device *netdev)
2844 {
2845 return MACB_GREGS_NBR * sizeof(u32);
2846 }
2847
macb_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)2848 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2849 void *p)
2850 {
2851 struct macb *bp = netdev_priv(dev);
2852 unsigned int tail, head;
2853 u32 *regs_buff = p;
2854
2855 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2856 | MACB_GREGS_VERSION;
2857
2858 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2859 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2860
2861 regs_buff[0] = macb_readl(bp, NCR);
2862 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2863 regs_buff[2] = macb_readl(bp, NSR);
2864 regs_buff[3] = macb_readl(bp, TSR);
2865 regs_buff[4] = macb_readl(bp, RBQP);
2866 regs_buff[5] = macb_readl(bp, TBQP);
2867 regs_buff[6] = macb_readl(bp, RSR);
2868 regs_buff[7] = macb_readl(bp, IMR);
2869
2870 regs_buff[8] = tail;
2871 regs_buff[9] = head;
2872 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2873 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2874
2875 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2876 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2877 if (macb_is_gem(bp))
2878 regs_buff[13] = gem_readl(bp, DMACFG);
2879 }
2880
macb_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)2881 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2882 {
2883 struct macb *bp = netdev_priv(netdev);
2884
2885 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2886 phylink_ethtool_get_wol(bp->phylink, wol);
2887 wol->supported |= WAKE_MAGIC;
2888
2889 if (bp->wol & MACB_WOL_ENABLED)
2890 wol->wolopts |= WAKE_MAGIC;
2891 }
2892 }
2893
macb_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)2894 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2895 {
2896 struct macb *bp = netdev_priv(netdev);
2897 int ret;
2898
2899 /* Pass the order to phylink layer */
2900 ret = phylink_ethtool_set_wol(bp->phylink, wol);
2901 /* Don't manage WoL on MAC if handled by the PHY
2902 * or if there's a failure in talking to the PHY
2903 */
2904 if (!ret || ret != -EOPNOTSUPP)
2905 return ret;
2906
2907 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2908 (wol->wolopts & ~WAKE_MAGIC))
2909 return -EOPNOTSUPP;
2910
2911 if (wol->wolopts & WAKE_MAGIC)
2912 bp->wol |= MACB_WOL_ENABLED;
2913 else
2914 bp->wol &= ~MACB_WOL_ENABLED;
2915
2916 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2917
2918 return 0;
2919 }
2920
macb_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * kset)2921 static int macb_get_link_ksettings(struct net_device *netdev,
2922 struct ethtool_link_ksettings *kset)
2923 {
2924 struct macb *bp = netdev_priv(netdev);
2925
2926 return phylink_ethtool_ksettings_get(bp->phylink, kset);
2927 }
2928
macb_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * kset)2929 static int macb_set_link_ksettings(struct net_device *netdev,
2930 const struct ethtool_link_ksettings *kset)
2931 {
2932 struct macb *bp = netdev_priv(netdev);
2933
2934 return phylink_ethtool_ksettings_set(bp->phylink, kset);
2935 }
2936
macb_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)2937 static void macb_get_ringparam(struct net_device *netdev,
2938 struct ethtool_ringparam *ring)
2939 {
2940 struct macb *bp = netdev_priv(netdev);
2941
2942 ring->rx_max_pending = MAX_RX_RING_SIZE;
2943 ring->tx_max_pending = MAX_TX_RING_SIZE;
2944
2945 ring->rx_pending = bp->rx_ring_size;
2946 ring->tx_pending = bp->tx_ring_size;
2947 }
2948
macb_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)2949 static int macb_set_ringparam(struct net_device *netdev,
2950 struct ethtool_ringparam *ring)
2951 {
2952 struct macb *bp = netdev_priv(netdev);
2953 u32 new_rx_size, new_tx_size;
2954 unsigned int reset = 0;
2955
2956 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2957 return -EINVAL;
2958
2959 new_rx_size = clamp_t(u32, ring->rx_pending,
2960 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2961 new_rx_size = roundup_pow_of_two(new_rx_size);
2962
2963 new_tx_size = clamp_t(u32, ring->tx_pending,
2964 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2965 new_tx_size = roundup_pow_of_two(new_tx_size);
2966
2967 if ((new_tx_size == bp->tx_ring_size) &&
2968 (new_rx_size == bp->rx_ring_size)) {
2969 /* nothing to do */
2970 return 0;
2971 }
2972
2973 if (netif_running(bp->dev)) {
2974 reset = 1;
2975 macb_close(bp->dev);
2976 }
2977
2978 bp->rx_ring_size = new_rx_size;
2979 bp->tx_ring_size = new_tx_size;
2980
2981 if (reset)
2982 macb_open(bp->dev);
2983
2984 return 0;
2985 }
2986
2987 #ifdef CONFIG_MACB_USE_HWSTAMP
gem_get_tsu_rate(struct macb * bp)2988 static unsigned int gem_get_tsu_rate(struct macb *bp)
2989 {
2990 struct clk *tsu_clk;
2991 unsigned int tsu_rate;
2992
2993 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2994 if (!IS_ERR(tsu_clk))
2995 tsu_rate = clk_get_rate(tsu_clk);
2996 /* try pclk instead */
2997 else if (!IS_ERR(bp->pclk)) {
2998 tsu_clk = bp->pclk;
2999 tsu_rate = clk_get_rate(tsu_clk);
3000 } else
3001 return -ENOTSUPP;
3002 return tsu_rate;
3003 }
3004
gem_get_ptp_max_adj(void)3005 static s32 gem_get_ptp_max_adj(void)
3006 {
3007 return 64000000;
3008 }
3009
gem_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)3010 static int gem_get_ts_info(struct net_device *dev,
3011 struct ethtool_ts_info *info)
3012 {
3013 struct macb *bp = netdev_priv(dev);
3014
3015 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3016 ethtool_op_get_ts_info(dev, info);
3017 return 0;
3018 }
3019
3020 info->so_timestamping =
3021 SOF_TIMESTAMPING_TX_SOFTWARE |
3022 SOF_TIMESTAMPING_RX_SOFTWARE |
3023 SOF_TIMESTAMPING_SOFTWARE |
3024 SOF_TIMESTAMPING_TX_HARDWARE |
3025 SOF_TIMESTAMPING_RX_HARDWARE |
3026 SOF_TIMESTAMPING_RAW_HARDWARE;
3027 info->tx_types =
3028 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3029 (1 << HWTSTAMP_TX_OFF) |
3030 (1 << HWTSTAMP_TX_ON);
3031 info->rx_filters =
3032 (1 << HWTSTAMP_FILTER_NONE) |
3033 (1 << HWTSTAMP_FILTER_ALL);
3034
3035 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3036
3037 return 0;
3038 }
3039
3040 static struct macb_ptp_info gem_ptp_info = {
3041 .ptp_init = gem_ptp_init,
3042 .ptp_remove = gem_ptp_remove,
3043 .get_ptp_max_adj = gem_get_ptp_max_adj,
3044 .get_tsu_rate = gem_get_tsu_rate,
3045 .get_ts_info = gem_get_ts_info,
3046 .get_hwtst = gem_get_hwtst,
3047 .set_hwtst = gem_set_hwtst,
3048 };
3049 #endif
3050
macb_get_ts_info(struct net_device * netdev,struct ethtool_ts_info * info)3051 static int macb_get_ts_info(struct net_device *netdev,
3052 struct ethtool_ts_info *info)
3053 {
3054 struct macb *bp = netdev_priv(netdev);
3055
3056 if (bp->ptp_info)
3057 return bp->ptp_info->get_ts_info(netdev, info);
3058
3059 return ethtool_op_get_ts_info(netdev, info);
3060 }
3061
gem_enable_flow_filters(struct macb * bp,bool enable)3062 static void gem_enable_flow_filters(struct macb *bp, bool enable)
3063 {
3064 struct net_device *netdev = bp->dev;
3065 struct ethtool_rx_fs_item *item;
3066 u32 t2_scr;
3067 int num_t2_scr;
3068
3069 if (!(netdev->features & NETIF_F_NTUPLE))
3070 return;
3071
3072 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3073
3074 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3075 struct ethtool_rx_flow_spec *fs = &item->fs;
3076 struct ethtool_tcpip4_spec *tp4sp_m;
3077
3078 if (fs->location >= num_t2_scr)
3079 continue;
3080
3081 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3082
3083 /* enable/disable screener regs for the flow entry */
3084 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3085
3086 /* only enable fields with no masking */
3087 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3088
3089 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3090 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3091 else
3092 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3093
3094 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3095 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3096 else
3097 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3098
3099 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3100 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3101 else
3102 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3103
3104 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3105 }
3106 }
3107
gem_prog_cmp_regs(struct macb * bp,struct ethtool_rx_flow_spec * fs)3108 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3109 {
3110 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3111 uint16_t index = fs->location;
3112 u32 w0, w1, t2_scr;
3113 bool cmp_a = false;
3114 bool cmp_b = false;
3115 bool cmp_c = false;
3116
3117 if (!macb_is_gem(bp))
3118 return;
3119
3120 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3121 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3122
3123 /* ignore field if any masking set */
3124 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3125 /* 1st compare reg - IP source address */
3126 w0 = 0;
3127 w1 = 0;
3128 w0 = tp4sp_v->ip4src;
3129 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3130 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3131 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3132 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3133 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3134 cmp_a = true;
3135 }
3136
3137 /* ignore field if any masking set */
3138 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3139 /* 2nd compare reg - IP destination address */
3140 w0 = 0;
3141 w1 = 0;
3142 w0 = tp4sp_v->ip4dst;
3143 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3144 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3145 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3146 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3147 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3148 cmp_b = true;
3149 }
3150
3151 /* ignore both port fields if masking set in both */
3152 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3153 /* 3rd compare reg - source port, destination port */
3154 w0 = 0;
3155 w1 = 0;
3156 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3157 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3158 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3159 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3160 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3161 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3162 } else {
3163 /* only one port definition */
3164 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3165 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3166 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3167 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3168 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3169 } else { /* dst port */
3170 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3171 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3172 }
3173 }
3174 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3175 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3176 cmp_c = true;
3177 }
3178
3179 t2_scr = 0;
3180 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3181 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3182 if (cmp_a)
3183 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3184 if (cmp_b)
3185 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3186 if (cmp_c)
3187 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3188 gem_writel_n(bp, SCRT2, index, t2_scr);
3189 }
3190
gem_add_flow_filter(struct net_device * netdev,struct ethtool_rxnfc * cmd)3191 static int gem_add_flow_filter(struct net_device *netdev,
3192 struct ethtool_rxnfc *cmd)
3193 {
3194 struct macb *bp = netdev_priv(netdev);
3195 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3196 struct ethtool_rx_fs_item *item, *newfs;
3197 unsigned long flags;
3198 int ret = -EINVAL;
3199 bool added = false;
3200
3201 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3202 if (newfs == NULL)
3203 return -ENOMEM;
3204 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3205
3206 netdev_dbg(netdev,
3207 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3208 fs->flow_type, (int)fs->ring_cookie, fs->location,
3209 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3210 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3211 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3212
3213 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3214
3215 /* find correct place to add in list */
3216 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3217 if (item->fs.location > newfs->fs.location) {
3218 list_add_tail(&newfs->list, &item->list);
3219 added = true;
3220 break;
3221 } else if (item->fs.location == fs->location) {
3222 netdev_err(netdev, "Rule not added: location %d not free!\n",
3223 fs->location);
3224 ret = -EBUSY;
3225 goto err;
3226 }
3227 }
3228 if (!added)
3229 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3230
3231 gem_prog_cmp_regs(bp, fs);
3232 bp->rx_fs_list.count++;
3233 /* enable filtering if NTUPLE on */
3234 gem_enable_flow_filters(bp, 1);
3235
3236 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3237 return 0;
3238
3239 err:
3240 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3241 kfree(newfs);
3242 return ret;
3243 }
3244
gem_del_flow_filter(struct net_device * netdev,struct ethtool_rxnfc * cmd)3245 static int gem_del_flow_filter(struct net_device *netdev,
3246 struct ethtool_rxnfc *cmd)
3247 {
3248 struct macb *bp = netdev_priv(netdev);
3249 struct ethtool_rx_fs_item *item;
3250 struct ethtool_rx_flow_spec *fs;
3251 unsigned long flags;
3252
3253 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3254
3255 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3256 if (item->fs.location == cmd->fs.location) {
3257 /* disable screener regs for the flow entry */
3258 fs = &(item->fs);
3259 netdev_dbg(netdev,
3260 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3261 fs->flow_type, (int)fs->ring_cookie, fs->location,
3262 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3263 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3264 htons(fs->h_u.tcp_ip4_spec.psrc),
3265 htons(fs->h_u.tcp_ip4_spec.pdst));
3266
3267 gem_writel_n(bp, SCRT2, fs->location, 0);
3268
3269 list_del(&item->list);
3270 bp->rx_fs_list.count--;
3271 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3272 kfree(item);
3273 return 0;
3274 }
3275 }
3276
3277 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3278 return -EINVAL;
3279 }
3280
gem_get_flow_entry(struct net_device * netdev,struct ethtool_rxnfc * cmd)3281 static int gem_get_flow_entry(struct net_device *netdev,
3282 struct ethtool_rxnfc *cmd)
3283 {
3284 struct macb *bp = netdev_priv(netdev);
3285 struct ethtool_rx_fs_item *item;
3286
3287 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3288 if (item->fs.location == cmd->fs.location) {
3289 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3290 return 0;
3291 }
3292 }
3293 return -EINVAL;
3294 }
3295
gem_get_all_flow_entries(struct net_device * netdev,struct ethtool_rxnfc * cmd,u32 * rule_locs)3296 static int gem_get_all_flow_entries(struct net_device *netdev,
3297 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3298 {
3299 struct macb *bp = netdev_priv(netdev);
3300 struct ethtool_rx_fs_item *item;
3301 uint32_t cnt = 0;
3302
3303 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3304 if (cnt == cmd->rule_cnt)
3305 return -EMSGSIZE;
3306 rule_locs[cnt] = item->fs.location;
3307 cnt++;
3308 }
3309 cmd->data = bp->max_tuples;
3310 cmd->rule_cnt = cnt;
3311
3312 return 0;
3313 }
3314
gem_get_rxnfc(struct net_device * netdev,struct ethtool_rxnfc * cmd,u32 * rule_locs)3315 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3316 u32 *rule_locs)
3317 {
3318 struct macb *bp = netdev_priv(netdev);
3319 int ret = 0;
3320
3321 switch (cmd->cmd) {
3322 case ETHTOOL_GRXRINGS:
3323 cmd->data = bp->num_queues;
3324 break;
3325 case ETHTOOL_GRXCLSRLCNT:
3326 cmd->rule_cnt = bp->rx_fs_list.count;
3327 break;
3328 case ETHTOOL_GRXCLSRULE:
3329 ret = gem_get_flow_entry(netdev, cmd);
3330 break;
3331 case ETHTOOL_GRXCLSRLALL:
3332 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3333 break;
3334 default:
3335 netdev_err(netdev,
3336 "Command parameter %d is not supported\n", cmd->cmd);
3337 ret = -EOPNOTSUPP;
3338 }
3339
3340 return ret;
3341 }
3342
gem_set_rxnfc(struct net_device * netdev,struct ethtool_rxnfc * cmd)3343 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3344 {
3345 struct macb *bp = netdev_priv(netdev);
3346 int ret;
3347
3348 switch (cmd->cmd) {
3349 case ETHTOOL_SRXCLSRLINS:
3350 if ((cmd->fs.location >= bp->max_tuples)
3351 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3352 ret = -EINVAL;
3353 break;
3354 }
3355 ret = gem_add_flow_filter(netdev, cmd);
3356 break;
3357 case ETHTOOL_SRXCLSRLDEL:
3358 ret = gem_del_flow_filter(netdev, cmd);
3359 break;
3360 default:
3361 netdev_err(netdev,
3362 "Command parameter %d is not supported\n", cmd->cmd);
3363 ret = -EOPNOTSUPP;
3364 }
3365
3366 return ret;
3367 }
3368
3369 static const struct ethtool_ops macb_ethtool_ops = {
3370 .get_regs_len = macb_get_regs_len,
3371 .get_regs = macb_get_regs,
3372 .get_link = ethtool_op_get_link,
3373 .get_ts_info = ethtool_op_get_ts_info,
3374 .get_wol = macb_get_wol,
3375 .set_wol = macb_set_wol,
3376 .get_link_ksettings = macb_get_link_ksettings,
3377 .set_link_ksettings = macb_set_link_ksettings,
3378 .get_ringparam = macb_get_ringparam,
3379 .set_ringparam = macb_set_ringparam,
3380 };
3381
3382 static const struct ethtool_ops gem_ethtool_ops = {
3383 .get_regs_len = macb_get_regs_len,
3384 .get_regs = macb_get_regs,
3385 .get_wol = macb_get_wol,
3386 .set_wol = macb_set_wol,
3387 .get_link = ethtool_op_get_link,
3388 .get_ts_info = macb_get_ts_info,
3389 .get_ethtool_stats = gem_get_ethtool_stats,
3390 .get_strings = gem_get_ethtool_strings,
3391 .get_sset_count = gem_get_sset_count,
3392 .get_link_ksettings = macb_get_link_ksettings,
3393 .set_link_ksettings = macb_set_link_ksettings,
3394 .get_ringparam = macb_get_ringparam,
3395 .set_ringparam = macb_set_ringparam,
3396 .get_rxnfc = gem_get_rxnfc,
3397 .set_rxnfc = gem_set_rxnfc,
3398 };
3399
macb_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)3400 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3401 {
3402 struct macb *bp = netdev_priv(dev);
3403
3404 if (!netif_running(dev))
3405 return -EINVAL;
3406
3407 if (bp->ptp_info) {
3408 switch (cmd) {
3409 case SIOCSHWTSTAMP:
3410 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3411 case SIOCGHWTSTAMP:
3412 return bp->ptp_info->get_hwtst(dev, rq);
3413 }
3414 }
3415
3416 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3417 }
3418
macb_set_txcsum_feature(struct macb * bp,netdev_features_t features)3419 static inline void macb_set_txcsum_feature(struct macb *bp,
3420 netdev_features_t features)
3421 {
3422 u32 val;
3423
3424 if (!macb_is_gem(bp))
3425 return;
3426
3427 val = gem_readl(bp, DMACFG);
3428 if (features & NETIF_F_HW_CSUM)
3429 val |= GEM_BIT(TXCOEN);
3430 else
3431 val &= ~GEM_BIT(TXCOEN);
3432
3433 gem_writel(bp, DMACFG, val);
3434 }
3435
macb_set_rxcsum_feature(struct macb * bp,netdev_features_t features)3436 static inline void macb_set_rxcsum_feature(struct macb *bp,
3437 netdev_features_t features)
3438 {
3439 struct net_device *netdev = bp->dev;
3440 u32 val;
3441
3442 if (!macb_is_gem(bp))
3443 return;
3444
3445 val = gem_readl(bp, NCFGR);
3446 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3447 val |= GEM_BIT(RXCOEN);
3448 else
3449 val &= ~GEM_BIT(RXCOEN);
3450
3451 gem_writel(bp, NCFGR, val);
3452 }
3453
macb_set_rxflow_feature(struct macb * bp,netdev_features_t features)3454 static inline void macb_set_rxflow_feature(struct macb *bp,
3455 netdev_features_t features)
3456 {
3457 if (!macb_is_gem(bp))
3458 return;
3459
3460 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3461 }
3462
macb_set_features(struct net_device * netdev,netdev_features_t features)3463 static int macb_set_features(struct net_device *netdev,
3464 netdev_features_t features)
3465 {
3466 struct macb *bp = netdev_priv(netdev);
3467 netdev_features_t changed = features ^ netdev->features;
3468
3469 /* TX checksum offload */
3470 if (changed & NETIF_F_HW_CSUM)
3471 macb_set_txcsum_feature(bp, features);
3472
3473 /* RX checksum offload */
3474 if (changed & NETIF_F_RXCSUM)
3475 macb_set_rxcsum_feature(bp, features);
3476
3477 /* RX Flow Filters */
3478 if (changed & NETIF_F_NTUPLE)
3479 macb_set_rxflow_feature(bp, features);
3480
3481 return 0;
3482 }
3483
macb_restore_features(struct macb * bp)3484 static void macb_restore_features(struct macb *bp)
3485 {
3486 struct net_device *netdev = bp->dev;
3487 netdev_features_t features = netdev->features;
3488 struct ethtool_rx_fs_item *item;
3489
3490 /* TX checksum offload */
3491 macb_set_txcsum_feature(bp, features);
3492
3493 /* RX checksum offload */
3494 macb_set_rxcsum_feature(bp, features);
3495
3496 /* RX Flow Filters */
3497 list_for_each_entry(item, &bp->rx_fs_list.list, list)
3498 gem_prog_cmp_regs(bp, &item->fs);
3499
3500 macb_set_rxflow_feature(bp, features);
3501 }
3502
3503 static const struct net_device_ops macb_netdev_ops = {
3504 .ndo_open = macb_open,
3505 .ndo_stop = macb_close,
3506 .ndo_start_xmit = macb_start_xmit,
3507 .ndo_set_rx_mode = macb_set_rx_mode,
3508 .ndo_get_stats = macb_get_stats,
3509 .ndo_do_ioctl = macb_ioctl,
3510 .ndo_validate_addr = eth_validate_addr,
3511 .ndo_change_mtu = macb_change_mtu,
3512 .ndo_set_mac_address = eth_mac_addr,
3513 #ifdef CONFIG_NET_POLL_CONTROLLER
3514 .ndo_poll_controller = macb_poll_controller,
3515 #endif
3516 .ndo_set_features = macb_set_features,
3517 .ndo_features_check = macb_features_check,
3518 };
3519
3520 /* Configure peripheral capabilities according to device tree
3521 * and integration options used
3522 */
macb_configure_caps(struct macb * bp,const struct macb_config * dt_conf)3523 static void macb_configure_caps(struct macb *bp,
3524 const struct macb_config *dt_conf)
3525 {
3526 u32 dcfg;
3527
3528 if (dt_conf)
3529 bp->caps = dt_conf->caps;
3530
3531 if (hw_is_gem(bp->regs, bp->native_io)) {
3532 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3533
3534 dcfg = gem_readl(bp, DCFG1);
3535 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3536 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3537 dcfg = gem_readl(bp, DCFG2);
3538 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3539 bp->caps |= MACB_CAPS_FIFO_MODE;
3540 #ifdef CONFIG_MACB_USE_HWSTAMP
3541 if (gem_has_ptp(bp)) {
3542 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3543 dev_err(&bp->pdev->dev,
3544 "GEM doesn't support hardware ptp.\n");
3545 else {
3546 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3547 bp->ptp_info = &gem_ptp_info;
3548 }
3549 }
3550 #endif
3551 }
3552
3553 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3554 }
3555
macb_probe_queues(void __iomem * mem,bool native_io,unsigned int * queue_mask,unsigned int * num_queues)3556 static void macb_probe_queues(void __iomem *mem,
3557 bool native_io,
3558 unsigned int *queue_mask,
3559 unsigned int *num_queues)
3560 {
3561 *queue_mask = 0x1;
3562 *num_queues = 1;
3563
3564 /* is it macb or gem ?
3565 *
3566 * We need to read directly from the hardware here because
3567 * we are early in the probe process and don't have the
3568 * MACB_CAPS_MACB_IS_GEM flag positioned
3569 */
3570 if (!hw_is_gem(mem, native_io))
3571 return;
3572
3573 /* bit 0 is never set but queue 0 always exists */
3574 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3575 *num_queues = hweight32(*queue_mask);
3576 }
3577
macb_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk)3578 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3579 struct clk **hclk, struct clk **tx_clk,
3580 struct clk **rx_clk, struct clk **tsu_clk)
3581 {
3582 struct macb_platform_data *pdata;
3583 int err;
3584
3585 pdata = dev_get_platdata(&pdev->dev);
3586 if (pdata) {
3587 *pclk = pdata->pclk;
3588 *hclk = pdata->hclk;
3589 } else {
3590 *pclk = devm_clk_get(&pdev->dev, "pclk");
3591 *hclk = devm_clk_get(&pdev->dev, "hclk");
3592 }
3593
3594 if (IS_ERR_OR_NULL(*pclk)) {
3595 err = PTR_ERR(*pclk);
3596 if (!err)
3597 err = -ENODEV;
3598
3599 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
3600 return err;
3601 }
3602
3603 if (IS_ERR_OR_NULL(*hclk)) {
3604 err = PTR_ERR(*hclk);
3605 if (!err)
3606 err = -ENODEV;
3607
3608 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
3609 return err;
3610 }
3611
3612 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3613 if (IS_ERR(*tx_clk))
3614 return PTR_ERR(*tx_clk);
3615
3616 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3617 if (IS_ERR(*rx_clk))
3618 return PTR_ERR(*rx_clk);
3619
3620 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3621 if (IS_ERR(*tsu_clk))
3622 return PTR_ERR(*tsu_clk);
3623
3624 err = clk_prepare_enable(*pclk);
3625 if (err) {
3626 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3627 return err;
3628 }
3629
3630 err = clk_prepare_enable(*hclk);
3631 if (err) {
3632 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3633 goto err_disable_pclk;
3634 }
3635
3636 err = clk_prepare_enable(*tx_clk);
3637 if (err) {
3638 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3639 goto err_disable_hclk;
3640 }
3641
3642 err = clk_prepare_enable(*rx_clk);
3643 if (err) {
3644 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3645 goto err_disable_txclk;
3646 }
3647
3648 err = clk_prepare_enable(*tsu_clk);
3649 if (err) {
3650 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3651 goto err_disable_rxclk;
3652 }
3653
3654 return 0;
3655
3656 err_disable_rxclk:
3657 clk_disable_unprepare(*rx_clk);
3658
3659 err_disable_txclk:
3660 clk_disable_unprepare(*tx_clk);
3661
3662 err_disable_hclk:
3663 clk_disable_unprepare(*hclk);
3664
3665 err_disable_pclk:
3666 clk_disable_unprepare(*pclk);
3667
3668 return err;
3669 }
3670
macb_init(struct platform_device * pdev)3671 static int macb_init(struct platform_device *pdev)
3672 {
3673 struct net_device *dev = platform_get_drvdata(pdev);
3674 unsigned int hw_q, q;
3675 struct macb *bp = netdev_priv(dev);
3676 struct macb_queue *queue;
3677 int err;
3678 u32 val, reg;
3679
3680 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3681 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3682
3683 /* set the queue register mapping once for all: queue0 has a special
3684 * register mapping but we don't want to test the queue index then
3685 * compute the corresponding register offset at run time.
3686 */
3687 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3688 if (!(bp->queue_mask & (1 << hw_q)))
3689 continue;
3690
3691 queue = &bp->queues[q];
3692 queue->bp = bp;
3693 netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
3694 if (hw_q) {
3695 queue->ISR = GEM_ISR(hw_q - 1);
3696 queue->IER = GEM_IER(hw_q - 1);
3697 queue->IDR = GEM_IDR(hw_q - 1);
3698 queue->IMR = GEM_IMR(hw_q - 1);
3699 queue->TBQP = GEM_TBQP(hw_q - 1);
3700 queue->RBQP = GEM_RBQP(hw_q - 1);
3701 queue->RBQS = GEM_RBQS(hw_q - 1);
3702 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3703 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3704 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3705 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3706 }
3707 #endif
3708 } else {
3709 /* queue0 uses legacy registers */
3710 queue->ISR = MACB_ISR;
3711 queue->IER = MACB_IER;
3712 queue->IDR = MACB_IDR;
3713 queue->IMR = MACB_IMR;
3714 queue->TBQP = MACB_TBQP;
3715 queue->RBQP = MACB_RBQP;
3716 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3717 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3718 queue->TBQPH = MACB_TBQPH;
3719 queue->RBQPH = MACB_RBQPH;
3720 }
3721 #endif
3722 }
3723
3724 /* get irq: here we use the linux queue index, not the hardware
3725 * queue index. the queue irq definitions in the device tree
3726 * must remove the optional gaps that could exist in the
3727 * hardware queue mask.
3728 */
3729 queue->irq = platform_get_irq(pdev, q);
3730 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3731 IRQF_SHARED, dev->name, queue);
3732 if (err) {
3733 dev_err(&pdev->dev,
3734 "Unable to request IRQ %d (error %d)\n",
3735 queue->irq, err);
3736 return err;
3737 }
3738
3739 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3740 q++;
3741 }
3742
3743 dev->netdev_ops = &macb_netdev_ops;
3744
3745 /* setup appropriated routines according to adapter type */
3746 if (macb_is_gem(bp)) {
3747 bp->max_tx_length = GEM_MAX_TX_LEN;
3748 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3749 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3750 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3751 bp->macbgem_ops.mog_rx = gem_rx;
3752 dev->ethtool_ops = &gem_ethtool_ops;
3753 } else {
3754 bp->max_tx_length = MACB_MAX_TX_LEN;
3755 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3756 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3757 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3758 bp->macbgem_ops.mog_rx = macb_rx;
3759 dev->ethtool_ops = &macb_ethtool_ops;
3760 }
3761
3762 /* Set features */
3763 dev->hw_features = NETIF_F_SG;
3764
3765 /* Check LSO capability */
3766 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3767 dev->hw_features |= MACB_NETIF_LSO;
3768
3769 /* Checksum offload is only available on gem with packet buffer */
3770 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3771 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3772 if (bp->caps & MACB_CAPS_SG_DISABLED)
3773 dev->hw_features &= ~NETIF_F_SG;
3774 dev->features = dev->hw_features;
3775
3776 /* Check RX Flow Filters support.
3777 * Max Rx flows set by availability of screeners & compare regs:
3778 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3779 */
3780 reg = gem_readl(bp, DCFG8);
3781 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3782 GEM_BFEXT(T2SCR, reg));
3783 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3784 if (bp->max_tuples > 0) {
3785 /* also needs one ethtype match to check IPv4 */
3786 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3787 /* program this reg now */
3788 reg = 0;
3789 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3790 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3791 /* Filtering is supported in hw but don't enable it in kernel now */
3792 dev->hw_features |= NETIF_F_NTUPLE;
3793 /* init Rx flow definitions */
3794 bp->rx_fs_list.count = 0;
3795 spin_lock_init(&bp->rx_fs_lock);
3796 } else
3797 bp->max_tuples = 0;
3798 }
3799
3800 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3801 val = 0;
3802 if (phy_interface_mode_is_rgmii(bp->phy_interface))
3803 val = GEM_BIT(RGMII);
3804 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3805 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3806 val = MACB_BIT(RMII);
3807 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3808 val = MACB_BIT(MII);
3809
3810 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3811 val |= MACB_BIT(CLKEN);
3812
3813 macb_or_gem_writel(bp, USRIO, val);
3814 }
3815
3816 /* Set MII management clock divider */
3817 val = macb_mdc_clk_div(bp);
3818 val |= macb_dbw(bp);
3819 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3820 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3821 macb_writel(bp, NCFGR, val);
3822
3823 return 0;
3824 }
3825
3826 #if defined(CONFIG_OF)
3827 /* 1518 rounded up */
3828 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3829 /* max number of receive buffers */
3830 #define AT91ETHER_MAX_RX_DESCR 9
3831
3832 static struct sifive_fu540_macb_mgmt *mgmt;
3833
at91ether_alloc_coherent(struct macb * lp)3834 static int at91ether_alloc_coherent(struct macb *lp)
3835 {
3836 struct macb_queue *q = &lp->queues[0];
3837
3838 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3839 (AT91ETHER_MAX_RX_DESCR *
3840 macb_dma_desc_get_size(lp)),
3841 &q->rx_ring_dma, GFP_KERNEL);
3842 if (!q->rx_ring)
3843 return -ENOMEM;
3844
3845 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3846 AT91ETHER_MAX_RX_DESCR *
3847 AT91ETHER_MAX_RBUFF_SZ,
3848 &q->rx_buffers_dma, GFP_KERNEL);
3849 if (!q->rx_buffers) {
3850 dma_free_coherent(&lp->pdev->dev,
3851 AT91ETHER_MAX_RX_DESCR *
3852 macb_dma_desc_get_size(lp),
3853 q->rx_ring, q->rx_ring_dma);
3854 q->rx_ring = NULL;
3855 return -ENOMEM;
3856 }
3857
3858 return 0;
3859 }
3860
at91ether_free_coherent(struct macb * lp)3861 static void at91ether_free_coherent(struct macb *lp)
3862 {
3863 struct macb_queue *q = &lp->queues[0];
3864
3865 if (q->rx_ring) {
3866 dma_free_coherent(&lp->pdev->dev,
3867 AT91ETHER_MAX_RX_DESCR *
3868 macb_dma_desc_get_size(lp),
3869 q->rx_ring, q->rx_ring_dma);
3870 q->rx_ring = NULL;
3871 }
3872
3873 if (q->rx_buffers) {
3874 dma_free_coherent(&lp->pdev->dev,
3875 AT91ETHER_MAX_RX_DESCR *
3876 AT91ETHER_MAX_RBUFF_SZ,
3877 q->rx_buffers, q->rx_buffers_dma);
3878 q->rx_buffers = NULL;
3879 }
3880 }
3881
3882 /* Initialize and start the Receiver and Transmit subsystems */
at91ether_start(struct macb * lp)3883 static int at91ether_start(struct macb *lp)
3884 {
3885 struct macb_queue *q = &lp->queues[0];
3886 struct macb_dma_desc *desc;
3887 dma_addr_t addr;
3888 u32 ctl;
3889 int i, ret;
3890
3891 ret = at91ether_alloc_coherent(lp);
3892 if (ret)
3893 return ret;
3894
3895 addr = q->rx_buffers_dma;
3896 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3897 desc = macb_rx_desc(q, i);
3898 macb_set_addr(lp, desc, addr);
3899 desc->ctrl = 0;
3900 addr += AT91ETHER_MAX_RBUFF_SZ;
3901 }
3902
3903 /* Set the Wrap bit on the last descriptor */
3904 desc->addr |= MACB_BIT(RX_WRAP);
3905
3906 /* Reset buffer index */
3907 q->rx_tail = 0;
3908
3909 /* Program address of descriptor list in Rx Buffer Queue register */
3910 macb_writel(lp, RBQP, q->rx_ring_dma);
3911
3912 /* Enable Receive and Transmit */
3913 ctl = macb_readl(lp, NCR);
3914 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3915
3916 /* Enable MAC interrupts */
3917 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3918 MACB_BIT(RXUBR) |
3919 MACB_BIT(ISR_TUND) |
3920 MACB_BIT(ISR_RLE) |
3921 MACB_BIT(TCOMP) |
3922 MACB_BIT(RM9200_TBRE) |
3923 MACB_BIT(ISR_ROVR) |
3924 MACB_BIT(HRESP));
3925
3926 return 0;
3927 }
3928
at91ether_stop(struct macb * lp)3929 static void at91ether_stop(struct macb *lp)
3930 {
3931 u32 ctl;
3932
3933 /* Disable MAC interrupts */
3934 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3935 MACB_BIT(RXUBR) |
3936 MACB_BIT(ISR_TUND) |
3937 MACB_BIT(ISR_RLE) |
3938 MACB_BIT(TCOMP) |
3939 MACB_BIT(RM9200_TBRE) |
3940 MACB_BIT(ISR_ROVR) |
3941 MACB_BIT(HRESP));
3942
3943 /* Disable Receiver and Transmitter */
3944 ctl = macb_readl(lp, NCR);
3945 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3946
3947 /* Free resources. */
3948 at91ether_free_coherent(lp);
3949 }
3950
3951 /* Open the ethernet interface */
at91ether_open(struct net_device * dev)3952 static int at91ether_open(struct net_device *dev)
3953 {
3954 struct macb *lp = netdev_priv(dev);
3955 u32 ctl;
3956 int ret;
3957
3958 ret = pm_runtime_get_sync(&lp->pdev->dev);
3959 if (ret < 0) {
3960 pm_runtime_put_noidle(&lp->pdev->dev);
3961 return ret;
3962 }
3963
3964 /* Clear internal statistics */
3965 ctl = macb_readl(lp, NCR);
3966 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3967
3968 macb_set_hwaddr(lp);
3969
3970 ret = at91ether_start(lp);
3971 if (ret)
3972 goto pm_exit;
3973
3974 ret = macb_phylink_connect(lp);
3975 if (ret)
3976 goto stop;
3977
3978 netif_start_queue(dev);
3979
3980 return 0;
3981
3982 stop:
3983 at91ether_stop(lp);
3984 pm_exit:
3985 pm_runtime_put_sync(&lp->pdev->dev);
3986 return ret;
3987 }
3988
3989 /* Close the interface */
at91ether_close(struct net_device * dev)3990 static int at91ether_close(struct net_device *dev)
3991 {
3992 struct macb *lp = netdev_priv(dev);
3993
3994 netif_stop_queue(dev);
3995
3996 phylink_stop(lp->phylink);
3997 phylink_disconnect_phy(lp->phylink);
3998
3999 at91ether_stop(lp);
4000
4001 return pm_runtime_put(&lp->pdev->dev);
4002 }
4003
4004 /* Transmit packet */
at91ether_start_xmit(struct sk_buff * skb,struct net_device * dev)4005 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4006 struct net_device *dev)
4007 {
4008 struct macb *lp = netdev_priv(dev);
4009 unsigned long flags;
4010
4011 if (lp->rm9200_tx_len < 2) {
4012 int desc = lp->rm9200_tx_tail;
4013
4014 /* Store packet information (to free when Tx completed) */
4015 lp->rm9200_txq[desc].skb = skb;
4016 lp->rm9200_txq[desc].size = skb->len;
4017 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4018 skb->len, DMA_TO_DEVICE);
4019 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4020 dev_kfree_skb_any(skb);
4021 dev->stats.tx_dropped++;
4022 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4023 return NETDEV_TX_OK;
4024 }
4025
4026 spin_lock_irqsave(&lp->lock, flags);
4027
4028 lp->rm9200_tx_tail = (desc + 1) & 1;
4029 lp->rm9200_tx_len++;
4030 if (lp->rm9200_tx_len > 1)
4031 netif_stop_queue(dev);
4032
4033 spin_unlock_irqrestore(&lp->lock, flags);
4034
4035 /* Set address of the data in the Transmit Address register */
4036 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4037 /* Set length of the packet in the Transmit Control register */
4038 macb_writel(lp, TCR, skb->len);
4039
4040 } else {
4041 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4042 return NETDEV_TX_BUSY;
4043 }
4044
4045 return NETDEV_TX_OK;
4046 }
4047
4048 /* Extract received frame from buffer descriptors and sent to upper layers.
4049 * (Called from interrupt context)
4050 */
at91ether_rx(struct net_device * dev)4051 static void at91ether_rx(struct net_device *dev)
4052 {
4053 struct macb *lp = netdev_priv(dev);
4054 struct macb_queue *q = &lp->queues[0];
4055 struct macb_dma_desc *desc;
4056 unsigned char *p_recv;
4057 struct sk_buff *skb;
4058 unsigned int pktlen;
4059
4060 desc = macb_rx_desc(q, q->rx_tail);
4061 while (desc->addr & MACB_BIT(RX_USED)) {
4062 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4063 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4064 skb = netdev_alloc_skb(dev, pktlen + 2);
4065 if (skb) {
4066 skb_reserve(skb, 2);
4067 skb_put_data(skb, p_recv, pktlen);
4068
4069 skb->protocol = eth_type_trans(skb, dev);
4070 dev->stats.rx_packets++;
4071 dev->stats.rx_bytes += pktlen;
4072 netif_rx(skb);
4073 } else {
4074 dev->stats.rx_dropped++;
4075 }
4076
4077 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4078 dev->stats.multicast++;
4079
4080 /* reset ownership bit */
4081 desc->addr &= ~MACB_BIT(RX_USED);
4082
4083 /* wrap after last buffer */
4084 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4085 q->rx_tail = 0;
4086 else
4087 q->rx_tail++;
4088
4089 desc = macb_rx_desc(q, q->rx_tail);
4090 }
4091 }
4092
4093 /* MAC interrupt handler */
at91ether_interrupt(int irq,void * dev_id)4094 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4095 {
4096 struct net_device *dev = dev_id;
4097 struct macb *lp = netdev_priv(dev);
4098 u32 intstatus, ctl;
4099 unsigned int desc;
4100 unsigned int qlen;
4101 u32 tsr;
4102
4103 /* MAC Interrupt Status register indicates what interrupts are pending.
4104 * It is automatically cleared once read.
4105 */
4106 intstatus = macb_readl(lp, ISR);
4107
4108 /* Receive complete */
4109 if (intstatus & MACB_BIT(RCOMP))
4110 at91ether_rx(dev);
4111
4112 /* Transmit complete */
4113 if (intstatus & (MACB_BIT(TCOMP) | MACB_BIT(RM9200_TBRE))) {
4114 /* The TCOM bit is set even if the transmission failed */
4115 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4116 dev->stats.tx_errors++;
4117
4118 spin_lock(&lp->lock);
4119
4120 tsr = macb_readl(lp, TSR);
4121
4122 /* we have three possibilities here:
4123 * - all pending packets transmitted (TGO, implies BNQ)
4124 * - only first packet transmitted (!TGO && BNQ)
4125 * - two frames pending (!TGO && !BNQ)
4126 * Note that TGO ("transmit go") is called "IDLE" on RM9200.
4127 */
4128 qlen = (tsr & MACB_BIT(TGO)) ? 0 :
4129 (tsr & MACB_BIT(RM9200_BNQ)) ? 1 : 2;
4130
4131 while (lp->rm9200_tx_len > qlen) {
4132 desc = (lp->rm9200_tx_tail - lp->rm9200_tx_len) & 1;
4133 dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
4134 lp->rm9200_txq[desc].skb = NULL;
4135 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4136 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4137 dev->stats.tx_packets++;
4138 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4139 lp->rm9200_tx_len--;
4140 }
4141
4142 if (lp->rm9200_tx_len < 2 && netif_queue_stopped(dev))
4143 netif_wake_queue(dev);
4144
4145 spin_unlock(&lp->lock);
4146 }
4147
4148 /* Work-around for EMAC Errata section 41.3.1 */
4149 if (intstatus & MACB_BIT(RXUBR)) {
4150 ctl = macb_readl(lp, NCR);
4151 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4152 wmb();
4153 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4154 }
4155
4156 if (intstatus & MACB_BIT(ISR_ROVR))
4157 netdev_err(dev, "ROVR error\n");
4158
4159 return IRQ_HANDLED;
4160 }
4161
4162 #ifdef CONFIG_NET_POLL_CONTROLLER
at91ether_poll_controller(struct net_device * dev)4163 static void at91ether_poll_controller(struct net_device *dev)
4164 {
4165 unsigned long flags;
4166
4167 local_irq_save(flags);
4168 at91ether_interrupt(dev->irq, dev);
4169 local_irq_restore(flags);
4170 }
4171 #endif
4172
4173 static const struct net_device_ops at91ether_netdev_ops = {
4174 .ndo_open = at91ether_open,
4175 .ndo_stop = at91ether_close,
4176 .ndo_start_xmit = at91ether_start_xmit,
4177 .ndo_get_stats = macb_get_stats,
4178 .ndo_set_rx_mode = macb_set_rx_mode,
4179 .ndo_set_mac_address = eth_mac_addr,
4180 .ndo_do_ioctl = macb_ioctl,
4181 .ndo_validate_addr = eth_validate_addr,
4182 #ifdef CONFIG_NET_POLL_CONTROLLER
4183 .ndo_poll_controller = at91ether_poll_controller,
4184 #endif
4185 };
4186
at91ether_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk)4187 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4188 struct clk **hclk, struct clk **tx_clk,
4189 struct clk **rx_clk, struct clk **tsu_clk)
4190 {
4191 int err;
4192
4193 *hclk = NULL;
4194 *tx_clk = NULL;
4195 *rx_clk = NULL;
4196 *tsu_clk = NULL;
4197
4198 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4199 if (IS_ERR(*pclk))
4200 return PTR_ERR(*pclk);
4201
4202 err = clk_prepare_enable(*pclk);
4203 if (err) {
4204 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4205 return err;
4206 }
4207
4208 return 0;
4209 }
4210
at91ether_init(struct platform_device * pdev)4211 static int at91ether_init(struct platform_device *pdev)
4212 {
4213 struct net_device *dev = platform_get_drvdata(pdev);
4214 struct macb *bp = netdev_priv(dev);
4215 int err;
4216
4217 bp->queues[0].bp = bp;
4218
4219 dev->netdev_ops = &at91ether_netdev_ops;
4220 dev->ethtool_ops = &macb_ethtool_ops;
4221
4222 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4223 0, dev->name, dev);
4224 if (err)
4225 return err;
4226
4227 macb_writel(bp, NCR, 0);
4228
4229 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4230
4231 return 0;
4232 }
4233
fu540_macb_tx_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)4234 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4235 unsigned long parent_rate)
4236 {
4237 return mgmt->rate;
4238 }
4239
fu540_macb_tx_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)4240 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4241 unsigned long *parent_rate)
4242 {
4243 if (WARN_ON(rate < 2500000))
4244 return 2500000;
4245 else if (rate == 2500000)
4246 return 2500000;
4247 else if (WARN_ON(rate < 13750000))
4248 return 2500000;
4249 else if (WARN_ON(rate < 25000000))
4250 return 25000000;
4251 else if (rate == 25000000)
4252 return 25000000;
4253 else if (WARN_ON(rate < 75000000))
4254 return 25000000;
4255 else if (WARN_ON(rate < 125000000))
4256 return 125000000;
4257 else if (rate == 125000000)
4258 return 125000000;
4259
4260 WARN_ON(rate > 125000000);
4261
4262 return 125000000;
4263 }
4264
fu540_macb_tx_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)4265 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4266 unsigned long parent_rate)
4267 {
4268 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4269 if (rate != 125000000)
4270 iowrite32(1, mgmt->reg);
4271 else
4272 iowrite32(0, mgmt->reg);
4273 mgmt->rate = rate;
4274
4275 return 0;
4276 }
4277
4278 static const struct clk_ops fu540_c000_ops = {
4279 .recalc_rate = fu540_macb_tx_recalc_rate,
4280 .round_rate = fu540_macb_tx_round_rate,
4281 .set_rate = fu540_macb_tx_set_rate,
4282 };
4283
fu540_c000_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk)4284 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4285 struct clk **hclk, struct clk **tx_clk,
4286 struct clk **rx_clk, struct clk **tsu_clk)
4287 {
4288 struct clk_init_data init;
4289 int err = 0;
4290
4291 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4292 if (err)
4293 return err;
4294
4295 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4296 if (!mgmt)
4297 return -ENOMEM;
4298
4299 init.name = "sifive-gemgxl-mgmt";
4300 init.ops = &fu540_c000_ops;
4301 init.flags = 0;
4302 init.num_parents = 0;
4303
4304 mgmt->rate = 0;
4305 mgmt->hw.init = &init;
4306
4307 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4308 if (IS_ERR(*tx_clk))
4309 return PTR_ERR(*tx_clk);
4310
4311 err = clk_prepare_enable(*tx_clk);
4312 if (err)
4313 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4314 else
4315 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4316
4317 return 0;
4318 }
4319
fu540_c000_init(struct platform_device * pdev)4320 static int fu540_c000_init(struct platform_device *pdev)
4321 {
4322 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4323 if (IS_ERR(mgmt->reg))
4324 return PTR_ERR(mgmt->reg);
4325
4326 return macb_init(pdev);
4327 }
4328
4329 static const struct macb_config fu540_c000_config = {
4330 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4331 MACB_CAPS_GEM_HAS_PTP,
4332 .dma_burst_length = 16,
4333 .clk_init = fu540_c000_clk_init,
4334 .init = fu540_c000_init,
4335 .jumbo_max_len = 10240,
4336 };
4337
4338 static const struct macb_config at91sam9260_config = {
4339 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4340 .clk_init = macb_clk_init,
4341 .init = macb_init,
4342 };
4343
4344 static const struct macb_config sama5d3macb_config = {
4345 .caps = MACB_CAPS_SG_DISABLED
4346 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4347 .clk_init = macb_clk_init,
4348 .init = macb_init,
4349 };
4350
4351 static const struct macb_config pc302gem_config = {
4352 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4353 .dma_burst_length = 16,
4354 .clk_init = macb_clk_init,
4355 .init = macb_init,
4356 };
4357
4358 static const struct macb_config sama5d2_config = {
4359 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4360 .dma_burst_length = 16,
4361 .clk_init = macb_clk_init,
4362 .init = macb_init,
4363 };
4364
4365 static const struct macb_config sama5d3_config = {
4366 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
4367 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4368 .dma_burst_length = 16,
4369 .clk_init = macb_clk_init,
4370 .init = macb_init,
4371 .jumbo_max_len = 10240,
4372 };
4373
4374 static const struct macb_config sama5d4_config = {
4375 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4376 .dma_burst_length = 4,
4377 .clk_init = macb_clk_init,
4378 .init = macb_init,
4379 };
4380
4381 static const struct macb_config emac_config = {
4382 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4383 .clk_init = at91ether_clk_init,
4384 .init = at91ether_init,
4385 };
4386
4387 static const struct macb_config np4_config = {
4388 .caps = MACB_CAPS_USRIO_DISABLED,
4389 .clk_init = macb_clk_init,
4390 .init = macb_init,
4391 };
4392
4393 static const struct macb_config zynqmp_config = {
4394 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4395 MACB_CAPS_JUMBO |
4396 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4397 .dma_burst_length = 16,
4398 .clk_init = macb_clk_init,
4399 .init = macb_init,
4400 .jumbo_max_len = 10240,
4401 };
4402
4403 static const struct macb_config zynq_config = {
4404 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4405 MACB_CAPS_NEEDS_RSTONUBR,
4406 .dma_burst_length = 16,
4407 .clk_init = macb_clk_init,
4408 .init = macb_init,
4409 };
4410
4411 static const struct of_device_id macb_dt_ids[] = {
4412 { .compatible = "cdns,at32ap7000-macb" },
4413 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4414 { .compatible = "cdns,macb" },
4415 { .compatible = "cdns,np4-macb", .data = &np4_config },
4416 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4417 { .compatible = "cdns,gem", .data = &pc302gem_config },
4418 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4419 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4420 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4421 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4422 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4423 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4424 { .compatible = "cdns,emac", .data = &emac_config },
4425 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4426 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4427 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4428 { /* sentinel */ }
4429 };
4430 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4431 #endif /* CONFIG_OF */
4432
4433 static const struct macb_config default_gem_config = {
4434 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4435 MACB_CAPS_JUMBO |
4436 MACB_CAPS_GEM_HAS_PTP,
4437 .dma_burst_length = 16,
4438 .clk_init = macb_clk_init,
4439 .init = macb_init,
4440 .jumbo_max_len = 10240,
4441 };
4442
macb_probe(struct platform_device * pdev)4443 static int macb_probe(struct platform_device *pdev)
4444 {
4445 const struct macb_config *macb_config = &default_gem_config;
4446 int (*clk_init)(struct platform_device *, struct clk **,
4447 struct clk **, struct clk **, struct clk **,
4448 struct clk **) = macb_config->clk_init;
4449 int (*init)(struct platform_device *) = macb_config->init;
4450 struct device_node *np = pdev->dev.of_node;
4451 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4452 struct clk *tsu_clk = NULL;
4453 unsigned int queue_mask, num_queues;
4454 bool native_io;
4455 phy_interface_t interface;
4456 struct net_device *dev;
4457 struct resource *regs;
4458 void __iomem *mem;
4459 const char *mac;
4460 struct macb *bp;
4461 int err, val;
4462
4463 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4464 mem = devm_ioremap_resource(&pdev->dev, regs);
4465 if (IS_ERR(mem))
4466 return PTR_ERR(mem);
4467
4468 if (np) {
4469 const struct of_device_id *match;
4470
4471 match = of_match_node(macb_dt_ids, np);
4472 if (match && match->data) {
4473 macb_config = match->data;
4474 clk_init = macb_config->clk_init;
4475 init = macb_config->init;
4476 }
4477 }
4478
4479 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4480 if (err)
4481 return err;
4482
4483 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4484 pm_runtime_use_autosuspend(&pdev->dev);
4485 pm_runtime_get_noresume(&pdev->dev);
4486 pm_runtime_set_active(&pdev->dev);
4487 pm_runtime_enable(&pdev->dev);
4488 native_io = hw_is_native_io(mem);
4489
4490 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4491 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4492 if (!dev) {
4493 err = -ENOMEM;
4494 goto err_disable_clocks;
4495 }
4496
4497 dev->base_addr = regs->start;
4498
4499 SET_NETDEV_DEV(dev, &pdev->dev);
4500
4501 bp = netdev_priv(dev);
4502 bp->pdev = pdev;
4503 bp->dev = dev;
4504 bp->regs = mem;
4505 bp->native_io = native_io;
4506 if (native_io) {
4507 bp->macb_reg_readl = hw_readl_native;
4508 bp->macb_reg_writel = hw_writel_native;
4509 } else {
4510 bp->macb_reg_readl = hw_readl;
4511 bp->macb_reg_writel = hw_writel;
4512 }
4513 bp->num_queues = num_queues;
4514 bp->queue_mask = queue_mask;
4515 if (macb_config)
4516 bp->dma_burst_length = macb_config->dma_burst_length;
4517 bp->pclk = pclk;
4518 bp->hclk = hclk;
4519 bp->tx_clk = tx_clk;
4520 bp->rx_clk = rx_clk;
4521 bp->tsu_clk = tsu_clk;
4522 if (macb_config)
4523 bp->jumbo_max_len = macb_config->jumbo_max_len;
4524
4525 bp->wol = 0;
4526 if (of_get_property(np, "magic-packet", NULL))
4527 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4528 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4529
4530 spin_lock_init(&bp->lock);
4531
4532 /* setup capabilities */
4533 macb_configure_caps(bp, macb_config);
4534
4535 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4536 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4537 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4538 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4539 }
4540 #endif
4541 platform_set_drvdata(pdev, dev);
4542
4543 dev->irq = platform_get_irq(pdev, 0);
4544 if (dev->irq < 0) {
4545 err = dev->irq;
4546 goto err_out_free_netdev;
4547 }
4548
4549 /* MTU range: 68 - 1500 or 10240 */
4550 dev->min_mtu = GEM_MTU_MIN_SIZE;
4551 if (bp->caps & MACB_CAPS_JUMBO)
4552 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4553 else
4554 dev->max_mtu = ETH_DATA_LEN;
4555
4556 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4557 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4558 if (val)
4559 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4560 macb_dma_desc_get_size(bp);
4561
4562 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4563 if (val)
4564 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4565 macb_dma_desc_get_size(bp);
4566 }
4567
4568 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4569 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4570 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4571
4572 mac = of_get_mac_address(np);
4573 if (PTR_ERR(mac) == -EPROBE_DEFER) {
4574 err = -EPROBE_DEFER;
4575 goto err_out_free_netdev;
4576 } else if (!IS_ERR_OR_NULL(mac)) {
4577 ether_addr_copy(bp->dev->dev_addr, mac);
4578 } else {
4579 macb_get_hwaddr(bp);
4580 }
4581
4582 err = of_get_phy_mode(np, &interface);
4583 if (err)
4584 /* not found in DT, MII by default */
4585 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4586 else
4587 bp->phy_interface = interface;
4588
4589 /* IP specific init */
4590 err = init(pdev);
4591 if (err)
4592 goto err_out_free_netdev;
4593
4594 err = macb_mii_init(bp);
4595 if (err)
4596 goto err_out_free_netdev;
4597
4598 netif_carrier_off(dev);
4599
4600 err = register_netdev(dev);
4601 if (err) {
4602 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4603 goto err_out_unregister_mdio;
4604 }
4605
4606 tasklet_setup(&bp->hresp_err_tasklet, macb_hresp_error_task);
4607
4608 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4609 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4610 dev->base_addr, dev->irq, dev->dev_addr);
4611
4612 pm_runtime_mark_last_busy(&bp->pdev->dev);
4613 pm_runtime_put_autosuspend(&bp->pdev->dev);
4614
4615 return 0;
4616
4617 err_out_unregister_mdio:
4618 mdiobus_unregister(bp->mii_bus);
4619 mdiobus_free(bp->mii_bus);
4620
4621 err_out_free_netdev:
4622 free_netdev(dev);
4623
4624 err_disable_clocks:
4625 clk_disable_unprepare(tx_clk);
4626 clk_disable_unprepare(hclk);
4627 clk_disable_unprepare(pclk);
4628 clk_disable_unprepare(rx_clk);
4629 clk_disable_unprepare(tsu_clk);
4630 pm_runtime_disable(&pdev->dev);
4631 pm_runtime_set_suspended(&pdev->dev);
4632 pm_runtime_dont_use_autosuspend(&pdev->dev);
4633
4634 return err;
4635 }
4636
macb_remove(struct platform_device * pdev)4637 static int macb_remove(struct platform_device *pdev)
4638 {
4639 struct net_device *dev;
4640 struct macb *bp;
4641
4642 dev = platform_get_drvdata(pdev);
4643
4644 if (dev) {
4645 bp = netdev_priv(dev);
4646 mdiobus_unregister(bp->mii_bus);
4647 mdiobus_free(bp->mii_bus);
4648
4649 unregister_netdev(dev);
4650 tasklet_kill(&bp->hresp_err_tasklet);
4651 pm_runtime_disable(&pdev->dev);
4652 pm_runtime_dont_use_autosuspend(&pdev->dev);
4653 if (!pm_runtime_suspended(&pdev->dev)) {
4654 clk_disable_unprepare(bp->tx_clk);
4655 clk_disable_unprepare(bp->hclk);
4656 clk_disable_unprepare(bp->pclk);
4657 clk_disable_unprepare(bp->rx_clk);
4658 clk_disable_unprepare(bp->tsu_clk);
4659 pm_runtime_set_suspended(&pdev->dev);
4660 }
4661 phylink_destroy(bp->phylink);
4662 free_netdev(dev);
4663 }
4664
4665 return 0;
4666 }
4667
macb_suspend(struct device * dev)4668 static int __maybe_unused macb_suspend(struct device *dev)
4669 {
4670 struct net_device *netdev = dev_get_drvdata(dev);
4671 struct macb *bp = netdev_priv(netdev);
4672 struct macb_queue *queue = bp->queues;
4673 unsigned long flags;
4674 unsigned int q;
4675 int err;
4676
4677 if (!netif_running(netdev))
4678 return 0;
4679
4680 if (bp->wol & MACB_WOL_ENABLED) {
4681 spin_lock_irqsave(&bp->lock, flags);
4682 /* Flush all status bits */
4683 macb_writel(bp, TSR, -1);
4684 macb_writel(bp, RSR, -1);
4685 for (q = 0, queue = bp->queues; q < bp->num_queues;
4686 ++q, ++queue) {
4687 /* Disable all interrupts */
4688 queue_writel(queue, IDR, -1);
4689 queue_readl(queue, ISR);
4690 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4691 queue_writel(queue, ISR, -1);
4692 }
4693 /* Change interrupt handler and
4694 * Enable WoL IRQ on queue 0
4695 */
4696 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4697 if (macb_is_gem(bp)) {
4698 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
4699 IRQF_SHARED, netdev->name, bp->queues);
4700 if (err) {
4701 dev_err(dev,
4702 "Unable to request IRQ %d (error %d)\n",
4703 bp->queues[0].irq, err);
4704 spin_unlock_irqrestore(&bp->lock, flags);
4705 return err;
4706 }
4707 queue_writel(bp->queues, IER, GEM_BIT(WOL));
4708 gem_writel(bp, WOL, MACB_BIT(MAG));
4709 } else {
4710 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
4711 IRQF_SHARED, netdev->name, bp->queues);
4712 if (err) {
4713 dev_err(dev,
4714 "Unable to request IRQ %d (error %d)\n",
4715 bp->queues[0].irq, err);
4716 spin_unlock_irqrestore(&bp->lock, flags);
4717 return err;
4718 }
4719 queue_writel(bp->queues, IER, MACB_BIT(WOL));
4720 macb_writel(bp, WOL, MACB_BIT(MAG));
4721 }
4722 spin_unlock_irqrestore(&bp->lock, flags);
4723
4724 enable_irq_wake(bp->queues[0].irq);
4725 }
4726
4727 netif_device_detach(netdev);
4728 for (q = 0, queue = bp->queues; q < bp->num_queues;
4729 ++q, ++queue)
4730 napi_disable(&queue->napi);
4731
4732 if (!(bp->wol & MACB_WOL_ENABLED)) {
4733 rtnl_lock();
4734 phylink_stop(bp->phylink);
4735 rtnl_unlock();
4736 spin_lock_irqsave(&bp->lock, flags);
4737 macb_reset_hw(bp);
4738 spin_unlock_irqrestore(&bp->lock, flags);
4739 }
4740
4741 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4742 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
4743
4744 if (netdev->hw_features & NETIF_F_NTUPLE)
4745 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
4746
4747 if (bp->ptp_info)
4748 bp->ptp_info->ptp_remove(netdev);
4749 if (!device_may_wakeup(dev))
4750 pm_runtime_force_suspend(dev);
4751
4752 return 0;
4753 }
4754
macb_resume(struct device * dev)4755 static int __maybe_unused macb_resume(struct device *dev)
4756 {
4757 struct net_device *netdev = dev_get_drvdata(dev);
4758 struct macb *bp = netdev_priv(netdev);
4759 struct macb_queue *queue = bp->queues;
4760 unsigned long flags;
4761 unsigned int q;
4762 int err;
4763
4764 if (!netif_running(netdev))
4765 return 0;
4766
4767 if (!device_may_wakeup(dev))
4768 pm_runtime_force_resume(dev);
4769
4770 if (bp->wol & MACB_WOL_ENABLED) {
4771 spin_lock_irqsave(&bp->lock, flags);
4772 /* Disable WoL */
4773 if (macb_is_gem(bp)) {
4774 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
4775 gem_writel(bp, WOL, 0);
4776 } else {
4777 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
4778 macb_writel(bp, WOL, 0);
4779 }
4780 /* Clear ISR on queue 0 */
4781 queue_readl(bp->queues, ISR);
4782 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4783 queue_writel(bp->queues, ISR, -1);
4784 /* Replace interrupt handler on queue 0 */
4785 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4786 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
4787 IRQF_SHARED, netdev->name, bp->queues);
4788 if (err) {
4789 dev_err(dev,
4790 "Unable to request IRQ %d (error %d)\n",
4791 bp->queues[0].irq, err);
4792 spin_unlock_irqrestore(&bp->lock, flags);
4793 return err;
4794 }
4795 spin_unlock_irqrestore(&bp->lock, flags);
4796
4797 disable_irq_wake(bp->queues[0].irq);
4798
4799 /* Now make sure we disable phy before moving
4800 * to common restore path
4801 */
4802 rtnl_lock();
4803 phylink_stop(bp->phylink);
4804 rtnl_unlock();
4805 }
4806
4807 for (q = 0, queue = bp->queues; q < bp->num_queues;
4808 ++q, ++queue)
4809 napi_enable(&queue->napi);
4810
4811 if (netdev->hw_features & NETIF_F_NTUPLE)
4812 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
4813
4814 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4815 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
4816
4817 macb_writel(bp, NCR, MACB_BIT(MPE));
4818 macb_init_hw(bp);
4819 macb_set_rx_mode(netdev);
4820 macb_restore_features(bp);
4821 rtnl_lock();
4822 phylink_start(bp->phylink);
4823 rtnl_unlock();
4824
4825 netif_device_attach(netdev);
4826 if (bp->ptp_info)
4827 bp->ptp_info->ptp_init(netdev);
4828
4829 return 0;
4830 }
4831
macb_runtime_suspend(struct device * dev)4832 static int __maybe_unused macb_runtime_suspend(struct device *dev)
4833 {
4834 struct net_device *netdev = dev_get_drvdata(dev);
4835 struct macb *bp = netdev_priv(netdev);
4836
4837 if (!(device_may_wakeup(dev))) {
4838 clk_disable_unprepare(bp->tx_clk);
4839 clk_disable_unprepare(bp->hclk);
4840 clk_disable_unprepare(bp->pclk);
4841 clk_disable_unprepare(bp->rx_clk);
4842 }
4843 clk_disable_unprepare(bp->tsu_clk);
4844
4845 return 0;
4846 }
4847
macb_runtime_resume(struct device * dev)4848 static int __maybe_unused macb_runtime_resume(struct device *dev)
4849 {
4850 struct net_device *netdev = dev_get_drvdata(dev);
4851 struct macb *bp = netdev_priv(netdev);
4852
4853 if (!(device_may_wakeup(dev))) {
4854 clk_prepare_enable(bp->pclk);
4855 clk_prepare_enable(bp->hclk);
4856 clk_prepare_enable(bp->tx_clk);
4857 clk_prepare_enable(bp->rx_clk);
4858 }
4859 clk_prepare_enable(bp->tsu_clk);
4860
4861 return 0;
4862 }
4863
4864 static const struct dev_pm_ops macb_pm_ops = {
4865 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
4866 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
4867 };
4868
4869 static struct platform_driver macb_driver = {
4870 .probe = macb_probe,
4871 .remove = macb_remove,
4872 .driver = {
4873 .name = "macb",
4874 .of_match_table = of_match_ptr(macb_dt_ids),
4875 .pm = &macb_pm_ops,
4876 },
4877 };
4878
4879 module_platform_driver(macb_driver);
4880
4881 MODULE_LICENSE("GPL");
4882 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4883 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4884 MODULE_ALIAS("platform:macb");
4885