1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH-X3 prototype CPU pinmux 4 * 5 * Copyright (C) 2010 Paul Mundt 6 */ 7 #include <linux/init.h> 8 #include <linux/kernel.h> 9 #include <cpu/shx3.h> 10 11 #include "sh_pfc.h" 12 13 enum { 14 PINMUX_RESERVED = 0, 15 16 PINMUX_DATA_BEGIN, 17 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 18 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, 19 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, 20 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, 21 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, 22 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, 23 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, 24 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, 25 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, 26 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, 27 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, 28 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, 29 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, 30 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA, 31 32 PH5_DATA, PH4_DATA, 33 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, 34 PINMUX_DATA_END, 35 36 PINMUX_INPUT_BEGIN, 37 PA7_IN, PA6_IN, PA5_IN, PA4_IN, 38 PA3_IN, PA2_IN, PA1_IN, PA0_IN, 39 PB7_IN, PB6_IN, PB5_IN, PB4_IN, 40 PB3_IN, PB2_IN, PB1_IN, PB0_IN, 41 PC7_IN, PC6_IN, PC5_IN, PC4_IN, 42 PC3_IN, PC2_IN, PC1_IN, PC0_IN, 43 PD7_IN, PD6_IN, PD5_IN, PD4_IN, 44 PD3_IN, PD2_IN, PD1_IN, PD0_IN, 45 PE7_IN, PE6_IN, PE5_IN, PE4_IN, 46 PE3_IN, PE2_IN, PE1_IN, PE0_IN, 47 PF7_IN, PF6_IN, PF5_IN, PF4_IN, 48 PF3_IN, PF2_IN, PF1_IN, PF0_IN, 49 PG7_IN, PG6_IN, PG5_IN, PG4_IN, 50 PG3_IN, PG2_IN, PG1_IN, PG0_IN, 51 52 PH5_IN, PH4_IN, 53 PH3_IN, PH2_IN, PH1_IN, PH0_IN, 54 PINMUX_INPUT_END, 55 56 PINMUX_OUTPUT_BEGIN, 57 PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, 58 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, 59 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT, 60 PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT, 61 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT, 62 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT, 63 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT, 64 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT, 65 PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT, 66 PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT, 67 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT, 68 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT, 69 PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT, 70 PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT, 71 72 PH5_OUT, PH4_OUT, 73 PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT, 74 PINMUX_OUTPUT_END, 75 76 PINMUX_FUNCTION_BEGIN, 77 PA7_FN, PA6_FN, PA5_FN, PA4_FN, 78 PA3_FN, PA2_FN, PA1_FN, PA0_FN, 79 PB7_FN, PB6_FN, PB5_FN, PB4_FN, 80 PB3_FN, PB2_FN, PB1_FN, PB0_FN, 81 PC7_FN, PC6_FN, PC5_FN, PC4_FN, 82 PC3_FN, PC2_FN, PC1_FN, PC0_FN, 83 PD7_FN, PD6_FN, PD5_FN, PD4_FN, 84 PD3_FN, PD2_FN, PD1_FN, PD0_FN, 85 PE7_FN, PE6_FN, PE5_FN, PE4_FN, 86 PE3_FN, PE2_FN, PE1_FN, PE0_FN, 87 PF7_FN, PF6_FN, PF5_FN, PF4_FN, 88 PF3_FN, PF2_FN, PF1_FN, PF0_FN, 89 PG7_FN, PG6_FN, PG5_FN, PG4_FN, 90 PG3_FN, PG2_FN, PG1_FN, PG0_FN, 91 92 PH5_FN, PH4_FN, 93 PH3_FN, PH2_FN, PH1_FN, PH0_FN, 94 PINMUX_FUNCTION_END, 95 96 PINMUX_MARK_BEGIN, 97 98 D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK, 99 D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK, 100 D19_MARK, D18_MARK, D17_MARK, D16_MARK, 101 102 BACK_MARK, BREQ_MARK, 103 WE3_MARK, WE2_MARK, 104 CS6_MARK, CS5_MARK, CS4_MARK, 105 CLKOUTENB_MARK, 106 107 DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK, 108 DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK, 109 110 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK, 111 112 DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK, 113 114 SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK, 115 IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK, 116 TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK, 117 RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK, 118 119 CE2B_MARK, CE2A_MARK, IOIS16_MARK, 120 STATUS1_MARK, STATUS0_MARK, 121 122 IRQOUT_MARK, 123 124 PINMUX_MARK_END, 125 }; 126 127 static const u16 pinmux_data[] = { 128 /* PA GPIO */ 129 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), 130 PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), 131 PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT), 132 PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT), 133 PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT), 134 PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT), 135 PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT), 136 PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT), 137 138 /* PB GPIO */ 139 PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT), 140 PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT), 141 PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT), 142 PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT), 143 PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT), 144 PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT), 145 PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT), 146 PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT), 147 148 /* PC GPIO */ 149 PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT), 150 PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT), 151 PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT), 152 PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT), 153 PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT), 154 PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT), 155 PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT), 156 PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT), 157 158 /* PD GPIO */ 159 PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT), 160 PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT), 161 PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT), 162 PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT), 163 PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT), 164 PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT), 165 PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT), 166 PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT), 167 168 /* PE GPIO */ 169 PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT), 170 PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT), 171 PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT), 172 PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT), 173 PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT), 174 PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT), 175 PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT), 176 PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT), 177 178 /* PF GPIO */ 179 PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT), 180 PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT), 181 PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT), 182 PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT), 183 PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT), 184 PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT), 185 PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT), 186 PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT), 187 188 /* PG GPIO */ 189 PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT), 190 PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT), 191 PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT), 192 PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT), 193 PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT), 194 PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT), 195 PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT), 196 PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT), 197 198 /* PH GPIO */ 199 PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT), 200 PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT), 201 PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT), 202 PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT), 203 PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT), 204 PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT), 205 206 /* PA FN */ 207 PINMUX_DATA(D31_MARK, PA7_FN), 208 PINMUX_DATA(D30_MARK, PA6_FN), 209 PINMUX_DATA(D29_MARK, PA5_FN), 210 PINMUX_DATA(D28_MARK, PA4_FN), 211 PINMUX_DATA(D27_MARK, PA3_FN), 212 PINMUX_DATA(D26_MARK, PA2_FN), 213 PINMUX_DATA(D25_MARK, PA1_FN), 214 PINMUX_DATA(D24_MARK, PA0_FN), 215 216 /* PB FN */ 217 PINMUX_DATA(D23_MARK, PB7_FN), 218 PINMUX_DATA(D22_MARK, PB6_FN), 219 PINMUX_DATA(D21_MARK, PB5_FN), 220 PINMUX_DATA(D20_MARK, PB4_FN), 221 PINMUX_DATA(D19_MARK, PB3_FN), 222 PINMUX_DATA(D18_MARK, PB2_FN), 223 PINMUX_DATA(D17_MARK, PB1_FN), 224 PINMUX_DATA(D16_MARK, PB0_FN), 225 226 /* PC FN */ 227 PINMUX_DATA(BACK_MARK, PC7_FN), 228 PINMUX_DATA(BREQ_MARK, PC6_FN), 229 PINMUX_DATA(WE3_MARK, PC5_FN), 230 PINMUX_DATA(WE2_MARK, PC4_FN), 231 PINMUX_DATA(CS6_MARK, PC3_FN), 232 PINMUX_DATA(CS5_MARK, PC2_FN), 233 PINMUX_DATA(CS4_MARK, PC1_FN), 234 PINMUX_DATA(CLKOUTENB_MARK, PC0_FN), 235 236 /* PD FN */ 237 PINMUX_DATA(DACK3_MARK, PD7_FN), 238 PINMUX_DATA(DACK2_MARK, PD6_FN), 239 PINMUX_DATA(DACK1_MARK, PD5_FN), 240 PINMUX_DATA(DACK0_MARK, PD4_FN), 241 PINMUX_DATA(DREQ3_MARK, PD3_FN), 242 PINMUX_DATA(DREQ2_MARK, PD2_FN), 243 PINMUX_DATA(DREQ1_MARK, PD1_FN), 244 PINMUX_DATA(DREQ0_MARK, PD0_FN), 245 246 /* PE FN */ 247 PINMUX_DATA(IRQ3_MARK, PE7_FN), 248 PINMUX_DATA(IRQ2_MARK, PE6_FN), 249 PINMUX_DATA(IRQ1_MARK, PE5_FN), 250 PINMUX_DATA(IRQ0_MARK, PE4_FN), 251 PINMUX_DATA(DRAK3_MARK, PE3_FN), 252 PINMUX_DATA(DRAK2_MARK, PE2_FN), 253 PINMUX_DATA(DRAK1_MARK, PE1_FN), 254 PINMUX_DATA(DRAK0_MARK, PE0_FN), 255 256 /* PF FN */ 257 PINMUX_DATA(SCK3_MARK, PF7_FN), 258 PINMUX_DATA(SCK2_MARK, PF6_FN), 259 PINMUX_DATA(SCK1_MARK, PF5_FN), 260 PINMUX_DATA(SCK0_MARK, PF4_FN), 261 PINMUX_DATA(IRL3_MARK, PF3_FN), 262 PINMUX_DATA(IRL2_MARK, PF2_FN), 263 PINMUX_DATA(IRL1_MARK, PF1_FN), 264 PINMUX_DATA(IRL0_MARK, PF0_FN), 265 266 /* PG FN */ 267 PINMUX_DATA(TXD3_MARK, PG7_FN), 268 PINMUX_DATA(TXD2_MARK, PG6_FN), 269 PINMUX_DATA(TXD1_MARK, PG5_FN), 270 PINMUX_DATA(TXD0_MARK, PG4_FN), 271 PINMUX_DATA(RXD3_MARK, PG3_FN), 272 PINMUX_DATA(RXD2_MARK, PG2_FN), 273 PINMUX_DATA(RXD1_MARK, PG1_FN), 274 PINMUX_DATA(RXD0_MARK, PG0_FN), 275 276 /* PH FN */ 277 PINMUX_DATA(CE2B_MARK, PH5_FN), 278 PINMUX_DATA(CE2A_MARK, PH4_FN), 279 PINMUX_DATA(IOIS16_MARK, PH3_FN), 280 PINMUX_DATA(STATUS1_MARK, PH2_FN), 281 PINMUX_DATA(STATUS0_MARK, PH1_FN), 282 PINMUX_DATA(IRQOUT_MARK, PH0_FN), 283 }; 284 285 static const struct sh_pfc_pin pinmux_pins[] = { 286 /* PA */ 287 PINMUX_GPIO(PA7), 288 PINMUX_GPIO(PA6), 289 PINMUX_GPIO(PA5), 290 PINMUX_GPIO(PA4), 291 PINMUX_GPIO(PA3), 292 PINMUX_GPIO(PA2), 293 PINMUX_GPIO(PA1), 294 PINMUX_GPIO(PA0), 295 296 /* PB */ 297 PINMUX_GPIO(PB7), 298 PINMUX_GPIO(PB6), 299 PINMUX_GPIO(PB5), 300 PINMUX_GPIO(PB4), 301 PINMUX_GPIO(PB3), 302 PINMUX_GPIO(PB2), 303 PINMUX_GPIO(PB1), 304 PINMUX_GPIO(PB0), 305 306 /* PC */ 307 PINMUX_GPIO(PC7), 308 PINMUX_GPIO(PC6), 309 PINMUX_GPIO(PC5), 310 PINMUX_GPIO(PC4), 311 PINMUX_GPIO(PC3), 312 PINMUX_GPIO(PC2), 313 PINMUX_GPIO(PC1), 314 PINMUX_GPIO(PC0), 315 316 /* PD */ 317 PINMUX_GPIO(PD7), 318 PINMUX_GPIO(PD6), 319 PINMUX_GPIO(PD5), 320 PINMUX_GPIO(PD4), 321 PINMUX_GPIO(PD3), 322 PINMUX_GPIO(PD2), 323 PINMUX_GPIO(PD1), 324 PINMUX_GPIO(PD0), 325 326 /* PE */ 327 PINMUX_GPIO(PE7), 328 PINMUX_GPIO(PE6), 329 PINMUX_GPIO(PE5), 330 PINMUX_GPIO(PE4), 331 PINMUX_GPIO(PE3), 332 PINMUX_GPIO(PE2), 333 PINMUX_GPIO(PE1), 334 PINMUX_GPIO(PE0), 335 336 /* PF */ 337 PINMUX_GPIO(PF7), 338 PINMUX_GPIO(PF6), 339 PINMUX_GPIO(PF5), 340 PINMUX_GPIO(PF4), 341 PINMUX_GPIO(PF3), 342 PINMUX_GPIO(PF2), 343 PINMUX_GPIO(PF1), 344 PINMUX_GPIO(PF0), 345 346 /* PG */ 347 PINMUX_GPIO(PG7), 348 PINMUX_GPIO(PG6), 349 PINMUX_GPIO(PG5), 350 PINMUX_GPIO(PG4), 351 PINMUX_GPIO(PG3), 352 PINMUX_GPIO(PG2), 353 PINMUX_GPIO(PG1), 354 PINMUX_GPIO(PG0), 355 356 /* PH */ 357 PINMUX_GPIO(PH5), 358 PINMUX_GPIO(PH4), 359 PINMUX_GPIO(PH3), 360 PINMUX_GPIO(PH2), 361 PINMUX_GPIO(PH1), 362 PINMUX_GPIO(PH0), 363 }; 364 365 #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) 366 367 static const struct pinmux_func pinmux_func_gpios[] = { 368 /* FN */ 369 GPIO_FN(D31), 370 GPIO_FN(D30), 371 GPIO_FN(D29), 372 GPIO_FN(D28), 373 GPIO_FN(D27), 374 GPIO_FN(D26), 375 GPIO_FN(D25), 376 GPIO_FN(D24), 377 GPIO_FN(D23), 378 GPIO_FN(D22), 379 GPIO_FN(D21), 380 GPIO_FN(D20), 381 GPIO_FN(D19), 382 GPIO_FN(D18), 383 GPIO_FN(D17), 384 GPIO_FN(D16), 385 GPIO_FN(BACK), 386 GPIO_FN(BREQ), 387 GPIO_FN(WE3), 388 GPIO_FN(WE2), 389 GPIO_FN(CS6), 390 GPIO_FN(CS5), 391 GPIO_FN(CS4), 392 GPIO_FN(CLKOUTENB), 393 GPIO_FN(DACK3), 394 GPIO_FN(DACK2), 395 GPIO_FN(DACK1), 396 GPIO_FN(DACK0), 397 GPIO_FN(DREQ3), 398 GPIO_FN(DREQ2), 399 GPIO_FN(DREQ1), 400 GPIO_FN(DREQ0), 401 GPIO_FN(IRQ3), 402 GPIO_FN(IRQ2), 403 GPIO_FN(IRQ1), 404 GPIO_FN(IRQ0), 405 GPIO_FN(DRAK3), 406 GPIO_FN(DRAK2), 407 GPIO_FN(DRAK1), 408 GPIO_FN(DRAK0), 409 GPIO_FN(SCK3), 410 GPIO_FN(SCK2), 411 GPIO_FN(SCK1), 412 GPIO_FN(SCK0), 413 GPIO_FN(IRL3), 414 GPIO_FN(IRL2), 415 GPIO_FN(IRL1), 416 GPIO_FN(IRL0), 417 GPIO_FN(TXD3), 418 GPIO_FN(TXD2), 419 GPIO_FN(TXD1), 420 GPIO_FN(TXD0), 421 GPIO_FN(RXD3), 422 GPIO_FN(RXD2), 423 GPIO_FN(RXD1), 424 GPIO_FN(RXD0), 425 GPIO_FN(CE2B), 426 GPIO_FN(CE2A), 427 GPIO_FN(IOIS16), 428 GPIO_FN(STATUS1), 429 GPIO_FN(STATUS0), 430 GPIO_FN(IRQOUT), 431 }; 432 433 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 434 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2, GROUP( 435 PA7_FN, PA7_OUT, PA7_IN, 0, 436 PA6_FN, PA6_OUT, PA6_IN, 0, 437 PA5_FN, PA5_OUT, PA5_IN, 0, 438 PA4_FN, PA4_OUT, PA4_IN, 0, 439 PA3_FN, PA3_OUT, PA3_IN, 0, 440 PA2_FN, PA2_OUT, PA2_IN, 0, 441 PA1_FN, PA1_OUT, PA1_IN, 0, 442 PA0_FN, PA0_OUT, PA0_IN, 0, 443 PB7_FN, PB7_OUT, PB7_IN, 0, 444 PB6_FN, PB6_OUT, PB6_IN, 0, 445 PB5_FN, PB5_OUT, PB5_IN, 0, 446 PB4_FN, PB4_OUT, PB4_IN, 0, 447 PB3_FN, PB3_OUT, PB3_IN, 0, 448 PB2_FN, PB2_OUT, PB2_IN, 0, 449 PB1_FN, PB1_OUT, PB1_IN, 0, 450 PB0_FN, PB0_OUT, PB0_IN, 0, )) 451 }, 452 { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2, GROUP( 453 PC7_FN, PC7_OUT, PC7_IN, 0, 454 PC6_FN, PC6_OUT, PC6_IN, 0, 455 PC5_FN, PC5_OUT, PC5_IN, 0, 456 PC4_FN, PC4_OUT, PC4_IN, 0, 457 PC3_FN, PC3_OUT, PC3_IN, 0, 458 PC2_FN, PC2_OUT, PC2_IN, 0, 459 PC1_FN, PC1_OUT, PC1_IN, 0, 460 PC0_FN, PC0_OUT, PC0_IN, 0, 461 PD7_FN, PD7_OUT, PD7_IN, 0, 462 PD6_FN, PD6_OUT, PD6_IN, 0, 463 PD5_FN, PD5_OUT, PD5_IN, 0, 464 PD4_FN, PD4_OUT, PD4_IN, 0, 465 PD3_FN, PD3_OUT, PD3_IN, 0, 466 PD2_FN, PD2_OUT, PD2_IN, 0, 467 PD1_FN, PD1_OUT, PD1_IN, 0, 468 PD0_FN, PD0_OUT, PD0_IN, 0, )) 469 }, 470 { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2, GROUP( 471 PE7_FN, PE7_OUT, PE7_IN, 0, 472 PE6_FN, PE6_OUT, PE6_IN, 0, 473 PE5_FN, PE5_OUT, PE5_IN, 0, 474 PE4_FN, PE4_OUT, PE4_IN, 0, 475 PE3_FN, PE3_OUT, PE3_IN, 0, 476 PE2_FN, PE2_OUT, PE2_IN, 0, 477 PE1_FN, PE1_OUT, PE1_IN, 0, 478 PE0_FN, PE0_OUT, PE0_IN, 0, 479 PF7_FN, PF7_OUT, PF7_IN, 0, 480 PF6_FN, PF6_OUT, PF6_IN, 0, 481 PF5_FN, PF5_OUT, PF5_IN, 0, 482 PF4_FN, PF4_OUT, PF4_IN, 0, 483 PF3_FN, PF3_OUT, PF3_IN, 0, 484 PF2_FN, PF2_OUT, PF2_IN, 0, 485 PF1_FN, PF1_OUT, PF1_IN, 0, 486 PF0_FN, PF0_OUT, PF0_IN, 0, )) 487 }, 488 { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2, GROUP( 489 PG7_FN, PG7_OUT, PG7_IN, 0, 490 PG6_FN, PG6_OUT, PG6_IN, 0, 491 PG5_FN, PG5_OUT, PG5_IN, 0, 492 PG4_FN, PG4_OUT, PG4_IN, 0, 493 PG3_FN, PG3_OUT, PG3_IN, 0, 494 PG2_FN, PG2_OUT, PG2_IN, 0, 495 PG1_FN, PG1_OUT, PG1_IN, 0, 496 PG0_FN, PG0_OUT, PG0_IN, 0, 497 0, 0, 0, 0, 498 0, 0, 0, 0, 499 PH5_FN, PH5_OUT, PH5_IN, 0, 500 PH4_FN, PH4_OUT, PH4_IN, 0, 501 PH3_FN, PH3_OUT, PH3_IN, 0, 502 PH2_FN, PH2_OUT, PH2_IN, 0, 503 PH1_FN, PH1_OUT, PH1_IN, 0, 504 PH0_FN, PH0_OUT, PH0_IN, 0, )) 505 }, 506 { }, 507 }; 508 509 static const struct pinmux_data_reg pinmux_data_regs[] = { 510 { PINMUX_DATA_REG("PABDR", 0xffc70010, 32, GROUP( 511 0, 0, 0, 0, 0, 0, 0, 0, 512 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 513 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, 514 0, 0, 0, 0, 0, 0, 0, 0, 515 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, 516 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, )) 517 }, 518 { PINMUX_DATA_REG("PCDDR", 0xffc70014, 32, GROUP( 519 0, 0, 0, 0, 0, 0, 0, 0, 520 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, 521 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, 522 0, 0, 0, 0, 0, 0, 0, 0, 523 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, 524 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, )) 525 }, 526 { PINMUX_DATA_REG("PEFDR", 0xffc70018, 32, GROUP( 527 0, 0, 0, 0, 0, 0, 0, 0, 528 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, 529 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, 530 0, 0, 0, 0, 0, 0, 0, 0, 531 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, 532 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, )) 533 }, 534 { PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32, GROUP( 535 0, 0, 0, 0, 0, 0, 0, 0, 536 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, 537 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA, 538 0, 0, 0, 0, 0, 0, 0, 0, 539 0, 0, PH5_DATA, PH4_DATA, 540 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, )) 541 }, 542 { }, 543 }; 544 545 const struct sh_pfc_soc_info shx3_pinmux_info = { 546 .name = "shx3_pfc", 547 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 548 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 549 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 550 .pins = pinmux_pins, 551 .nr_pins = ARRAY_SIZE(pinmux_pins), 552 .func_gpios = pinmux_func_gpios, 553 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), 554 .pinmux_data = pinmux_data, 555 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 556 .cfg_regs = pinmux_config_regs, 557 .data_regs = pinmux_data_regs, 558 }; 559