1 /*
2 * Allwinner a33 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
5 *
6 * Based on pinctrl-sun8i-a23.c, which is:
7 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/pinctrl/pinctrl.h>
20
21 #include "pinctrl-sunxi.h"
22
23 static const struct sunxi_desc_pin sun8i_a33_pins[] = {
24 /* Hole */
25 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
29 SUNXI_FUNCTION(0x3, "uart0"), /* TX */
30 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
35 SUNXI_FUNCTION(0x3, "uart0"), /* RX */
36 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
41 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */
42 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
43 SUNXI_FUNCTION(0x0, "gpio_in"),
44 SUNXI_FUNCTION(0x1, "gpio_out"),
45 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
46 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
48 SUNXI_FUNCTION(0x0, "gpio_in"),
49 SUNXI_FUNCTION(0x1, "gpio_out"),
50 SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
51 SUNXI_FUNCTION(0x3, "aif2"), /* SYNC */
52 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PB_EINT4 */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
57 SUNXI_FUNCTION(0x3, "aif2"), /* BCLK */
58 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PB_EINT5 */
59 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
60 SUNXI_FUNCTION(0x0, "gpio_in"),
61 SUNXI_FUNCTION(0x1, "gpio_out"),
62 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
63 SUNXI_FUNCTION(0x3, "aif2"), /* DOUT */
64 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PB_EINT6 */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
69 SUNXI_FUNCTION(0x3, "aif2"), /* DIN */
70 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PB_EINT7 */
71 /* Hole */
72 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
73 SUNXI_FUNCTION(0x0, "gpio_in"),
74 SUNXI_FUNCTION(0x1, "gpio_out"),
75 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
76 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
77 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
78 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out"),
80 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
81 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
82 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
83 SUNXI_FUNCTION(0x0, "gpio_in"),
84 SUNXI_FUNCTION(0x1, "gpio_out"),
85 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
86 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
87 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
88 SUNXI_FUNCTION(0x0, "gpio_in"),
89 SUNXI_FUNCTION(0x1, "gpio_out"),
90 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
91 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
92 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
93 SUNXI_FUNCTION(0x0, "gpio_in"),
94 SUNXI_FUNCTION(0x1, "gpio_out"),
95 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
96 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
97 SUNXI_FUNCTION(0x0, "gpio_in"),
98 SUNXI_FUNCTION(0x1, "gpio_out"),
99 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
100 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
105 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
106 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
107 SUNXI_FUNCTION(0x0, "gpio_in"),
108 SUNXI_FUNCTION(0x1, "gpio_out"),
109 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
114 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
115 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
116 SUNXI_FUNCTION(0x0, "gpio_in"),
117 SUNXI_FUNCTION(0x1, "gpio_out"),
118 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
119 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
120 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
121 SUNXI_FUNCTION(0x0, "gpio_in"),
122 SUNXI_FUNCTION(0x1, "gpio_out"),
123 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
124 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
125 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
126 SUNXI_FUNCTION(0x0, "gpio_in"),
127 SUNXI_FUNCTION(0x1, "gpio_out"),
128 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
129 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
130 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
131 SUNXI_FUNCTION(0x0, "gpio_in"),
132 SUNXI_FUNCTION(0x1, "gpio_out"),
133 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
134 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
135 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
136 SUNXI_FUNCTION(0x0, "gpio_in"),
137 SUNXI_FUNCTION(0x1, "gpio_out"),
138 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
139 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
140 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
141 SUNXI_FUNCTION(0x0, "gpio_in"),
142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
144 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
145 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out"),
148 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
149 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
154 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
155 /* Hole */
156 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
157 SUNXI_FUNCTION(0x0, "gpio_in"),
158 SUNXI_FUNCTION(0x1, "gpio_out"),
159 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
160 SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
161 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
162 SUNXI_FUNCTION(0x0, "gpio_in"),
163 SUNXI_FUNCTION(0x1, "gpio_out"),
164 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
165 SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
166 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
167 SUNXI_FUNCTION(0x0, "gpio_in"),
168 SUNXI_FUNCTION(0x1, "gpio_out"),
169 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
170 SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
171 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
172 SUNXI_FUNCTION(0x0, "gpio_in"),
173 SUNXI_FUNCTION(0x1, "gpio_out"),
174 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
175 SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
176 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
177 SUNXI_FUNCTION(0x0, "gpio_in"),
178 SUNXI_FUNCTION(0x1, "gpio_out"),
179 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
180 SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out"),
184 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
185 SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
186 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
187 SUNXI_FUNCTION(0x0, "gpio_in"),
188 SUNXI_FUNCTION(0x1, "gpio_out"),
189 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
190 SUNXI_FUNCTION(0x3, "uart1")), /* TX */
191 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
195 SUNXI_FUNCTION(0x3, "uart1")), /* RX */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
200 SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
201 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
202 SUNXI_FUNCTION(0x0, "gpio_in"),
203 SUNXI_FUNCTION(0x1, "gpio_out"),
204 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
205 SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
206 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
207 SUNXI_FUNCTION(0x0, "gpio_in"),
208 SUNXI_FUNCTION(0x1, "gpio_out"),
209 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
210 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
211 SUNXI_FUNCTION(0x0, "gpio_in"),
212 SUNXI_FUNCTION(0x1, "gpio_out"),
213 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
214 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
215 SUNXI_FUNCTION(0x0, "gpio_in"),
216 SUNXI_FUNCTION(0x1, "gpio_out"),
217 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
218 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
219 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
220 SUNXI_FUNCTION(0x0, "gpio_in"),
221 SUNXI_FUNCTION(0x1, "gpio_out"),
222 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
223 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
224 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
225 SUNXI_FUNCTION(0x0, "gpio_in"),
226 SUNXI_FUNCTION(0x1, "gpio_out"),
227 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
228 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
229 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
230 SUNXI_FUNCTION(0x0, "gpio_in"),
231 SUNXI_FUNCTION(0x1, "gpio_out"),
232 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
233 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
234 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
235 SUNXI_FUNCTION(0x0, "gpio_in"),
236 SUNXI_FUNCTION(0x1, "gpio_out"),
237 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
238 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
239 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
240 SUNXI_FUNCTION(0x0, "gpio_in"),
241 SUNXI_FUNCTION(0x1, "gpio_out"),
242 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
243 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
244 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
245 SUNXI_FUNCTION(0x0, "gpio_in"),
246 SUNXI_FUNCTION(0x1, "gpio_out"),
247 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
248 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
249 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
250 SUNXI_FUNCTION(0x0, "gpio_in"),
251 SUNXI_FUNCTION(0x1, "gpio_out"),
252 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
253 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
254 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
255 SUNXI_FUNCTION(0x0, "gpio_in"),
256 SUNXI_FUNCTION(0x1, "gpio_out"),
257 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
258 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
259 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
260 SUNXI_FUNCTION(0x0, "gpio_in"),
261 SUNXI_FUNCTION(0x1, "gpio_out"),
262 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
263 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
264 /* Hole */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
269 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
270 SUNXI_FUNCTION(0x0, "gpio_in"),
271 SUNXI_FUNCTION(0x1, "gpio_out"),
272 SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
273 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
274 SUNXI_FUNCTION(0x0, "gpio_in"),
275 SUNXI_FUNCTION(0x1, "gpio_out"),
276 SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
277 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
278 SUNXI_FUNCTION(0x0, "gpio_in"),
279 SUNXI_FUNCTION(0x1, "gpio_out"),
280 SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
281 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
282 SUNXI_FUNCTION(0x0, "gpio_in"),
283 SUNXI_FUNCTION(0x1, "gpio_out"),
284 SUNXI_FUNCTION(0x2, "csi")), /* D0 */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x2, "csi")), /* D1 */
289 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "csi")), /* D2 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "csi")), /* D3 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "csi")), /* D4 */
301 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
302 SUNXI_FUNCTION(0x0, "gpio_in"),
303 SUNXI_FUNCTION(0x1, "gpio_out"),
304 SUNXI_FUNCTION(0x2, "csi")), /* D5 */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "csi")), /* D6 */
309 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "csi")), /* D7 */
313 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
314 SUNXI_FUNCTION(0x0, "gpio_in"),
315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
317 SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
322 SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out")),
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out")),
329 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
330 SUNXI_FUNCTION(0x0, "gpio_in"),
331 SUNXI_FUNCTION(0x1, "gpio_out")),
332 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
333 SUNXI_FUNCTION(0x0, "gpio_in"),
334 SUNXI_FUNCTION(0x1, "gpio_out")),
335 /* Hole */
336 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
337 SUNXI_FUNCTION(0x0, "gpio_in"),
338 SUNXI_FUNCTION(0x1, "gpio_out"),
339 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
340 SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
341 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
342 SUNXI_FUNCTION(0x0, "gpio_in"),
343 SUNXI_FUNCTION(0x1, "gpio_out"),
344 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
345 SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
346 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
347 SUNXI_FUNCTION(0x0, "gpio_in"),
348 SUNXI_FUNCTION(0x1, "gpio_out"),
349 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
350 SUNXI_FUNCTION(0x3, "uart0")), /* TX */
351 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
352 SUNXI_FUNCTION(0x0, "gpio_in"),
353 SUNXI_FUNCTION(0x1, "gpio_out"),
354 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
355 SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
356 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
357 SUNXI_FUNCTION(0x0, "gpio_in"),
358 SUNXI_FUNCTION(0x1, "gpio_out"),
359 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
360 SUNXI_FUNCTION(0x3, "uart0")), /* RX */
361 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
362 SUNXI_FUNCTION(0x0, "gpio_in"),
363 SUNXI_FUNCTION(0x1, "gpio_out"),
364 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
365 SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
366 /* Hole */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
371 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PG_EINT0 */
372 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
373 SUNXI_FUNCTION(0x0, "gpio_in"),
374 SUNXI_FUNCTION(0x1, "gpio_out"),
375 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
376 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PG_EINT1 */
377 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
378 SUNXI_FUNCTION(0x0, "gpio_in"),
379 SUNXI_FUNCTION(0x1, "gpio_out"),
380 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
381 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PG_EINT2 */
382 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
383 SUNXI_FUNCTION(0x0, "gpio_in"),
384 SUNXI_FUNCTION(0x1, "gpio_out"),
385 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
386 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PG_EINT3 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
391 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PG_EINT4 */
392 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
396 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PG_EINT5 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
401 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PG_EINT6 */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
406 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PG_EINT7 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
411 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
416 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
421 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */
422 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
426 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
431 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out"),
435 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
436 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */
437 /* Hole */
438 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
439 SUNXI_FUNCTION(0x0, "gpio_in"),
440 SUNXI_FUNCTION(0x1, "gpio_out"),
441 SUNXI_FUNCTION(0x2, "pwm0")),
442 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
443 SUNXI_FUNCTION(0x0, "gpio_in"),
444 SUNXI_FUNCTION(0x1, "gpio_out"),
445 SUNXI_FUNCTION(0x2, "pwm1")),
446 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
447 SUNXI_FUNCTION(0x0, "gpio_in"),
448 SUNXI_FUNCTION(0x1, "gpio_out"),
449 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
454 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
455 SUNXI_FUNCTION(0x0, "gpio_in"),
456 SUNXI_FUNCTION(0x1, "gpio_out"),
457 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
458 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
459 SUNXI_FUNCTION(0x0, "gpio_in"),
460 SUNXI_FUNCTION(0x1, "gpio_out"),
461 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
462 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "spi0"), /* CS */
466 SUNXI_FUNCTION(0x3, "uart3")), /* TX */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
471 SUNXI_FUNCTION(0x3, "uart3")), /* RX */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
476 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
477 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
481 SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
482 };
483
484 static const unsigned int sun8i_a33_pinctrl_irq_bank_map[] = { 1, 2 };
485
486 static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
487 .pins = sun8i_a33_pins,
488 .npins = ARRAY_SIZE(sun8i_a33_pins),
489 .irq_banks = 2,
490 .irq_bank_map = sun8i_a33_pinctrl_irq_bank_map,
491 .disable_strict_mode = true,
492 };
493
sun8i_a33_pinctrl_probe(struct platform_device * pdev)494 static int sun8i_a33_pinctrl_probe(struct platform_device *pdev)
495 {
496 return sunxi_pinctrl_init(pdev,
497 &sun8i_a33_pinctrl_data);
498 }
499
500 static const struct of_device_id sun8i_a33_pinctrl_match[] = {
501 { .compatible = "allwinner,sun8i-a33-pinctrl", },
502 {}
503 };
504
505 static struct platform_driver sun8i_a33_pinctrl_driver = {
506 .probe = sun8i_a33_pinctrl_probe,
507 .driver = {
508 .name = "sun8i-a33-pinctrl",
509 .of_match_table = sun8i_a33_pinctrl_match,
510 },
511 };
512 builtin_platform_driver(sun8i_a33_pinctrl_driver);
513