1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AM33XX Power Management Routines
4 *
5 * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Vaibhav Bedia, Dave Gerlach
7 */
8
9 #include <linux/clk.h>
10 #include <linux/cpu.h>
11 #include <linux/err.h>
12 #include <linux/genalloc.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/nvmem-consumer.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/platform_data/pm33xx.h>
21 #include <linux/platform_device.h>
22 #include <linux/rtc.h>
23 #include <linux/rtc/rtc-omap.h>
24 #include <linux/sizes.h>
25 #include <linux/sram.h>
26 #include <linux/suspend.h>
27 #include <linux/ti-emif-sram.h>
28 #include <linux/wkup_m3_ipc.h>
29
30 #include <asm/proc-fns.h>
31 #include <asm/suspend.h>
32 #include <asm/system_misc.h>
33
34 #define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
35 (unsigned long)pm_sram->do_wfi)
36
37 #define RTC_SCRATCH_RESUME_REG 0
38 #define RTC_SCRATCH_MAGIC_REG 1
39 #define RTC_REG_BOOT_MAGIC 0x8cd0 /* RTC */
40 #define GIC_INT_SET_PENDING_BASE 0x200
41 #define AM43XX_GIC_DIST_BASE 0x48241000
42
43 static void __iomem *rtc_base_virt;
44 static struct clk *rtc_fck;
45 static u32 rtc_magic_val;
46
47 static int (*am33xx_do_wfi_sram)(unsigned long unused);
48 static phys_addr_t am33xx_do_wfi_sram_phys;
49
50 static struct gen_pool *sram_pool, *sram_pool_data;
51 static unsigned long ocmcram_location, ocmcram_location_data;
52
53 static struct rtc_device *omap_rtc;
54 static void __iomem *gic_dist_base;
55
56 static struct am33xx_pm_platform_data *pm_ops;
57 static struct am33xx_pm_sram_addr *pm_sram;
58
59 static struct device *pm33xx_dev;
60 static struct wkup_m3_ipc *m3_ipc;
61
62 #ifdef CONFIG_SUSPEND
63 static int rtc_only_idle;
64 static int retrigger_irq;
65 static unsigned long suspend_wfi_flags;
66
67 static struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0,
68 .src = "Unknown",
69 };
70
71 static struct wkup_m3_wakeup_src rtc_alarm_wakeup = {
72 .irq_nr = 108, .src = "RTC Alarm",
73 };
74
75 static struct wkup_m3_wakeup_src rtc_ext_wakeup = {
76 .irq_nr = 0, .src = "Ext wakeup",
77 };
78 #endif
79
sram_suspend_address(unsigned long addr)80 static u32 sram_suspend_address(unsigned long addr)
81 {
82 return ((unsigned long)am33xx_do_wfi_sram +
83 AMX3_PM_SRAM_SYMBOL_OFFSET(addr));
84 }
85
am33xx_push_sram_idle(void)86 static int am33xx_push_sram_idle(void)
87 {
88 struct am33xx_pm_ro_sram_data ro_sram_data;
89 int ret;
90 u32 table_addr, ro_data_addr;
91 void *copy_addr;
92
93 ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data;
94 ro_sram_data.amx3_pm_sram_data_phys =
95 gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data);
96 ro_sram_data.rtc_base_virt = rtc_base_virt;
97
98 /* Save physical address to calculate resume offset during pm init */
99 am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool,
100 ocmcram_location);
101
102 am33xx_do_wfi_sram = sram_exec_copy(sram_pool, (void *)ocmcram_location,
103 pm_sram->do_wfi,
104 *pm_sram->do_wfi_sz);
105 if (!am33xx_do_wfi_sram) {
106 dev_err(pm33xx_dev,
107 "PM: %s: am33xx_do_wfi copy to sram failed\n",
108 __func__);
109 return -ENODEV;
110 }
111
112 table_addr =
113 sram_suspend_address((unsigned long)pm_sram->emif_sram_table);
114 ret = ti_emif_copy_pm_function_table(sram_pool, (void *)table_addr);
115 if (ret) {
116 dev_dbg(pm33xx_dev,
117 "PM: %s: EMIF function copy failed\n", __func__);
118 return -EPROBE_DEFER;
119 }
120
121 ro_data_addr =
122 sram_suspend_address((unsigned long)pm_sram->ro_sram_data);
123 copy_addr = sram_exec_copy(sram_pool, (void *)ro_data_addr,
124 &ro_sram_data,
125 sizeof(ro_sram_data));
126 if (!copy_addr) {
127 dev_err(pm33xx_dev,
128 "PM: %s: ro_sram_data copy to sram failed\n",
129 __func__);
130 return -ENODEV;
131 }
132
133 return 0;
134 }
135
am33xx_do_sram_idle(u32 wfi_flags)136 static int am33xx_do_sram_idle(u32 wfi_flags)
137 {
138 int ret = 0;
139
140 if (!m3_ipc || !pm_ops)
141 return 0;
142
143 if (wfi_flags & WFI_FLAG_WAKE_M3)
144 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_IDLE);
145
146 return pm_ops->cpu_suspend(am33xx_do_wfi_sram, wfi_flags);
147 }
148
am43xx_map_gic(void)149 static int __init am43xx_map_gic(void)
150 {
151 gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K);
152
153 if (!gic_dist_base)
154 return -ENOMEM;
155
156 return 0;
157 }
158
159 #ifdef CONFIG_SUSPEND
rtc_wake_src(void)160 static struct wkup_m3_wakeup_src rtc_wake_src(void)
161 {
162 u32 i;
163
164 i = __raw_readl(rtc_base_virt + 0x44) & 0x40;
165
166 if (i) {
167 retrigger_irq = rtc_alarm_wakeup.irq_nr;
168 return rtc_alarm_wakeup;
169 }
170
171 retrigger_irq = rtc_ext_wakeup.irq_nr;
172
173 return rtc_ext_wakeup;
174 }
175
am33xx_rtc_only_idle(unsigned long wfi_flags)176 static int am33xx_rtc_only_idle(unsigned long wfi_flags)
177 {
178 omap_rtc_power_off_program(&omap_rtc->dev);
179 am33xx_do_wfi_sram(wfi_flags);
180 return 0;
181 }
182
183 /*
184 * Note that the RTC module clock must be re-enabled only for rtc+ddr suspend.
185 * And looks like the module can stay in SYSC_IDLE_SMART_WKUP mode configured
186 * by the interconnect code just fine for both rtc+ddr suspend and retention
187 * suspend.
188 */
am33xx_pm_suspend(suspend_state_t suspend_state)189 static int am33xx_pm_suspend(suspend_state_t suspend_state)
190 {
191 int i, ret = 0;
192
193 if (suspend_state == PM_SUSPEND_MEM &&
194 pm_ops->check_off_mode_enable()) {
195 ret = clk_prepare_enable(rtc_fck);
196 if (ret) {
197 dev_err(pm33xx_dev, "Failed to enable clock: %i\n", ret);
198 return ret;
199 }
200
201 pm_ops->save_context();
202 suspend_wfi_flags |= WFI_FLAG_RTC_ONLY;
203 clk_save_context();
204 ret = pm_ops->soc_suspend(suspend_state, am33xx_rtc_only_idle,
205 suspend_wfi_flags);
206
207 suspend_wfi_flags &= ~WFI_FLAG_RTC_ONLY;
208 dev_info(pm33xx_dev, "Entering RTC Only mode with DDR in self-refresh\n");
209
210 if (!ret) {
211 clk_restore_context();
212 pm_ops->restore_context();
213 m3_ipc->ops->set_rtc_only(m3_ipc);
214 am33xx_push_sram_idle();
215 }
216 } else {
217 ret = pm_ops->soc_suspend(suspend_state, am33xx_do_wfi_sram,
218 suspend_wfi_flags);
219 }
220
221 if (ret) {
222 dev_err(pm33xx_dev, "PM: Kernel suspend failure\n");
223 } else {
224 i = m3_ipc->ops->request_pm_status(m3_ipc);
225
226 switch (i) {
227 case 0:
228 dev_info(pm33xx_dev,
229 "PM: Successfully put all powerdomains to target state\n");
230 break;
231 case 1:
232 dev_err(pm33xx_dev,
233 "PM: Could not transition all powerdomains to target state\n");
234 ret = -1;
235 break;
236 default:
237 dev_err(pm33xx_dev,
238 "PM: CM3 returned unknown result = %d\n", i);
239 ret = -1;
240 }
241
242 /* print the wakeup reason */
243 if (rtc_only_idle) {
244 wakeup_src = rtc_wake_src();
245 pr_info("PM: Wakeup source %s\n", wakeup_src.src);
246 } else {
247 pr_info("PM: Wakeup source %s\n",
248 m3_ipc->ops->request_wake_src(m3_ipc));
249 }
250 }
251
252 if (suspend_state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable())
253 clk_disable_unprepare(rtc_fck);
254
255 return ret;
256 }
257
am33xx_pm_enter(suspend_state_t suspend_state)258 static int am33xx_pm_enter(suspend_state_t suspend_state)
259 {
260 int ret = 0;
261
262 switch (suspend_state) {
263 case PM_SUSPEND_MEM:
264 case PM_SUSPEND_STANDBY:
265 ret = am33xx_pm_suspend(suspend_state);
266 break;
267 default:
268 ret = -EINVAL;
269 }
270
271 return ret;
272 }
273
am33xx_pm_begin(suspend_state_t state)274 static int am33xx_pm_begin(suspend_state_t state)
275 {
276 int ret = -EINVAL;
277 struct nvmem_device *nvmem;
278
279 if (state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) {
280 nvmem = devm_nvmem_device_get(&omap_rtc->dev,
281 "omap_rtc_scratch0");
282 if (!IS_ERR(nvmem))
283 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
284 (void *)&rtc_magic_val);
285 rtc_only_idle = 1;
286 } else {
287 rtc_only_idle = 0;
288 }
289
290 pm_ops->begin_suspend();
291
292 switch (state) {
293 case PM_SUSPEND_MEM:
294 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_DEEPSLEEP);
295 break;
296 case PM_SUSPEND_STANDBY:
297 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_STANDBY);
298 break;
299 }
300
301 return ret;
302 }
303
am33xx_pm_end(void)304 static void am33xx_pm_end(void)
305 {
306 u32 val = 0;
307 struct nvmem_device *nvmem;
308
309 nvmem = devm_nvmem_device_get(&omap_rtc->dev, "omap_rtc_scratch0");
310 if (IS_ERR(nvmem))
311 return;
312
313 m3_ipc->ops->finish_low_power(m3_ipc);
314 if (rtc_only_idle) {
315 if (retrigger_irq) {
316 /*
317 * 32 bits of Interrupt Set-Pending correspond to 32
318 * 32 interrupts. Compute the bit offset of the
319 * Interrupt and set that particular bit
320 * Compute the register offset by dividing interrupt
321 * number by 32 and mutiplying by 4
322 */
323 writel_relaxed(1 << (retrigger_irq & 31),
324 gic_dist_base + GIC_INT_SET_PENDING_BASE
325 + retrigger_irq / 32 * 4);
326 }
327
328 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
329 (void *)&val);
330 }
331
332 rtc_only_idle = 0;
333
334 pm_ops->finish_suspend();
335 }
336
am33xx_pm_valid(suspend_state_t state)337 static int am33xx_pm_valid(suspend_state_t state)
338 {
339 switch (state) {
340 case PM_SUSPEND_STANDBY:
341 case PM_SUSPEND_MEM:
342 return 1;
343 default:
344 return 0;
345 }
346 }
347
348 static const struct platform_suspend_ops am33xx_pm_ops = {
349 .begin = am33xx_pm_begin,
350 .end = am33xx_pm_end,
351 .enter = am33xx_pm_enter,
352 .valid = am33xx_pm_valid,
353 };
354 #endif /* CONFIG_SUSPEND */
355
am33xx_pm_set_ipc_ops(void)356 static void am33xx_pm_set_ipc_ops(void)
357 {
358 u32 resume_address;
359 int temp;
360
361 temp = ti_emif_get_mem_type();
362 if (temp < 0) {
363 dev_err(pm33xx_dev, "PM: Cannot determine memory type, no PM available\n");
364 return;
365 }
366 m3_ipc->ops->set_mem_type(m3_ipc, temp);
367
368 /* Physical resume address to be used by ROM code */
369 resume_address = am33xx_do_wfi_sram_phys +
370 *pm_sram->resume_offset + 0x4;
371
372 m3_ipc->ops->set_resume_address(m3_ipc, (void *)resume_address);
373 }
374
am33xx_pm_free_sram(void)375 static void am33xx_pm_free_sram(void)
376 {
377 gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
378 gen_pool_free(sram_pool_data, ocmcram_location_data,
379 sizeof(struct am33xx_pm_ro_sram_data));
380 }
381
382 /*
383 * Push the minimal suspend-resume code to SRAM
384 */
am33xx_pm_alloc_sram(void)385 static int am33xx_pm_alloc_sram(void)
386 {
387 struct device_node *np;
388 int ret = 0;
389
390 np = of_find_compatible_node(NULL, NULL, "ti,omap3-mpu");
391 if (!np) {
392 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
393 if (!np) {
394 dev_err(pm33xx_dev, "PM: %s: Unable to find device node for mpu\n",
395 __func__);
396 return -ENODEV;
397 }
398 }
399
400 sram_pool = of_gen_pool_get(np, "pm-sram", 0);
401 if (!sram_pool) {
402 dev_err(pm33xx_dev, "PM: %s: Unable to get sram pool for ocmcram\n",
403 __func__);
404 ret = -ENODEV;
405 goto mpu_put_node;
406 }
407
408 sram_pool_data = of_gen_pool_get(np, "pm-sram", 1);
409 if (!sram_pool_data) {
410 dev_err(pm33xx_dev, "PM: %s: Unable to get sram data pool for ocmcram\n",
411 __func__);
412 ret = -ENODEV;
413 goto mpu_put_node;
414 }
415
416 ocmcram_location = gen_pool_alloc(sram_pool, *pm_sram->do_wfi_sz);
417 if (!ocmcram_location) {
418 dev_err(pm33xx_dev, "PM: %s: Unable to allocate memory from ocmcram\n",
419 __func__);
420 ret = -ENOMEM;
421 goto mpu_put_node;
422 }
423
424 ocmcram_location_data = gen_pool_alloc(sram_pool_data,
425 sizeof(struct emif_regs_amx3));
426 if (!ocmcram_location_data) {
427 dev_err(pm33xx_dev, "PM: Unable to allocate memory from ocmcram\n");
428 gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
429 ret = -ENOMEM;
430 }
431
432 mpu_put_node:
433 of_node_put(np);
434 return ret;
435 }
436
am33xx_pm_rtc_setup(void)437 static int am33xx_pm_rtc_setup(void)
438 {
439 struct device_node *np;
440 unsigned long val = 0;
441 struct nvmem_device *nvmem;
442 int error;
443
444 np = of_find_node_by_name(NULL, "rtc");
445
446 if (of_device_is_available(np)) {
447 /* RTC interconnect target module clock */
448 rtc_fck = of_clk_get_by_name(np->parent, "fck");
449 if (IS_ERR(rtc_fck))
450 return PTR_ERR(rtc_fck);
451
452 rtc_base_virt = of_iomap(np, 0);
453 if (!rtc_base_virt) {
454 pr_warn("PM: could not iomap rtc");
455 error = -ENODEV;
456 goto err_clk_put;
457 }
458
459 omap_rtc = rtc_class_open("rtc0");
460 if (!omap_rtc) {
461 pr_warn("PM: rtc0 not available");
462 error = -EPROBE_DEFER;
463 goto err_iounmap;
464 }
465
466 nvmem = devm_nvmem_device_get(&omap_rtc->dev,
467 "omap_rtc_scratch0");
468 if (!IS_ERR(nvmem)) {
469 nvmem_device_read(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
470 4, (void *)&rtc_magic_val);
471 if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC)
472 pr_warn("PM: bootloader does not support rtc-only!\n");
473
474 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
475 4, (void *)&val);
476 val = pm_sram->resume_address;
477 nvmem_device_write(nvmem, RTC_SCRATCH_RESUME_REG * 4,
478 4, (void *)&val);
479 }
480 } else {
481 pr_warn("PM: no-rtc available, rtc-only mode disabled.\n");
482 }
483
484 return 0;
485
486 err_iounmap:
487 iounmap(rtc_base_virt);
488 err_clk_put:
489 clk_put(rtc_fck);
490
491 return error;
492 }
493
am33xx_pm_probe(struct platform_device * pdev)494 static int am33xx_pm_probe(struct platform_device *pdev)
495 {
496 struct device *dev = &pdev->dev;
497 int ret;
498
499 if (!of_machine_is_compatible("ti,am33xx") &&
500 !of_machine_is_compatible("ti,am43"))
501 return -ENODEV;
502
503 pm_ops = dev->platform_data;
504 if (!pm_ops) {
505 dev_err(dev, "PM: Cannot get core PM ops!\n");
506 return -ENODEV;
507 }
508
509 ret = am43xx_map_gic();
510 if (ret) {
511 pr_err("PM: Could not ioremap GIC base\n");
512 return ret;
513 }
514
515 pm_sram = pm_ops->get_sram_addrs();
516 if (!pm_sram) {
517 dev_err(dev, "PM: Cannot get PM asm function addresses!!\n");
518 return -ENODEV;
519 }
520
521 m3_ipc = wkup_m3_ipc_get();
522 if (!m3_ipc) {
523 pr_err("PM: Cannot get wkup_m3_ipc handle\n");
524 return -EPROBE_DEFER;
525 }
526
527 pm33xx_dev = dev;
528
529 ret = am33xx_pm_alloc_sram();
530 if (ret)
531 return ret;
532
533 ret = am33xx_pm_rtc_setup();
534 if (ret)
535 goto err_free_sram;
536
537 ret = am33xx_push_sram_idle();
538 if (ret)
539 goto err_unsetup_rtc;
540
541 am33xx_pm_set_ipc_ops();
542
543 #ifdef CONFIG_SUSPEND
544 suspend_set_ops(&am33xx_pm_ops);
545
546 /*
547 * For a system suspend we must flush the caches, we want
548 * the DDR in self-refresh, we want to save the context
549 * of the EMIF, and we want the wkup_m3 to handle low-power
550 * transition.
551 */
552 suspend_wfi_flags |= WFI_FLAG_FLUSH_CACHE;
553 suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH;
554 suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF;
555 suspend_wfi_flags |= WFI_FLAG_WAKE_M3;
556 #endif /* CONFIG_SUSPEND */
557
558 ret = pm_ops->init(am33xx_do_sram_idle);
559 if (ret) {
560 dev_err(dev, "Unable to call core pm init!\n");
561 ret = -ENODEV;
562 goto err_put_wkup_m3_ipc;
563 }
564
565 return 0;
566
567 err_put_wkup_m3_ipc:
568 wkup_m3_ipc_put(m3_ipc);
569 err_unsetup_rtc:
570 iounmap(rtc_base_virt);
571 clk_put(rtc_fck);
572 err_free_sram:
573 am33xx_pm_free_sram();
574 pm33xx_dev = NULL;
575 return ret;
576 }
577
am33xx_pm_remove(struct platform_device * pdev)578 static int am33xx_pm_remove(struct platform_device *pdev)
579 {
580 if (pm_ops->deinit)
581 pm_ops->deinit();
582 suspend_set_ops(NULL);
583 wkup_m3_ipc_put(m3_ipc);
584 am33xx_pm_free_sram();
585 iounmap(rtc_base_virt);
586 clk_put(rtc_fck);
587 return 0;
588 }
589
590 static struct platform_driver am33xx_pm_driver = {
591 .driver = {
592 .name = "pm33xx",
593 },
594 .probe = am33xx_pm_probe,
595 .remove = am33xx_pm_remove,
596 };
597 module_platform_driver(am33xx_pm_driver);
598
599 MODULE_ALIAS("platform:pm33xx");
600 MODULE_LICENSE("GPL v2");
601 MODULE_DESCRIPTION("am33xx power management driver");
602