1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2012 - 2014 Allwinner Tech
4 * Pan Nan <pannan@allwinnertech.com>
5 *
6 * Copyright (C) 2014 Maxime Ripard
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/reset.h>
21
22 #include <linux/spi/spi.h>
23
24 #define SUN6I_FIFO_DEPTH 128
25 #define SUN8I_FIFO_DEPTH 64
26
27 #define SUN6I_GBL_CTL_REG 0x04
28 #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
29 #define SUN6I_GBL_CTL_MASTER BIT(1)
30 #define SUN6I_GBL_CTL_TP BIT(7)
31 #define SUN6I_GBL_CTL_RST BIT(31)
32
33 #define SUN6I_TFR_CTL_REG 0x08
34 #define SUN6I_TFR_CTL_CPHA BIT(0)
35 #define SUN6I_TFR_CTL_CPOL BIT(1)
36 #define SUN6I_TFR_CTL_SPOL BIT(2)
37 #define SUN6I_TFR_CTL_CS_MASK 0x30
38 #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
39 #define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
40 #define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
41 #define SUN6I_TFR_CTL_DHB BIT(8)
42 #define SUN6I_TFR_CTL_FBS BIT(12)
43 #define SUN6I_TFR_CTL_XCH BIT(31)
44
45 #define SUN6I_INT_CTL_REG 0x10
46 #define SUN6I_INT_CTL_RF_RDY BIT(0)
47 #define SUN6I_INT_CTL_TF_ERQ BIT(4)
48 #define SUN6I_INT_CTL_RF_OVF BIT(8)
49 #define SUN6I_INT_CTL_TC BIT(12)
50
51 #define SUN6I_INT_STA_REG 0x14
52
53 #define SUN6I_FIFO_CTL_REG 0x18
54 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
55 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
56 #define SUN6I_FIFO_CTL_RF_RST BIT(15)
57 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
58 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
59 #define SUN6I_FIFO_CTL_TF_RST BIT(31)
60
61 #define SUN6I_FIFO_STA_REG 0x1c
62 #define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0)
63 #define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16)
64
65 #define SUN6I_CLK_CTL_REG 0x24
66 #define SUN6I_CLK_CTL_CDR2_MASK 0xff
67 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
68 #define SUN6I_CLK_CTL_CDR1_MASK 0xf
69 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
70 #define SUN6I_CLK_CTL_DRS BIT(12)
71
72 #define SUN6I_MAX_XFER_SIZE 0xffffff
73
74 #define SUN6I_BURST_CNT_REG 0x30
75
76 #define SUN6I_XMIT_CNT_REG 0x34
77
78 #define SUN6I_BURST_CTL_CNT_REG 0x38
79
80 #define SUN6I_TXDATA_REG 0x200
81 #define SUN6I_RXDATA_REG 0x300
82
83 struct sun6i_spi {
84 struct spi_master *master;
85 void __iomem *base_addr;
86 struct clk *hclk;
87 struct clk *mclk;
88 struct reset_control *rstc;
89
90 struct completion done;
91
92 const u8 *tx_buf;
93 u8 *rx_buf;
94 int len;
95 unsigned long fifo_depth;
96 };
97
sun6i_spi_read(struct sun6i_spi * sspi,u32 reg)98 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
99 {
100 return readl(sspi->base_addr + reg);
101 }
102
sun6i_spi_write(struct sun6i_spi * sspi,u32 reg,u32 value)103 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
104 {
105 writel(value, sspi->base_addr + reg);
106 }
107
sun6i_spi_get_rx_fifo_count(struct sun6i_spi * sspi)108 static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
109 {
110 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
111
112 return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg);
113 }
114
sun6i_spi_get_tx_fifo_count(struct sun6i_spi * sspi)115 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
116 {
117 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
118
119 return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg);
120 }
121
sun6i_spi_disable_interrupt(struct sun6i_spi * sspi,u32 mask)122 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
123 {
124 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
125
126 reg &= ~mask;
127 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
128 }
129
sun6i_spi_drain_fifo(struct sun6i_spi * sspi)130 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
131 {
132 u32 len;
133 u8 byte;
134
135 /* See how much data is available */
136 len = sun6i_spi_get_rx_fifo_count(sspi);
137
138 while (len--) {
139 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
140 if (sspi->rx_buf)
141 *sspi->rx_buf++ = byte;
142 }
143 }
144
sun6i_spi_fill_fifo(struct sun6i_spi * sspi)145 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
146 {
147 u32 cnt;
148 int len;
149 u8 byte;
150
151 /* See how much data we can fit */
152 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
153
154 len = min((int)cnt, sspi->len);
155
156 while (len--) {
157 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
158 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
159 sspi->len--;
160 }
161 }
162
sun6i_spi_set_cs(struct spi_device * spi,bool enable)163 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
164 {
165 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
166 u32 reg;
167
168 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
169 reg &= ~SUN6I_TFR_CTL_CS_MASK;
170 reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
171
172 if (enable)
173 reg |= SUN6I_TFR_CTL_CS_LEVEL;
174 else
175 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
176
177 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
178 }
179
sun6i_spi_max_transfer_size(struct spi_device * spi)180 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
181 {
182 return SUN6I_MAX_XFER_SIZE - 1;
183 }
184
sun6i_spi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * tfr)185 static int sun6i_spi_transfer_one(struct spi_master *master,
186 struct spi_device *spi,
187 struct spi_transfer *tfr)
188 {
189 struct sun6i_spi *sspi = spi_master_get_devdata(master);
190 unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
191 unsigned int start, end, tx_time;
192 unsigned int trig_level;
193 unsigned int tx_len = 0, rx_len = 0;
194 int ret = 0;
195 u32 reg;
196
197 if (tfr->len > SUN6I_MAX_XFER_SIZE)
198 return -EINVAL;
199
200 reinit_completion(&sspi->done);
201 sspi->tx_buf = tfr->tx_buf;
202 sspi->rx_buf = tfr->rx_buf;
203 sspi->len = tfr->len;
204
205 /* Clear pending interrupts */
206 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
207
208 /* Reset FIFO */
209 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
210 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
211
212 /*
213 * Setup FIFO interrupt trigger level
214 * Here we choose 3/4 of the full fifo depth, as it's the hardcoded
215 * value used in old generation of Allwinner SPI controller.
216 * (See spi-sun4i.c)
217 */
218 trig_level = sspi->fifo_depth / 4 * 3;
219 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
220 (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
221 (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));
222
223 /*
224 * Setup the transfer control register: Chip Select,
225 * polarities, etc.
226 */
227 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
228
229 if (spi->mode & SPI_CPOL)
230 reg |= SUN6I_TFR_CTL_CPOL;
231 else
232 reg &= ~SUN6I_TFR_CTL_CPOL;
233
234 if (spi->mode & SPI_CPHA)
235 reg |= SUN6I_TFR_CTL_CPHA;
236 else
237 reg &= ~SUN6I_TFR_CTL_CPHA;
238
239 if (spi->mode & SPI_LSB_FIRST)
240 reg |= SUN6I_TFR_CTL_FBS;
241 else
242 reg &= ~SUN6I_TFR_CTL_FBS;
243
244 /*
245 * If it's a TX only transfer, we don't want to fill the RX
246 * FIFO with bogus data
247 */
248 if (sspi->rx_buf) {
249 reg &= ~SUN6I_TFR_CTL_DHB;
250 rx_len = tfr->len;
251 } else {
252 reg |= SUN6I_TFR_CTL_DHB;
253 }
254
255 /* We want to control the chip select manually */
256 reg |= SUN6I_TFR_CTL_CS_MANUAL;
257
258 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
259
260 /* Ensure that we have a parent clock fast enough */
261 mclk_rate = clk_get_rate(sspi->mclk);
262 if (mclk_rate < (2 * tfr->speed_hz)) {
263 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
264 mclk_rate = clk_get_rate(sspi->mclk);
265 }
266
267 /*
268 * Setup clock divider.
269 *
270 * We have two choices there. Either we can use the clock
271 * divide rate 1, which is calculated thanks to this formula:
272 * SPI_CLK = MOD_CLK / (2 ^ cdr)
273 * Or we can use CDR2, which is calculated with the formula:
274 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
275 * Wether we use the former or the latter is set through the
276 * DRS bit.
277 *
278 * First try CDR2, and if we can't reach the expected
279 * frequency, fall back to CDR1.
280 */
281 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
282 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
283 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
284 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
285 tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
286 } else {
287 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
288 reg = SUN6I_CLK_CTL_CDR1(div);
289 tfr->effective_speed_hz = mclk_rate / (1 << div);
290 }
291
292 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
293 /* Finally enable the bus - doing so before might raise SCK to HIGH */
294 reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
295 reg |= SUN6I_GBL_CTL_BUS_ENABLE;
296 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
297
298 /* Setup the transfer now... */
299 if (sspi->tx_buf)
300 tx_len = tfr->len;
301
302 /* Setup the counters */
303 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
304 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
305 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
306
307 /* Fill the TX FIFO */
308 sun6i_spi_fill_fifo(sspi);
309
310 /* Enable the interrupts */
311 reg = SUN6I_INT_CTL_TC;
312
313 if (rx_len > sspi->fifo_depth)
314 reg |= SUN6I_INT_CTL_RF_RDY;
315 if (tx_len > sspi->fifo_depth)
316 reg |= SUN6I_INT_CTL_TF_ERQ;
317
318 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
319
320 /* Start the transfer */
321 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
322 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
323
324 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
325 start = jiffies;
326 timeout = wait_for_completion_timeout(&sspi->done,
327 msecs_to_jiffies(tx_time));
328 end = jiffies;
329 if (!timeout) {
330 dev_warn(&master->dev,
331 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
332 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
333 jiffies_to_msecs(end - start), tx_time);
334 ret = -ETIMEDOUT;
335 }
336
337 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
338
339 return ret;
340 }
341
sun6i_spi_handler(int irq,void * dev_id)342 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
343 {
344 struct sun6i_spi *sspi = dev_id;
345 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
346
347 /* Transfer complete */
348 if (status & SUN6I_INT_CTL_TC) {
349 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
350 sun6i_spi_drain_fifo(sspi);
351 complete(&sspi->done);
352 return IRQ_HANDLED;
353 }
354
355 /* Receive FIFO 3/4 full */
356 if (status & SUN6I_INT_CTL_RF_RDY) {
357 sun6i_spi_drain_fifo(sspi);
358 /* Only clear the interrupt _after_ draining the FIFO */
359 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
360 return IRQ_HANDLED;
361 }
362
363 /* Transmit FIFO 3/4 empty */
364 if (status & SUN6I_INT_CTL_TF_ERQ) {
365 sun6i_spi_fill_fifo(sspi);
366
367 if (!sspi->len)
368 /* nothing left to transmit */
369 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
370
371 /* Only clear the interrupt _after_ re-seeding the FIFO */
372 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
373
374 return IRQ_HANDLED;
375 }
376
377 return IRQ_NONE;
378 }
379
sun6i_spi_runtime_resume(struct device * dev)380 static int sun6i_spi_runtime_resume(struct device *dev)
381 {
382 struct spi_master *master = dev_get_drvdata(dev);
383 struct sun6i_spi *sspi = spi_master_get_devdata(master);
384 int ret;
385
386 ret = clk_prepare_enable(sspi->hclk);
387 if (ret) {
388 dev_err(dev, "Couldn't enable AHB clock\n");
389 goto out;
390 }
391
392 ret = clk_prepare_enable(sspi->mclk);
393 if (ret) {
394 dev_err(dev, "Couldn't enable module clock\n");
395 goto err;
396 }
397
398 ret = reset_control_deassert(sspi->rstc);
399 if (ret) {
400 dev_err(dev, "Couldn't deassert the device from reset\n");
401 goto err2;
402 }
403
404 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
405 SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
406
407 return 0;
408
409 err2:
410 clk_disable_unprepare(sspi->mclk);
411 err:
412 clk_disable_unprepare(sspi->hclk);
413 out:
414 return ret;
415 }
416
sun6i_spi_runtime_suspend(struct device * dev)417 static int sun6i_spi_runtime_suspend(struct device *dev)
418 {
419 struct spi_master *master = dev_get_drvdata(dev);
420 struct sun6i_spi *sspi = spi_master_get_devdata(master);
421
422 reset_control_assert(sspi->rstc);
423 clk_disable_unprepare(sspi->mclk);
424 clk_disable_unprepare(sspi->hclk);
425
426 return 0;
427 }
428
sun6i_spi_probe(struct platform_device * pdev)429 static int sun6i_spi_probe(struct platform_device *pdev)
430 {
431 struct spi_master *master;
432 struct sun6i_spi *sspi;
433 int ret = 0, irq;
434
435 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
436 if (!master) {
437 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
438 return -ENOMEM;
439 }
440
441 platform_set_drvdata(pdev, master);
442 sspi = spi_master_get_devdata(master);
443
444 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
445 if (IS_ERR(sspi->base_addr)) {
446 ret = PTR_ERR(sspi->base_addr);
447 goto err_free_master;
448 }
449
450 irq = platform_get_irq(pdev, 0);
451 if (irq < 0) {
452 ret = -ENXIO;
453 goto err_free_master;
454 }
455
456 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
457 0, "sun6i-spi", sspi);
458 if (ret) {
459 dev_err(&pdev->dev, "Cannot request IRQ\n");
460 goto err_free_master;
461 }
462
463 sspi->master = master;
464 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
465
466 master->max_speed_hz = 100 * 1000 * 1000;
467 master->min_speed_hz = 3 * 1000;
468 master->use_gpio_descriptors = true;
469 master->set_cs = sun6i_spi_set_cs;
470 master->transfer_one = sun6i_spi_transfer_one;
471 master->num_chipselect = 4;
472 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
473 master->bits_per_word_mask = SPI_BPW_MASK(8);
474 master->dev.of_node = pdev->dev.of_node;
475 master->auto_runtime_pm = true;
476 master->max_transfer_size = sun6i_spi_max_transfer_size;
477
478 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
479 if (IS_ERR(sspi->hclk)) {
480 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
481 ret = PTR_ERR(sspi->hclk);
482 goto err_free_master;
483 }
484
485 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
486 if (IS_ERR(sspi->mclk)) {
487 dev_err(&pdev->dev, "Unable to acquire module clock\n");
488 ret = PTR_ERR(sspi->mclk);
489 goto err_free_master;
490 }
491
492 init_completion(&sspi->done);
493
494 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
495 if (IS_ERR(sspi->rstc)) {
496 dev_err(&pdev->dev, "Couldn't get reset controller\n");
497 ret = PTR_ERR(sspi->rstc);
498 goto err_free_master;
499 }
500
501 /*
502 * This wake-up/shutdown pattern is to be able to have the
503 * device woken up, even if runtime_pm is disabled
504 */
505 ret = sun6i_spi_runtime_resume(&pdev->dev);
506 if (ret) {
507 dev_err(&pdev->dev, "Couldn't resume the device\n");
508 goto err_free_master;
509 }
510
511 pm_runtime_set_active(&pdev->dev);
512 pm_runtime_enable(&pdev->dev);
513 pm_runtime_idle(&pdev->dev);
514
515 ret = devm_spi_register_master(&pdev->dev, master);
516 if (ret) {
517 dev_err(&pdev->dev, "cannot register SPI master\n");
518 goto err_pm_disable;
519 }
520
521 return 0;
522
523 err_pm_disable:
524 pm_runtime_disable(&pdev->dev);
525 sun6i_spi_runtime_suspend(&pdev->dev);
526 err_free_master:
527 spi_master_put(master);
528 return ret;
529 }
530
sun6i_spi_remove(struct platform_device * pdev)531 static int sun6i_spi_remove(struct platform_device *pdev)
532 {
533 pm_runtime_force_suspend(&pdev->dev);
534
535 return 0;
536 }
537
538 static const struct of_device_id sun6i_spi_match[] = {
539 { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
540 { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
541 {}
542 };
543 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
544
545 static const struct dev_pm_ops sun6i_spi_pm_ops = {
546 .runtime_resume = sun6i_spi_runtime_resume,
547 .runtime_suspend = sun6i_spi_runtime_suspend,
548 };
549
550 static struct platform_driver sun6i_spi_driver = {
551 .probe = sun6i_spi_probe,
552 .remove = sun6i_spi_remove,
553 .driver = {
554 .name = "sun6i-spi",
555 .of_match_table = sun6i_spi_match,
556 .pm = &sun6i_spi_pm_ops,
557 },
558 };
559 module_platform_driver(sun6i_spi_driver);
560
561 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
562 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
563 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
564 MODULE_LICENSE("GPL");
565