1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
4 * (master mode only)
5 *
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/spi/spi.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/spi/spi-mem.h>
25
26 /* Generic QSPI register offsets */
27 #define GQSPI_CONFIG_OFST 0x00000100
28 #define GQSPI_ISR_OFST 0x00000104
29 #define GQSPI_IDR_OFST 0x0000010C
30 #define GQSPI_IER_OFST 0x00000108
31 #define GQSPI_IMASK_OFST 0x00000110
32 #define GQSPI_EN_OFST 0x00000114
33 #define GQSPI_TXD_OFST 0x0000011C
34 #define GQSPI_RXD_OFST 0x00000120
35 #define GQSPI_TX_THRESHOLD_OFST 0x00000128
36 #define GQSPI_RX_THRESHOLD_OFST 0x0000012C
37 #define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
38 #define GQSPI_GEN_FIFO_OFST 0x00000140
39 #define GQSPI_SEL_OFST 0x00000144
40 #define GQSPI_GF_THRESHOLD_OFST 0x00000150
41 #define GQSPI_FIFO_CTRL_OFST 0x0000014C
42 #define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
43 #define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
44 #define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808
45 #define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814
46 #define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
47 #define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C
48 #define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
49 #define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
50 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
51
52 /* GQSPI register bit masks */
53 #define GQSPI_SEL_MASK 0x00000001
54 #define GQSPI_EN_MASK 0x00000001
55 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
56 #define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002
57 #define GQSPI_IDR_ALL_MASK 0x00000FBE
58 #define GQSPI_CFG_MODE_EN_MASK 0xC0000000
59 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000
60 #define GQSPI_CFG_ENDIAN_MASK 0x04000000
61 #define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000
62 #define GQSPI_CFG_WP_HOLD_MASK 0x00080000
63 #define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038
64 #define GQSPI_CFG_CLK_PHA_MASK 0x00000004
65 #define GQSPI_CFG_CLK_POL_MASK 0x00000002
66 #define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000
67 #define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF
68 #define GQSPI_GENFIFO_DATA_XFER 0x00000100
69 #define GQSPI_GENFIFO_EXP 0x00000200
70 #define GQSPI_GENFIFO_MODE_SPI 0x00000400
71 #define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800
72 #define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00
73 #define GQSPI_GENFIFO_MODE_MASK 0x00000C00
74 #define GQSPI_GENFIFO_CS_LOWER 0x00001000
75 #define GQSPI_GENFIFO_CS_UPPER 0x00002000
76 #define GQSPI_GENFIFO_BUS_LOWER 0x00004000
77 #define GQSPI_GENFIFO_BUS_UPPER 0x00008000
78 #define GQSPI_GENFIFO_BUS_BOTH 0x0000C000
79 #define GQSPI_GENFIFO_BUS_MASK 0x0000C000
80 #define GQSPI_GENFIFO_TX 0x00010000
81 #define GQSPI_GENFIFO_RX 0x00020000
82 #define GQSPI_GENFIFO_STRIPE 0x00040000
83 #define GQSPI_GENFIFO_POLL 0x00080000
84 #define GQSPI_GENFIFO_EXP_START 0x00000100
85 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
86 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
87 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
88 #define GQSPI_ISR_RXEMPTY_MASK 0x00000800
89 #define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400
90 #define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200
91 #define GQSPI_ISR_TXEMPTY_MASK 0x00000100
92 #define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080
93 #define GQSPI_ISR_RXFULL_MASK 0x00000020
94 #define GQSPI_ISR_RXNEMPTY_MASK 0x00000010
95 #define GQSPI_ISR_TXFULL_MASK 0x00000008
96 #define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004
97 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002
98 #define GQSPI_IER_TXNOT_FULL_MASK 0x00000004
99 #define GQSPI_IER_RXEMPTY_MASK 0x00000800
100 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002
101 #define GQSPI_IER_RXNEMPTY_MASK 0x00000010
102 #define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080
103 #define GQSPI_IER_TXEMPTY_MASK 0x00000100
104 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE
105 #define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000
106 #define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000
107 #define GQSPI_ISR_IDR_MASK 0x00000994
108 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002
109 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002
110 #define GQSPI_IRQ_MASK 0x00000980
111
112 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3
113 #define GQSPI_GENFIFO_CS_SETUP 0x4
114 #define GQSPI_GENFIFO_CS_HOLD 0x3
115 #define GQSPI_TXD_DEPTH 64
116 #define GQSPI_RX_FIFO_THRESHOLD 32
117 #define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)
118 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32
119 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
120 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
121 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
122 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
123 #define GQSPI_SELECT_FLASH_CS_LOWER 0x1
124 #define GQSPI_SELECT_FLASH_CS_UPPER 0x2
125 #define GQSPI_SELECT_FLASH_CS_BOTH 0x3
126 #define GQSPI_SELECT_FLASH_BUS_LOWER 0x1
127 #define GQSPI_SELECT_FLASH_BUS_UPPER 0x2
128 #define GQSPI_SELECT_FLASH_BUS_BOTH 0x3
129 #define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
130 #define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */
131 #define GQSPI_SELECT_MODE_SPI 0x1
132 #define GQSPI_SELECT_MODE_DUALSPI 0x2
133 #define GQSPI_SELECT_MODE_QUADSPI 0x4
134 #define GQSPI_DMA_UNALIGN 0x3
135 #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
136
137 #define SPI_AUTOSUSPEND_TIMEOUT 3000
138 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
139
140 /**
141 * struct zynqmp_qspi - Defines qspi driver instance
142 * @regs: Virtual address of the QSPI controller registers
143 * @refclk: Pointer to the peripheral clock
144 * @pclk: Pointer to the APB clock
145 * @irq: IRQ number
146 * @dev: Pointer to struct device
147 * @txbuf: Pointer to the TX buffer
148 * @rxbuf: Pointer to the RX buffer
149 * @bytes_to_transfer: Number of bytes left to transfer
150 * @bytes_to_receive: Number of bytes left to receive
151 * @genfifocs: Used for chip select
152 * @genfifobus: Used to select the upper or lower bus
153 * @dma_rx_bytes: Remaining bytes to receive by DMA mode
154 * @dma_addr: DMA address after mapping the kernel buffer
155 * @genfifoentry: Used for storing the genfifoentry instruction.
156 * @mode: Defines the mode in which QSPI is operating
157 * @data_completion: completion structure
158 */
159 struct zynqmp_qspi {
160 struct spi_controller *ctlr;
161 void __iomem *regs;
162 struct clk *refclk;
163 struct clk *pclk;
164 int irq;
165 struct device *dev;
166 const void *txbuf;
167 void *rxbuf;
168 int bytes_to_transfer;
169 int bytes_to_receive;
170 u32 genfifocs;
171 u32 genfifobus;
172 u32 dma_rx_bytes;
173 dma_addr_t dma_addr;
174 u32 genfifoentry;
175 enum mode_type mode;
176 struct completion data_completion;
177 struct mutex op_lock;
178 };
179
180 /**
181 * zynqmp_gqspi_read - For GQSPI controller read operation
182 * @xqspi: Pointer to the zynqmp_qspi structure
183 * @offset: Offset from where to read
184 * Return: Value at the offset
185 */
zynqmp_gqspi_read(struct zynqmp_qspi * xqspi,u32 offset)186 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
187 {
188 return readl_relaxed(xqspi->regs + offset);
189 }
190
191 /**
192 * zynqmp_gqspi_write - For GQSPI controller write operation
193 * @xqspi: Pointer to the zynqmp_qspi structure
194 * @offset: Offset where to write
195 * @val: Value to be written
196 */
zynqmp_gqspi_write(struct zynqmp_qspi * xqspi,u32 offset,u32 val)197 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
198 u32 val)
199 {
200 writel_relaxed(val, (xqspi->regs + offset));
201 }
202
203 /**
204 * zynqmp_gqspi_selectslave - For selection of slave device
205 * @instanceptr: Pointer to the zynqmp_qspi structure
206 * @slavecs: For chip select
207 * @slavebus: To check which bus is selected- upper or lower
208 */
zynqmp_gqspi_selectslave(struct zynqmp_qspi * instanceptr,u8 slavecs,u8 slavebus)209 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
210 u8 slavecs, u8 slavebus)
211 {
212 /*
213 * Bus and CS lines selected here will be updated in the instance and
214 * used for subsequent GENFIFO entries during transfer.
215 */
216
217 /* Choose slave select line */
218 switch (slavecs) {
219 case GQSPI_SELECT_FLASH_CS_BOTH:
220 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
221 GQSPI_GENFIFO_CS_UPPER;
222 break;
223 case GQSPI_SELECT_FLASH_CS_UPPER:
224 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
225 break;
226 case GQSPI_SELECT_FLASH_CS_LOWER:
227 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
228 break;
229 default:
230 dev_warn(instanceptr->dev, "Invalid slave select\n");
231 }
232
233 /* Choose the bus */
234 switch (slavebus) {
235 case GQSPI_SELECT_FLASH_BUS_BOTH:
236 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
237 GQSPI_GENFIFO_BUS_UPPER;
238 break;
239 case GQSPI_SELECT_FLASH_BUS_UPPER:
240 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
241 break;
242 case GQSPI_SELECT_FLASH_BUS_LOWER:
243 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
244 break;
245 default:
246 dev_warn(instanceptr->dev, "Invalid slave bus\n");
247 }
248 }
249
250 /**
251 * zynqmp_qspi_init_hw - Initialize the hardware
252 * @xqspi: Pointer to the zynqmp_qspi structure
253 *
254 * The default settings of the QSPI controller's configurable parameters on
255 * reset are
256 * - Master mode
257 * - TX threshold set to 1
258 * - RX threshold set to 1
259 * - Flash memory interface mode enabled
260 * This function performs the following actions
261 * - Disable and clear all the interrupts
262 * - Enable manual slave select
263 * - Enable manual start
264 * - Deselect all the chip select lines
265 * - Set the little endian mode of TX FIFO and
266 * - Enable the QSPI controller
267 */
zynqmp_qspi_init_hw(struct zynqmp_qspi * xqspi)268 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
269 {
270 u32 config_reg;
271
272 /* Select the GQSPI mode */
273 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
274 /* Clear and disable interrupts */
275 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
276 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
277 GQSPI_ISR_WR_TO_CLR_MASK);
278 /* Clear the DMA STS */
279 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
280 zynqmp_gqspi_read(xqspi,
281 GQSPI_QSPIDMA_DST_I_STS_OFST));
282 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
283 zynqmp_gqspi_read(xqspi,
284 GQSPI_QSPIDMA_DST_STS_OFST) |
285 GQSPI_QSPIDMA_DST_STS_WTC);
286 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
287 zynqmp_gqspi_write(xqspi,
288 GQSPI_QSPIDMA_DST_I_DIS_OFST,
289 GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
290 /* Disable the GQSPI */
291 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
292 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
293 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
294 /* Manual start */
295 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
296 /* Little endian by default */
297 config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
298 /* Disable poll time out */
299 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
300 /* Set hold bit */
301 config_reg |= GQSPI_CFG_WP_HOLD_MASK;
302 /* Clear pre-scalar by default */
303 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
304 /* CPHA 0 */
305 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
306 /* CPOL 0 */
307 config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
308 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
309
310 /* Clear the TX and RX FIFO */
311 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
312 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
313 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
314 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
315 /* Set by default to allow for high frequencies */
316 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
317 zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
318 GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
319 /* Reset thresholds */
320 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
321 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
322 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
323 GQSPI_RX_FIFO_THRESHOLD);
324 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
325 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
326 zynqmp_gqspi_selectslave(xqspi,
327 GQSPI_SELECT_FLASH_CS_LOWER,
328 GQSPI_SELECT_FLASH_BUS_LOWER);
329 /* Initialize DMA */
330 zynqmp_gqspi_write(xqspi,
331 GQSPI_QSPIDMA_DST_CTRL_OFST,
332 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
333
334 /* Enable the GQSPI */
335 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
336 }
337
338 /**
339 * zynqmp_qspi_copy_read_data - Copy data to RX buffer
340 * @xqspi: Pointer to the zynqmp_qspi structure
341 * @data: The variable where data is stored
342 * @size: Number of bytes to be copied from data to RX buffer
343 */
zynqmp_qspi_copy_read_data(struct zynqmp_qspi * xqspi,ulong data,u8 size)344 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
345 ulong data, u8 size)
346 {
347 memcpy(xqspi->rxbuf, &data, size);
348 xqspi->rxbuf += size;
349 xqspi->bytes_to_receive -= size;
350 }
351
352 /**
353 * zynqmp_qspi_chipselect - Select or deselect the chip select line
354 * @qspi: Pointer to the spi_device structure
355 * @is_high: Select(0) or deselect (1) the chip select line
356 */
zynqmp_qspi_chipselect(struct spi_device * qspi,bool is_high)357 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
358 {
359 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
360 ulong timeout;
361 u32 genfifoentry = 0, statusreg;
362
363 genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
364
365 if (!is_high) {
366 xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
367 xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
368 genfifoentry |= xqspi->genfifobus;
369 genfifoentry |= xqspi->genfifocs;
370 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
371 } else {
372 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
373 }
374
375 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
376
377 /* Manually start the generic FIFO command */
378 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
379 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
380 GQSPI_CFG_START_GEN_FIFO_MASK);
381
382 timeout = jiffies + msecs_to_jiffies(1000);
383
384 /* Wait until the generic FIFO command is empty */
385 do {
386 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
387
388 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
389 (statusreg & GQSPI_ISR_TXEMPTY_MASK))
390 break;
391 cpu_relax();
392 } while (!time_after_eq(jiffies, timeout));
393
394 if (time_after_eq(jiffies, timeout))
395 dev_err(xqspi->dev, "Chip select timed out\n");
396 }
397
398 /**
399 * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
400 * @xqspi: xqspi is a pointer to the GQSPI instance
401 * @spimode: spimode - SPI or DUAL or QUAD.
402 * Return: Mask to set desired SPI mode in GENFIFO entry.
403 */
zynqmp_qspi_selectspimode(struct zynqmp_qspi * xqspi,u8 spimode)404 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
405 u8 spimode)
406 {
407 u32 mask = 0;
408
409 switch (spimode) {
410 case GQSPI_SELECT_MODE_DUALSPI:
411 mask = GQSPI_GENFIFO_MODE_DUALSPI;
412 break;
413 case GQSPI_SELECT_MODE_QUADSPI:
414 mask = GQSPI_GENFIFO_MODE_QUADSPI;
415 break;
416 case GQSPI_SELECT_MODE_SPI:
417 mask = GQSPI_GENFIFO_MODE_SPI;
418 break;
419 default:
420 dev_warn(xqspi->dev, "Invalid SPI mode\n");
421 }
422
423 return mask;
424 }
425
426 /**
427 * zynqmp_qspi_config_op - Configure QSPI controller for specified
428 * transfer
429 * @xqspi: Pointer to the zynqmp_qspi structure
430 * @qspi: Pointer to the spi_device structure
431 *
432 * Sets the operational mode of QSPI controller for the next QSPI transfer and
433 * sets the requested clock frequency.
434 *
435 * Return: Always 0
436 *
437 * Note:
438 * If the requested frequency is not an exact match with what can be
439 * obtained using the pre-scalar value, the driver sets the clock
440 * frequency which is lower than the requested frequency (maximum lower)
441 * for the transfer.
442 *
443 * If the requested frequency is higher or lower than that is supported
444 * by the QSPI controller the driver will set the highest or lowest
445 * frequency supported by controller.
446 */
zynqmp_qspi_config_op(struct zynqmp_qspi * xqspi,struct spi_device * qspi)447 static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
448 struct spi_device *qspi)
449 {
450 ulong clk_rate;
451 u32 config_reg, baud_rate_val = 0;
452
453 /* Set the clock frequency */
454 /* If req_hz == 0, default to lowest speed */
455 clk_rate = clk_get_rate(xqspi->refclk);
456
457 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
458 (clk_rate /
459 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > qspi->max_speed_hz)
460 baud_rate_val++;
461
462 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
463
464 /* Set the QSPI clock phase and clock polarity */
465 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
466
467 if (qspi->mode & SPI_CPHA)
468 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
469 if (qspi->mode & SPI_CPOL)
470 config_reg |= GQSPI_CFG_CLK_POL_MASK;
471
472 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
473 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
474 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
475 return 0;
476 }
477
478 /**
479 * zynqmp_qspi_setup_op - Configure the QSPI controller
480 * @qspi: Pointer to the spi_device structure
481 *
482 * Sets the operational mode of QSPI controller for the next QSPI transfer,
483 * baud rate and divisor value to setup the requested qspi clock.
484 *
485 * Return: 0 on success; error value otherwise.
486 */
zynqmp_qspi_setup_op(struct spi_device * qspi)487 static int zynqmp_qspi_setup_op(struct spi_device *qspi)
488 {
489 struct spi_controller *ctlr = qspi->master;
490 struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
491
492 if (ctlr->busy)
493 return -EBUSY;
494
495 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
496
497 return 0;
498 }
499
500 /**
501 * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
502 * the FIFO or the bytes required to be
503 * transmitted.
504 * @xqspi: Pointer to the zynqmp_qspi structure
505 * @size: Number of bytes to be copied from TX buffer to TX FIFO
506 */
zynqmp_qspi_filltxfifo(struct zynqmp_qspi * xqspi,int size)507 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
508 {
509 u32 count = 0, intermediate;
510
511 while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) {
512 memcpy(&intermediate, xqspi->txbuf, 4);
513 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
514
515 if (xqspi->bytes_to_transfer >= 4) {
516 xqspi->txbuf += 4;
517 xqspi->bytes_to_transfer -= 4;
518 } else {
519 xqspi->txbuf += xqspi->bytes_to_transfer;
520 xqspi->bytes_to_transfer = 0;
521 }
522 count++;
523 }
524 }
525
526 /**
527 * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
528 * the FIFO.
529 * @xqspi: Pointer to the zynqmp_qspi structure
530 * @size: Number of bytes to be copied from RX buffer to RX FIFO
531 */
zynqmp_qspi_readrxfifo(struct zynqmp_qspi * xqspi,u32 size)532 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
533 {
534 ulong data;
535 int count = 0;
536
537 while ((count < size) && (xqspi->bytes_to_receive > 0)) {
538 if (xqspi->bytes_to_receive >= 4) {
539 (*(u32 *)xqspi->rxbuf) =
540 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
541 xqspi->rxbuf += 4;
542 xqspi->bytes_to_receive -= 4;
543 count += 4;
544 } else {
545 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
546 count += xqspi->bytes_to_receive;
547 zynqmp_qspi_copy_read_data(xqspi, data,
548 xqspi->bytes_to_receive);
549 xqspi->bytes_to_receive = 0;
550 }
551 }
552 }
553
554 /**
555 * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
556 * @xqspi: Pointer to the zynqmp_qspi structure
557 * @nbits: Transfer/Receive buswidth.
558 * @genfifoentry: Variable in which GENFIFO mask is saved
559 */
zynqmp_qspi_fillgenfifo(struct zynqmp_qspi * xqspi,u8 nbits,u32 genfifoentry)560 static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
561 u32 genfifoentry)
562 {
563 u32 transfer_len = 0;
564
565 if (xqspi->txbuf) {
566 genfifoentry &= ~GQSPI_GENFIFO_RX;
567 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
568 genfifoentry |= GQSPI_GENFIFO_TX;
569 transfer_len = xqspi->bytes_to_transfer;
570 } else if (xqspi->rxbuf) {
571 genfifoentry &= ~GQSPI_GENFIFO_TX;
572 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
573 genfifoentry |= GQSPI_GENFIFO_RX;
574 if (xqspi->mode == GQSPI_MODE_DMA)
575 transfer_len = xqspi->dma_rx_bytes;
576 else
577 transfer_len = xqspi->bytes_to_receive;
578 } else {
579 /* Sending dummy circles here */
580 genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);
581 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
582 transfer_len = xqspi->bytes_to_transfer;
583 }
584 genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
585 xqspi->genfifoentry = genfifoentry;
586
587 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
588 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
589 genfifoentry |= transfer_len;
590 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
591 } else {
592 int tempcount = transfer_len;
593 u32 exponent = 8; /* 2^8 = 256 */
594 u8 imm_data = tempcount & 0xFF;
595
596 tempcount &= ~(tempcount & 0xFF);
597 /* Immediate entry */
598 if (tempcount != 0) {
599 /* Exponent entries */
600 genfifoentry |= GQSPI_GENFIFO_EXP;
601 while (tempcount != 0) {
602 if (tempcount & GQSPI_GENFIFO_EXP_START) {
603 genfifoentry &=
604 ~GQSPI_GENFIFO_IMM_DATA_MASK;
605 genfifoentry |= exponent;
606 zynqmp_gqspi_write(xqspi,
607 GQSPI_GEN_FIFO_OFST,
608 genfifoentry);
609 }
610 tempcount = tempcount >> 1;
611 exponent++;
612 }
613 }
614 if (imm_data != 0) {
615 genfifoentry &= ~GQSPI_GENFIFO_EXP;
616 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
617 genfifoentry |= (u8)(imm_data & 0xFF);
618 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
619 genfifoentry);
620 }
621 }
622 if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {
623 /* Dummy generic FIFO entry */
624 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
625 }
626 }
627
628 /**
629 * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
630 * controller
631 * @xqspi: zynqmp_qspi instance pointer
632 *
633 * This function handles DMA interrupt only.
634 */
zynqmp_process_dma_irq(struct zynqmp_qspi * xqspi)635 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
636 {
637 u32 config_reg, genfifoentry;
638
639 dma_unmap_single(xqspi->dev, xqspi->dma_addr,
640 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
641 xqspi->rxbuf += xqspi->dma_rx_bytes;
642 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
643 xqspi->dma_rx_bytes = 0;
644
645 /* Disabling the DMA interrupts */
646 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
647 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
648
649 if (xqspi->bytes_to_receive > 0) {
650 /* Switch to IO mode,for remaining bytes to receive */
651 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
652 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
653 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
654
655 /* Initiate the transfer of remaining bytes */
656 genfifoentry = xqspi->genfifoentry;
657 genfifoentry |= xqspi->bytes_to_receive;
658 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
659
660 /* Dummy generic FIFO entry */
661 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
662
663 /* Manual start */
664 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
665 (zynqmp_gqspi_read(xqspi,
666 GQSPI_CONFIG_OFST) |
667 GQSPI_CFG_START_GEN_FIFO_MASK));
668
669 /* Enable the RX interrupts for IO mode */
670 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
671 GQSPI_IER_GENFIFOEMPTY_MASK |
672 GQSPI_IER_RXNEMPTY_MASK |
673 GQSPI_IER_RXEMPTY_MASK);
674 }
675 }
676
677 /**
678 * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
679 * @irq: IRQ number
680 * @dev_id: Pointer to the xqspi structure
681 *
682 * This function handles TX empty only.
683 * On TX empty interrupt this function reads the received data from RX FIFO
684 * and fills the TX FIFO if there is any data remaining to be transferred.
685 *
686 * Return: IRQ_HANDLED when interrupt is handled
687 * IRQ_NONE otherwise.
688 */
zynqmp_qspi_irq(int irq,void * dev_id)689 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
690 {
691 struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
692 irqreturn_t ret = IRQ_NONE;
693 u32 status, mask, dma_status = 0;
694
695 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
696 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
697 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
698
699 /* Read and clear DMA status */
700 if (xqspi->mode == GQSPI_MODE_DMA) {
701 dma_status =
702 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
703 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
704 dma_status);
705 }
706
707 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
708 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
709 ret = IRQ_HANDLED;
710 }
711
712 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
713 zynqmp_process_dma_irq(xqspi);
714 ret = IRQ_HANDLED;
715 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
716 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
717 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
718 ret = IRQ_HANDLED;
719 }
720
721 if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
722 ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
723 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
724 complete(&xqspi->data_completion);
725 ret = IRQ_HANDLED;
726 }
727 return ret;
728 }
729
730 /**
731 * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
732 * @xqspi: xqspi is a pointer to the GQSPI instance.
733 */
zynqmp_qspi_setuprxdma(struct zynqmp_qspi * xqspi)734 static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
735 {
736 u32 rx_bytes, rx_rem, config_reg;
737 dma_addr_t addr;
738 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
739
740 if (xqspi->bytes_to_receive < 8 ||
741 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
742 /* Setting to IO mode */
743 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
744 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
745 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
746 xqspi->mode = GQSPI_MODE_IO;
747 xqspi->dma_rx_bytes = 0;
748 return 0;
749 }
750
751 rx_rem = xqspi->bytes_to_receive % 4;
752 rx_bytes = (xqspi->bytes_to_receive - rx_rem);
753
754 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
755 rx_bytes, DMA_FROM_DEVICE);
756 if (dma_mapping_error(xqspi->dev, addr)) {
757 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
758 return -ENOMEM;
759 }
760
761 xqspi->dma_rx_bytes = rx_bytes;
762 xqspi->dma_addr = addr;
763 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
764 (u32)(addr & 0xffffffff));
765 addr = ((addr >> 16) >> 16);
766 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
767 ((u32)addr) & 0xfff);
768
769 /* Enabling the DMA mode */
770 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
771 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
772 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
773 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
774
775 /* Switch to DMA mode */
776 xqspi->mode = GQSPI_MODE_DMA;
777
778 /* Write the number of bytes to transfer */
779 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
780
781 return 0;
782 }
783
784 /**
785 * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
786 * TX FIFO, and fills the TX FIFO with as many
787 * bytes as possible.
788 * @xqspi: Pointer to the GQSPI instance.
789 * @tx_nbits: Transfer buswidth.
790 * @genfifoentry: Variable in which GENFIFO mask is returned
791 * to calling function
792 */
zynqmp_qspi_write_op(struct zynqmp_qspi * xqspi,u8 tx_nbits,u32 genfifoentry)793 static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
794 u32 genfifoentry)
795 {
796 u32 config_reg;
797
798 zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
799 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
800 if (xqspi->mode == GQSPI_MODE_DMA) {
801 config_reg = zynqmp_gqspi_read(xqspi,
802 GQSPI_CONFIG_OFST);
803 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
804 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
805 config_reg);
806 xqspi->mode = GQSPI_MODE_IO;
807 }
808 }
809
810 /**
811 * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
812 * RX DMA operation.
813 * @xqspi: xqspi is a pointer to the GQSPI instance.
814 * @rx_nbits: Receive buswidth.
815 * @genfifoentry: genfifoentry is pointer to the variable in which
816 * GENFIFO mask is returned to calling function
817 */
zynqmp_qspi_read_op(struct zynqmp_qspi * xqspi,u8 rx_nbits,u32 genfifoentry)818 static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
819 u32 genfifoentry)
820 {
821 int ret;
822
823 ret = zynqmp_qspi_setuprxdma(xqspi);
824 if (ret)
825 return ret;
826 zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry);
827
828 return 0;
829 }
830
831 /**
832 * zynqmp_qspi_suspend - Suspend method for the QSPI driver
833 * @dev: Address of the platform_device structure
834 *
835 * This function stops the QSPI driver queue and disables the QSPI controller
836 *
837 * Return: Always 0
838 */
zynqmp_qspi_suspend(struct device * dev)839 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
840 {
841 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
842 struct spi_controller *ctlr = xqspi->ctlr;
843 int ret;
844
845 ret = spi_controller_suspend(ctlr);
846 if (ret)
847 return ret;
848
849 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
850
851 return 0;
852 }
853
854 /**
855 * zynqmp_qspi_resume - Resume method for the QSPI driver
856 * @dev: Address of the platform_device structure
857 *
858 * The function starts the QSPI driver queue and initializes the QSPI
859 * controller
860 *
861 * Return: 0 on success; error value otherwise
862 */
zynqmp_qspi_resume(struct device * dev)863 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
864 {
865 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
866 struct spi_controller *ctlr = xqspi->ctlr;
867
868 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
869
870 spi_controller_resume(ctlr);
871
872 return 0;
873 }
874
875 /**
876 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
877 * @dev: Address of the platform_device structure
878 *
879 * This function disables the clocks
880 *
881 * Return: Always 0
882 */
zynqmp_runtime_suspend(struct device * dev)883 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
884 {
885 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
886
887 clk_disable_unprepare(xqspi->refclk);
888 clk_disable_unprepare(xqspi->pclk);
889
890 return 0;
891 }
892
893 /**
894 * zynqmp_runtime_resume - Runtime resume method for the SPI driver
895 * @dev: Address of the platform_device structure
896 *
897 * This function enables the clocks
898 *
899 * Return: 0 on success and error value on error
900 */
zynqmp_runtime_resume(struct device * dev)901 static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
902 {
903 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
904 int ret;
905
906 ret = clk_prepare_enable(xqspi->pclk);
907 if (ret) {
908 dev_err(dev, "Cannot enable APB clock.\n");
909 return ret;
910 }
911
912 ret = clk_prepare_enable(xqspi->refclk);
913 if (ret) {
914 dev_err(dev, "Cannot enable device clock.\n");
915 clk_disable_unprepare(xqspi->pclk);
916 return ret;
917 }
918
919 return 0;
920 }
921
922 /**
923 * zynqmp_qspi_exec_op() - Initiates the QSPI transfer
924 * @mem: The SPI memory
925 * @op: The memory operation to execute
926 *
927 * Executes a memory operation.
928 *
929 * This function first selects the chip and starts the memory operation.
930 *
931 * Return: 0 in case of success, a negative error code otherwise.
932 */
zynqmp_qspi_exec_op(struct spi_mem * mem,const struct spi_mem_op * op)933 static int zynqmp_qspi_exec_op(struct spi_mem *mem,
934 const struct spi_mem_op *op)
935 {
936 struct zynqmp_qspi *xqspi = spi_controller_get_devdata
937 (mem->spi->master);
938 int err = 0, i;
939 u32 genfifoentry = 0;
940 u16 opcode = op->cmd.opcode;
941 u64 opaddr;
942
943 dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
944 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
945 op->dummy.buswidth, op->data.buswidth);
946
947 mutex_lock(&xqspi->op_lock);
948 zynqmp_qspi_config_op(xqspi, mem->spi);
949 zynqmp_qspi_chipselect(mem->spi, false);
950 genfifoentry |= xqspi->genfifocs;
951 genfifoentry |= xqspi->genfifobus;
952
953 if (op->cmd.opcode) {
954 reinit_completion(&xqspi->data_completion);
955 xqspi->txbuf = &opcode;
956 xqspi->rxbuf = NULL;
957 xqspi->bytes_to_transfer = op->cmd.nbytes;
958 xqspi->bytes_to_receive = 0;
959 zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);
960 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
961 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
962 GQSPI_CFG_START_GEN_FIFO_MASK);
963 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
964 GQSPI_IER_GENFIFOEMPTY_MASK |
965 GQSPI_IER_TXNOT_FULL_MASK);
966 if (!wait_for_completion_timeout
967 (&xqspi->data_completion, msecs_to_jiffies(1000))) {
968 err = -ETIMEDOUT;
969 goto return_err;
970 }
971 }
972
973 if (op->addr.nbytes) {
974 xqspi->txbuf = &opaddr;
975 for (i = 0; i < op->addr.nbytes; i++) {
976 *(((u8 *)xqspi->txbuf) + i) = op->addr.val >>
977 (8 * (op->addr.nbytes - i - 1));
978 }
979
980 reinit_completion(&xqspi->data_completion);
981 xqspi->rxbuf = NULL;
982 xqspi->bytes_to_transfer = op->addr.nbytes;
983 xqspi->bytes_to_receive = 0;
984 zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);
985 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
986 zynqmp_gqspi_read(xqspi,
987 GQSPI_CONFIG_OFST) |
988 GQSPI_CFG_START_GEN_FIFO_MASK);
989 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
990 GQSPI_IER_TXEMPTY_MASK |
991 GQSPI_IER_GENFIFOEMPTY_MASK |
992 GQSPI_IER_TXNOT_FULL_MASK);
993 if (!wait_for_completion_timeout
994 (&xqspi->data_completion, msecs_to_jiffies(1000))) {
995 err = -ETIMEDOUT;
996 goto return_err;
997 }
998 }
999
1000 if (op->dummy.nbytes) {
1001 xqspi->txbuf = NULL;
1002 xqspi->rxbuf = NULL;
1003 /*
1004 * xqspi->bytes_to_transfer here represents the dummy circles
1005 * which need to be sent.
1006 */
1007 xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth;
1008 xqspi->bytes_to_receive = 0;
1009 /*
1010 * Using op->data.buswidth instead of op->dummy.buswidth here because
1011 * we need to use it to configure the correct SPI mode.
1012 */
1013 zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1014 genfifoentry);
1015 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1016 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
1017 GQSPI_CFG_START_GEN_FIFO_MASK);
1018 }
1019
1020 if (op->data.nbytes) {
1021 reinit_completion(&xqspi->data_completion);
1022 if (op->data.dir == SPI_MEM_DATA_OUT) {
1023 xqspi->txbuf = (u8 *)op->data.buf.out;
1024 xqspi->rxbuf = NULL;
1025 xqspi->bytes_to_transfer = op->data.nbytes;
1026 xqspi->bytes_to_receive = 0;
1027 zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1028 genfifoentry);
1029 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1030 zynqmp_gqspi_read
1031 (xqspi, GQSPI_CONFIG_OFST) |
1032 GQSPI_CFG_START_GEN_FIFO_MASK);
1033 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1034 GQSPI_IER_TXEMPTY_MASK |
1035 GQSPI_IER_GENFIFOEMPTY_MASK |
1036 GQSPI_IER_TXNOT_FULL_MASK);
1037 } else {
1038 xqspi->txbuf = NULL;
1039 xqspi->rxbuf = (u8 *)op->data.buf.in;
1040 xqspi->bytes_to_receive = op->data.nbytes;
1041 xqspi->bytes_to_transfer = 0;
1042 err = zynqmp_qspi_read_op(xqspi, op->data.buswidth,
1043 genfifoentry);
1044 if (err)
1045 goto return_err;
1046
1047 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1048 zynqmp_gqspi_read
1049 (xqspi, GQSPI_CONFIG_OFST) |
1050 GQSPI_CFG_START_GEN_FIFO_MASK);
1051 if (xqspi->mode == GQSPI_MODE_DMA) {
1052 zynqmp_gqspi_write
1053 (xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,
1054 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
1055 } else {
1056 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1057 GQSPI_IER_GENFIFOEMPTY_MASK |
1058 GQSPI_IER_RXNEMPTY_MASK |
1059 GQSPI_IER_RXEMPTY_MASK);
1060 }
1061 }
1062 if (!wait_for_completion_timeout
1063 (&xqspi->data_completion, msecs_to_jiffies(1000)))
1064 err = -ETIMEDOUT;
1065 }
1066
1067 return_err:
1068
1069 zynqmp_qspi_chipselect(mem->spi, true);
1070 mutex_unlock(&xqspi->op_lock);
1071
1072 return err;
1073 }
1074
1075 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
1076 SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
1077 zynqmp_runtime_resume, NULL)
1078 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1079 };
1080
1081 static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
1082 .exec_op = zynqmp_qspi_exec_op,
1083 };
1084
1085 /**
1086 * zynqmp_qspi_probe - Probe method for the QSPI driver
1087 * @pdev: Pointer to the platform_device structure
1088 *
1089 * This function initializes the driver data structures and the hardware.
1090 *
1091 * Return: 0 on success; error value otherwise
1092 */
zynqmp_qspi_probe(struct platform_device * pdev)1093 static int zynqmp_qspi_probe(struct platform_device *pdev)
1094 {
1095 int ret = 0;
1096 struct spi_controller *ctlr;
1097 struct zynqmp_qspi *xqspi;
1098 struct device *dev = &pdev->dev;
1099 struct device_node *np = dev->of_node;
1100
1101 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1102 if (!ctlr)
1103 return -ENOMEM;
1104
1105 xqspi = spi_controller_get_devdata(ctlr);
1106 xqspi->dev = dev;
1107 xqspi->ctlr = ctlr;
1108 platform_set_drvdata(pdev, xqspi);
1109
1110 xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
1111 if (IS_ERR(xqspi->regs)) {
1112 ret = PTR_ERR(xqspi->regs);
1113 goto remove_master;
1114 }
1115
1116 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1117 if (IS_ERR(xqspi->pclk)) {
1118 dev_err(dev, "pclk clock not found.\n");
1119 ret = PTR_ERR(xqspi->pclk);
1120 goto remove_master;
1121 }
1122
1123 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1124 if (IS_ERR(xqspi->refclk)) {
1125 dev_err(dev, "ref_clk clock not found.\n");
1126 ret = PTR_ERR(xqspi->refclk);
1127 goto remove_master;
1128 }
1129
1130 ret = clk_prepare_enable(xqspi->pclk);
1131 if (ret) {
1132 dev_err(dev, "Unable to enable APB clock.\n");
1133 goto remove_master;
1134 }
1135
1136 ret = clk_prepare_enable(xqspi->refclk);
1137 if (ret) {
1138 dev_err(dev, "Unable to enable device clock.\n");
1139 goto clk_dis_pclk;
1140 }
1141
1142 init_completion(&xqspi->data_completion);
1143
1144 mutex_init(&xqspi->op_lock);
1145
1146 pm_runtime_use_autosuspend(&pdev->dev);
1147 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1148 pm_runtime_set_active(&pdev->dev);
1149 pm_runtime_enable(&pdev->dev);
1150 /* QSPI controller initializations */
1151 zynqmp_qspi_init_hw(xqspi);
1152
1153 pm_runtime_mark_last_busy(&pdev->dev);
1154 pm_runtime_put_autosuspend(&pdev->dev);
1155 xqspi->irq = platform_get_irq(pdev, 0);
1156 if (xqspi->irq <= 0) {
1157 ret = -ENXIO;
1158 goto clk_dis_all;
1159 }
1160 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1161 0, pdev->name, xqspi);
1162 if (ret != 0) {
1163 ret = -ENXIO;
1164 dev_err(dev, "request_irq failed\n");
1165 goto clk_dis_all;
1166 }
1167
1168 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1169 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1170 ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1171 ctlr->mem_ops = &zynqmp_qspi_mem_ops;
1172 ctlr->setup = zynqmp_qspi_setup_op;
1173 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1174 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1175 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1176 SPI_TX_DUAL | SPI_TX_QUAD;
1177 ctlr->dev.of_node = np;
1178
1179 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1180 if (ret) {
1181 dev_err(&pdev->dev, "spi_register_controller failed\n");
1182 goto clk_dis_all;
1183 }
1184
1185 return 0;
1186
1187 clk_dis_all:
1188 pm_runtime_set_suspended(&pdev->dev);
1189 pm_runtime_disable(&pdev->dev);
1190 clk_disable_unprepare(xqspi->refclk);
1191 clk_dis_pclk:
1192 clk_disable_unprepare(xqspi->pclk);
1193 remove_master:
1194 spi_controller_put(ctlr);
1195
1196 return ret;
1197 }
1198
1199 /**
1200 * zynqmp_qspi_remove - Remove method for the QSPI driver
1201 * @pdev: Pointer to the platform_device structure
1202 *
1203 * This function is called if a device is physically removed from the system or
1204 * if the driver module is being unloaded. It frees all resources allocated to
1205 * the device.
1206 *
1207 * Return: 0 Always
1208 */
zynqmp_qspi_remove(struct platform_device * pdev)1209 static int zynqmp_qspi_remove(struct platform_device *pdev)
1210 {
1211 struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);
1212
1213 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1214 clk_disable_unprepare(xqspi->refclk);
1215 clk_disable_unprepare(xqspi->pclk);
1216 pm_runtime_set_suspended(&pdev->dev);
1217 pm_runtime_disable(&pdev->dev);
1218
1219 return 0;
1220 }
1221
1222 static const struct of_device_id zynqmp_qspi_of_match[] = {
1223 { .compatible = "xlnx,zynqmp-qspi-1.0", },
1224 { /* End of table */ }
1225 };
1226
1227 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1228
1229 static struct platform_driver zynqmp_qspi_driver = {
1230 .probe = zynqmp_qspi_probe,
1231 .remove = zynqmp_qspi_remove,
1232 .driver = {
1233 .name = "zynqmp-qspi",
1234 .of_match_table = zynqmp_qspi_of_match,
1235 .pm = &zynqmp_qspi_dev_pm_ops,
1236 },
1237 };
1238
1239 module_platform_driver(zynqmp_qspi_driver);
1240
1241 MODULE_AUTHOR("Xilinx, Inc.");
1242 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1243 MODULE_LICENSE("GPL");
1244