1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * 8250-core based driver for the OMAP internal UART
4 *
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 *
7 * Copyright (C) 2014 Sebastian Andrzej Siewior
8 *
9 */
10
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/serial_8250.h>
16 #include <linux/serial_reg.h>
17 #include <linux/tty_flip.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/of_irq.h>
24 #include <linux/delay.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/console.h>
27 #include <linux/pm_qos.h>
28 #include <linux/pm_wakeirq.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/sys_soc.h>
31
32 #include "8250.h"
33
34 #define DEFAULT_CLK_SPEED 48000000
35
36 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
37 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
38 #define OMAP_DMA_TX_KICK (1 << 2)
39 /*
40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
41 * The same errata is applicable to AM335x and DRA7x processors too.
42 */
43 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
44 #define UART_HAS_EFR2 BIT(4)
45 #define UART_HAS_RHR_IT_DIS BIT(5)
46 #define UART_RX_TIMEOUT_QUIRK BIT(6)
47
48 #define OMAP_UART_FCR_RX_TRIG 6
49 #define OMAP_UART_FCR_TX_TRIG 4
50
51 /* SCR register bitmasks */
52 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
53 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
54 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
55 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
56 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
57 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
58
59 /* MVR register bitmasks */
60 #define OMAP_UART_MVR_SCHEME_SHIFT 30
61 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
62 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
63 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
64 #define OMAP_UART_MVR_MAJ_MASK 0x700
65 #define OMAP_UART_MVR_MAJ_SHIFT 8
66 #define OMAP_UART_MVR_MIN_MASK 0x3f
67
68 /* SYSC register bitmasks */
69 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
70
71 /* SYSS register bitmasks */
72 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
73
74 #define UART_TI752_TLR_TX 0
75 #define UART_TI752_TLR_RX 4
76
77 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
78 #define TRIGGER_FCR_MASK(x) (x & 3)
79
80 /* Enable XON/XOFF flow control on output */
81 #define OMAP_UART_SW_TX 0x08
82 /* Enable XON/XOFF flow control on input */
83 #define OMAP_UART_SW_RX 0x02
84
85 #define OMAP_UART_WER_MOD_WKUP 0x7f
86 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
87
88 #define TX_TRIGGER 1
89 #define RX_TRIGGER 48
90
91 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
92 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
93
94 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
95
96 #define OMAP_UART_REV_46 0x0406
97 #define OMAP_UART_REV_52 0x0502
98 #define OMAP_UART_REV_63 0x0603
99
100 /* Interrupt Enable Register 2 */
101 #define UART_OMAP_IER2 0x1B
102 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2)
103
104 /* Enhanced features register 2 */
105 #define UART_OMAP_EFR2 0x23
106 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6)
107
108 /* RX FIFO occupancy indicator */
109 #define UART_OMAP_RX_LVL 0x19
110
111 struct omap8250_priv {
112 int line;
113 u8 habit;
114 u8 mdr1;
115 u8 efr;
116 u8 scr;
117 u8 wer;
118 u8 xon;
119 u8 xoff;
120 u8 delayed_restore;
121 u16 quot;
122
123 u8 tx_trigger;
124 u8 rx_trigger;
125 bool is_suspending;
126 int wakeirq;
127 int wakeups_enabled;
128 u32 latency;
129 u32 calc_latency;
130 struct pm_qos_request pm_qos_request;
131 struct work_struct qos_work;
132 struct uart_8250_dma omap8250_dma;
133 spinlock_t rx_dma_lock;
134 bool rx_dma_broken;
135 bool throttled;
136 };
137
138 struct omap8250_dma_params {
139 u32 rx_size;
140 u8 rx_trigger;
141 u8 tx_trigger;
142 };
143
144 struct omap8250_platdata {
145 struct omap8250_dma_params *dma_params;
146 u8 habit;
147 };
148
149 #ifdef CONFIG_SERIAL_8250_DMA
150 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
151 #else
omap_8250_rx_dma_flush(struct uart_8250_port * p)152 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
153 #endif
154
uart_read(struct uart_8250_port * up,u32 reg)155 static u32 uart_read(struct uart_8250_port *up, u32 reg)
156 {
157 return readl(up->port.membase + (reg << up->port.regshift));
158 }
159
omap8250_set_mctrl(struct uart_port * port,unsigned int mctrl)160 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
161 {
162 struct uart_8250_port *up = up_to_u8250p(port);
163 struct omap8250_priv *priv = up->port.private_data;
164 u8 lcr;
165
166 serial8250_do_set_mctrl(port, mctrl);
167
168 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
169 /*
170 * Turn off autoRTS if RTS is lowered and restore autoRTS
171 * setting if RTS is raised
172 */
173 lcr = serial_in(up, UART_LCR);
174 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
175 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
176 priv->efr |= UART_EFR_RTS;
177 else
178 priv->efr &= ~UART_EFR_RTS;
179 serial_out(up, UART_EFR, priv->efr);
180 serial_out(up, UART_LCR, lcr);
181 }
182 }
183
184 /*
185 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
186 * The access to uart register after MDR1 Access
187 * causes UART to corrupt data.
188 *
189 * Need a delay =
190 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
191 * give 10 times as much
192 */
omap_8250_mdr1_errataset(struct uart_8250_port * up,struct omap8250_priv * priv)193 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
194 struct omap8250_priv *priv)
195 {
196 u8 timeout = 255;
197
198 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
199 udelay(2);
200 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
201 UART_FCR_CLEAR_RCVR);
202 /*
203 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
204 * TX_FIFO_E bit is 1.
205 */
206 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
207 (UART_LSR_THRE | UART_LSR_DR))) {
208 timeout--;
209 if (!timeout) {
210 /* Should *never* happen. we warn and carry on */
211 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
212 serial_in(up, UART_LSR));
213 break;
214 }
215 udelay(1);
216 }
217 }
218
omap_8250_get_divisor(struct uart_port * port,unsigned int baud,struct omap8250_priv * priv)219 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
220 struct omap8250_priv *priv)
221 {
222 unsigned int uartclk = port->uartclk;
223 unsigned int div_13, div_16;
224 unsigned int abs_d13, abs_d16;
225
226 /*
227 * Old custom speed handling.
228 */
229 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
230 priv->quot = port->custom_divisor & UART_DIV_MAX;
231 /*
232 * I assume that nobody is using this. But hey, if somebody
233 * would like to specify the divisor _and_ the mode then the
234 * driver is ready and waiting for it.
235 */
236 if (port->custom_divisor & (1 << 16))
237 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
238 else
239 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
240 return;
241 }
242 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
243 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
244
245 if (!div_13)
246 div_13 = 1;
247 if (!div_16)
248 div_16 = 1;
249
250 abs_d13 = abs(baud - uartclk / 13 / div_13);
251 abs_d16 = abs(baud - uartclk / 16 / div_16);
252
253 if (abs_d13 >= abs_d16) {
254 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
255 priv->quot = div_16;
256 } else {
257 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
258 priv->quot = div_13;
259 }
260 }
261
omap8250_update_scr(struct uart_8250_port * up,struct omap8250_priv * priv)262 static void omap8250_update_scr(struct uart_8250_port *up,
263 struct omap8250_priv *priv)
264 {
265 u8 old_scr;
266
267 old_scr = serial_in(up, UART_OMAP_SCR);
268 if (old_scr == priv->scr)
269 return;
270
271 /*
272 * The manual recommends not to enable the DMA mode selector in the SCR
273 * (instead of the FCR) register _and_ selecting the DMA mode as one
274 * register write because this may lead to malfunction.
275 */
276 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
277 serial_out(up, UART_OMAP_SCR,
278 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
279 serial_out(up, UART_OMAP_SCR, priv->scr);
280 }
281
omap8250_update_mdr1(struct uart_8250_port * up,struct omap8250_priv * priv)282 static void omap8250_update_mdr1(struct uart_8250_port *up,
283 struct omap8250_priv *priv)
284 {
285 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
286 omap_8250_mdr1_errataset(up, priv);
287 else
288 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
289 }
290
omap8250_restore_regs(struct uart_8250_port * up)291 static void omap8250_restore_regs(struct uart_8250_port *up)
292 {
293 struct omap8250_priv *priv = up->port.private_data;
294 struct uart_8250_dma *dma = up->dma;
295
296 if (dma && dma->tx_running) {
297 /*
298 * TCSANOW requests the change to occur immediately however if
299 * we have a TX-DMA operation in progress then it has been
300 * observed that it might stall and never complete. Therefore we
301 * delay DMA completes to prevent this hang from happen.
302 */
303 priv->delayed_restore = 1;
304 return;
305 }
306
307 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
308 serial_out(up, UART_EFR, UART_EFR_ECB);
309
310 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
311 serial8250_out_MCR(up, UART_MCR_TCRTLR);
312 serial_out(up, UART_FCR, up->fcr);
313
314 omap8250_update_scr(up, priv);
315
316 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
317
318 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
319 OMAP_UART_TCR_HALT(52));
320 serial_out(up, UART_TI752_TLR,
321 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
322 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
323
324 serial_out(up, UART_LCR, 0);
325
326 /* drop TCR + TLR access, we setup XON/XOFF later */
327 serial8250_out_MCR(up, up->mcr);
328 serial_out(up, UART_IER, up->ier);
329
330 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
331 serial_dl_write(up, priv->quot);
332
333 serial_out(up, UART_EFR, priv->efr);
334
335 /* Configure flow control */
336 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
337 serial_out(up, UART_XON1, priv->xon);
338 serial_out(up, UART_XOFF1, priv->xoff);
339
340 serial_out(up, UART_LCR, up->lcr);
341
342 omap8250_update_mdr1(up, priv);
343
344 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
345 }
346
347 /*
348 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
349 * some differences in how we want to handle flow control.
350 */
omap_8250_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)351 static void omap_8250_set_termios(struct uart_port *port,
352 struct ktermios *termios,
353 struct ktermios *old)
354 {
355 struct uart_8250_port *up = up_to_u8250p(port);
356 struct omap8250_priv *priv = up->port.private_data;
357 unsigned char cval = 0;
358 unsigned int baud;
359
360 switch (termios->c_cflag & CSIZE) {
361 case CS5:
362 cval = UART_LCR_WLEN5;
363 break;
364 case CS6:
365 cval = UART_LCR_WLEN6;
366 break;
367 case CS7:
368 cval = UART_LCR_WLEN7;
369 break;
370 default:
371 case CS8:
372 cval = UART_LCR_WLEN8;
373 break;
374 }
375
376 if (termios->c_cflag & CSTOPB)
377 cval |= UART_LCR_STOP;
378 if (termios->c_cflag & PARENB)
379 cval |= UART_LCR_PARITY;
380 if (!(termios->c_cflag & PARODD))
381 cval |= UART_LCR_EPAR;
382 if (termios->c_cflag & CMSPAR)
383 cval |= UART_LCR_SPAR;
384
385 /*
386 * Ask the core to calculate the divisor for us.
387 */
388 baud = uart_get_baud_rate(port, termios, old,
389 port->uartclk / 16 / UART_DIV_MAX,
390 port->uartclk / 13);
391 omap_8250_get_divisor(port, baud, priv);
392
393 /*
394 * Ok, we're now changing the port state. Do it with
395 * interrupts disabled.
396 */
397 pm_runtime_get_sync(port->dev);
398 spin_lock_irq(&port->lock);
399
400 /*
401 * Update the per-port timeout.
402 */
403 uart_update_timeout(port, termios->c_cflag, baud);
404
405 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
406 if (termios->c_iflag & INPCK)
407 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
408 if (termios->c_iflag & (IGNBRK | PARMRK))
409 up->port.read_status_mask |= UART_LSR_BI;
410
411 /*
412 * Characters to ignore
413 */
414 up->port.ignore_status_mask = 0;
415 if (termios->c_iflag & IGNPAR)
416 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
417 if (termios->c_iflag & IGNBRK) {
418 up->port.ignore_status_mask |= UART_LSR_BI;
419 /*
420 * If we're ignoring parity and break indicators,
421 * ignore overruns too (for real raw support).
422 */
423 if (termios->c_iflag & IGNPAR)
424 up->port.ignore_status_mask |= UART_LSR_OE;
425 }
426
427 /*
428 * ignore all characters if CREAD is not set
429 */
430 if ((termios->c_cflag & CREAD) == 0)
431 up->port.ignore_status_mask |= UART_LSR_DR;
432
433 /*
434 * Modem status interrupts
435 */
436 up->ier &= ~UART_IER_MSI;
437 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
438 up->ier |= UART_IER_MSI;
439
440 up->lcr = cval;
441 /* Up to here it was mostly serial8250_do_set_termios() */
442
443 /*
444 * We enable TRIG_GRANU for RX and TX and additionally we set
445 * SCR_TX_EMPTY bit. The result is the following:
446 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
447 * - less than RX_TRIGGER number of bytes will also cause an interrupt
448 * once the UART decides that there no new bytes arriving.
449 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
450 * empty - the trigger level is ignored here.
451 *
452 * Once DMA is enabled:
453 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
454 * bytes in the TX FIFO. On each assert the DMA engine will move
455 * TX_TRIGGER bytes into the FIFO.
456 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
457 * the FIFO and move RX_TRIGGER bytes.
458 * This is because threshold and trigger values are the same.
459 */
460 up->fcr = UART_FCR_ENABLE_FIFO;
461 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
462 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
463
464 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
465 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
466
467 if (up->dma)
468 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
469 OMAP_UART_SCR_DMAMODE_CTL;
470
471 priv->xon = termios->c_cc[VSTART];
472 priv->xoff = termios->c_cc[VSTOP];
473
474 priv->efr = 0;
475 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
476
477 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
478 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
479 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
480 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
481 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
482 priv->efr |= UART_EFR_CTS;
483 } else if (up->port.flags & UPF_SOFT_FLOW) {
484 /*
485 * OMAP rx s/w flow control is borked; the transmitter remains
486 * stuck off even if rx flow control is subsequently disabled
487 */
488
489 /*
490 * IXOFF Flag:
491 * Enable XON/XOFF flow control on output.
492 * Transmit XON1, XOFF1
493 */
494 if (termios->c_iflag & IXOFF) {
495 up->port.status |= UPSTAT_AUTOXOFF;
496 priv->efr |= OMAP_UART_SW_TX;
497 }
498 }
499 omap8250_restore_regs(up);
500
501 spin_unlock_irq(&up->port.lock);
502 pm_runtime_mark_last_busy(port->dev);
503 pm_runtime_put_autosuspend(port->dev);
504
505 /* calculate wakeup latency constraint */
506 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
507 priv->latency = priv->calc_latency;
508
509 schedule_work(&priv->qos_work);
510
511 /* Don't rewrite B0 */
512 if (tty_termios_baud_rate(termios))
513 tty_termios_encode_baud_rate(termios, baud, baud);
514 }
515
516 /* same as 8250 except that we may have extra flow bits set in EFR */
omap_8250_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)517 static void omap_8250_pm(struct uart_port *port, unsigned int state,
518 unsigned int oldstate)
519 {
520 struct uart_8250_port *up = up_to_u8250p(port);
521 u8 efr;
522
523 pm_runtime_get_sync(port->dev);
524 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
525 efr = serial_in(up, UART_EFR);
526 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
527 serial_out(up, UART_LCR, 0);
528
529 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
530 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
531 serial_out(up, UART_EFR, efr);
532 serial_out(up, UART_LCR, 0);
533
534 pm_runtime_mark_last_busy(port->dev);
535 pm_runtime_put_autosuspend(port->dev);
536 }
537
omap_serial_fill_features_erratas(struct uart_8250_port * up,struct omap8250_priv * priv)538 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
539 struct omap8250_priv *priv)
540 {
541 const struct soc_device_attribute k3_soc_devices[] = {
542 { .family = "AM65X", },
543 { .family = "J721E", .revision = "SR1.0" },
544 { /* sentinel */ }
545 };
546 u32 mvr, scheme;
547 u16 revision, major, minor;
548
549 mvr = uart_read(up, UART_OMAP_MVER);
550
551 /* Check revision register scheme */
552 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
553
554 switch (scheme) {
555 case 0: /* Legacy Scheme: OMAP2/3 */
556 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
557 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
558 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
559 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
560 break;
561 case 1:
562 /* New Scheme: OMAP4+ */
563 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
564 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
565 OMAP_UART_MVR_MAJ_SHIFT;
566 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
567 break;
568 default:
569 dev_warn(up->port.dev,
570 "Unknown revision, defaulting to highest\n");
571 /* highest possible revision */
572 major = 0xff;
573 minor = 0xff;
574 }
575 /* normalize revision for the driver */
576 revision = UART_BUILD_REVISION(major, minor);
577
578 switch (revision) {
579 case OMAP_UART_REV_46:
580 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
581 break;
582 case OMAP_UART_REV_52:
583 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
584 OMAP_UART_WER_HAS_TX_WAKEUP;
585 break;
586 case OMAP_UART_REV_63:
587 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
588 OMAP_UART_WER_HAS_TX_WAKEUP;
589 break;
590 default:
591 break;
592 }
593
594 /*
595 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
596 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
597 * to enable errata workaround.
598 */
599 if (soc_device_match(k3_soc_devices))
600 priv->habit &= ~UART_HAS_RHR_IT_DIS;
601 }
602
omap8250_uart_qos_work(struct work_struct * work)603 static void omap8250_uart_qos_work(struct work_struct *work)
604 {
605 struct omap8250_priv *priv;
606
607 priv = container_of(work, struct omap8250_priv, qos_work);
608 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
609 }
610
611 #ifdef CONFIG_SERIAL_8250_DMA
612 static int omap_8250_dma_handle_irq(struct uart_port *port);
613 #endif
614
omap8250_irq(int irq,void * dev_id)615 static irqreturn_t omap8250_irq(int irq, void *dev_id)
616 {
617 struct uart_port *port = dev_id;
618 struct omap8250_priv *priv = port->private_data;
619 struct uart_8250_port *up = up_to_u8250p(port);
620 unsigned int iir, lsr;
621 int ret;
622
623 #ifdef CONFIG_SERIAL_8250_DMA
624 if (up->dma) {
625 ret = omap_8250_dma_handle_irq(port);
626 return IRQ_RETVAL(ret);
627 }
628 #endif
629
630 serial8250_rpm_get(up);
631 lsr = serial_port_in(port, UART_LSR);
632 iir = serial_port_in(port, UART_IIR);
633 ret = serial8250_handle_irq(port, iir);
634
635 /*
636 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
637 * FIFO has been drained, in which case a dummy read of RX FIFO
638 * is required to clear RX TIMEOUT condition.
639 */
640 if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
641 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
642 serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
643 serial_port_in(port, UART_RX);
644 }
645
646 /* Stop processing interrupts on input overrun */
647 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
648 unsigned long delay;
649
650 up->ier = port->serial_in(port, UART_IER);
651 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
652 port->ops->stop_rx(port);
653 } else {
654 /* Keep restarting the timer until
655 * the input overrun subsides.
656 */
657 cancel_delayed_work(&up->overrun_backoff);
658 }
659
660 delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
661 schedule_delayed_work(&up->overrun_backoff, delay);
662 }
663
664 serial8250_rpm_put(up);
665
666 return IRQ_RETVAL(ret);
667 }
668
omap_8250_startup(struct uart_port * port)669 static int omap_8250_startup(struct uart_port *port)
670 {
671 struct uart_8250_port *up = up_to_u8250p(port);
672 struct omap8250_priv *priv = port->private_data;
673 int ret;
674
675 if (priv->wakeirq) {
676 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
677 if (ret)
678 return ret;
679 }
680
681 pm_runtime_get_sync(port->dev);
682
683 up->mcr = 0;
684 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
685
686 serial_out(up, UART_LCR, UART_LCR_WLEN8);
687
688 up->lsr_saved_flags = 0;
689 up->msr_saved_flags = 0;
690
691 /* Disable DMA for console UART */
692 if (uart_console(port))
693 up->dma = NULL;
694
695 if (up->dma) {
696 ret = serial8250_request_dma(up);
697 if (ret) {
698 dev_warn_ratelimited(port->dev,
699 "failed to request DMA\n");
700 up->dma = NULL;
701 }
702 }
703
704 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
705 dev_name(port->dev), port);
706 if (ret < 0)
707 goto err;
708
709 up->ier = UART_IER_RLSI | UART_IER_RDI;
710 serial_out(up, UART_IER, up->ier);
711
712 #ifdef CONFIG_PM
713 up->capabilities |= UART_CAP_RPM;
714 #endif
715
716 /* Enable module level wake up */
717 priv->wer = OMAP_UART_WER_MOD_WKUP;
718 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
719 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
720 serial_out(up, UART_OMAP_WER, priv->wer);
721
722 if (up->dma && !(priv->habit & UART_HAS_EFR2))
723 up->dma->rx_dma(up);
724
725 pm_runtime_mark_last_busy(port->dev);
726 pm_runtime_put_autosuspend(port->dev);
727 return 0;
728 err:
729 pm_runtime_mark_last_busy(port->dev);
730 pm_runtime_put_autosuspend(port->dev);
731 dev_pm_clear_wake_irq(port->dev);
732 return ret;
733 }
734
omap_8250_shutdown(struct uart_port * port)735 static void omap_8250_shutdown(struct uart_port *port)
736 {
737 struct uart_8250_port *up = up_to_u8250p(port);
738 struct omap8250_priv *priv = port->private_data;
739
740 flush_work(&priv->qos_work);
741 if (up->dma)
742 omap_8250_rx_dma_flush(up);
743
744 pm_runtime_get_sync(port->dev);
745
746 serial_out(up, UART_OMAP_WER, 0);
747 if (priv->habit & UART_HAS_EFR2)
748 serial_out(up, UART_OMAP_EFR2, 0x0);
749
750 up->ier = 0;
751 serial_out(up, UART_IER, 0);
752
753 if (up->dma)
754 serial8250_release_dma(up);
755
756 /*
757 * Disable break condition and FIFOs
758 */
759 if (up->lcr & UART_LCR_SBC)
760 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
761 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
762
763 pm_runtime_mark_last_busy(port->dev);
764 pm_runtime_put_autosuspend(port->dev);
765 free_irq(port->irq, port);
766 dev_pm_clear_wake_irq(port->dev);
767 }
768
omap_8250_throttle(struct uart_port * port)769 static void omap_8250_throttle(struct uart_port *port)
770 {
771 struct omap8250_priv *priv = port->private_data;
772 unsigned long flags;
773
774 pm_runtime_get_sync(port->dev);
775
776 spin_lock_irqsave(&port->lock, flags);
777 port->ops->stop_rx(port);
778 priv->throttled = true;
779 spin_unlock_irqrestore(&port->lock, flags);
780
781 pm_runtime_mark_last_busy(port->dev);
782 pm_runtime_put_autosuspend(port->dev);
783 }
784
omap_8250_unthrottle(struct uart_port * port)785 static void omap_8250_unthrottle(struct uart_port *port)
786 {
787 struct omap8250_priv *priv = port->private_data;
788 struct uart_8250_port *up = up_to_u8250p(port);
789 unsigned long flags;
790
791 pm_runtime_get_sync(port->dev);
792
793 spin_lock_irqsave(&port->lock, flags);
794 priv->throttled = false;
795 if (up->dma)
796 up->dma->rx_dma(up);
797 up->ier |= UART_IER_RLSI | UART_IER_RDI;
798 port->read_status_mask |= UART_LSR_DR;
799 serial_out(up, UART_IER, up->ier);
800 spin_unlock_irqrestore(&port->lock, flags);
801
802 pm_runtime_mark_last_busy(port->dev);
803 pm_runtime_put_autosuspend(port->dev);
804 }
805
806 #ifdef CONFIG_SERIAL_8250_DMA
807 static int omap_8250_rx_dma(struct uart_8250_port *p);
808
809 /* Must be called while priv->rx_dma_lock is held */
__dma_rx_do_complete(struct uart_8250_port * p)810 static void __dma_rx_do_complete(struct uart_8250_port *p)
811 {
812 struct uart_8250_dma *dma = p->dma;
813 struct tty_port *tty_port = &p->port.state->port;
814 struct omap8250_priv *priv = p->port.private_data;
815 struct dma_chan *rxchan = dma->rxchan;
816 dma_cookie_t cookie;
817 struct dma_tx_state state;
818 int count;
819 int ret;
820 u32 reg;
821
822 if (!dma->rx_running)
823 goto out;
824
825 cookie = dma->rx_cookie;
826 dma->rx_running = 0;
827
828 /* Re-enable RX FIFO interrupt now that transfer is complete */
829 if (priv->habit & UART_HAS_RHR_IT_DIS) {
830 reg = serial_in(p, UART_OMAP_IER2);
831 reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
832 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
833 }
834
835 dmaengine_tx_status(rxchan, cookie, &state);
836
837 count = dma->rx_size - state.residue + state.in_flight_bytes;
838 if (count < dma->rx_size) {
839 dmaengine_terminate_async(rxchan);
840
841 /*
842 * Poll for teardown to complete which guarantees in
843 * flight data is drained.
844 */
845 if (state.in_flight_bytes) {
846 int poll_count = 25;
847
848 while (dmaengine_tx_status(rxchan, cookie, NULL) &&
849 poll_count--)
850 cpu_relax();
851
852 if (poll_count == -1)
853 dev_err(p->port.dev, "teardown incomplete\n");
854 }
855 }
856 if (!count)
857 goto out;
858 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
859
860 p->port.icount.rx += ret;
861 p->port.icount.buf_overrun += count - ret;
862 out:
863
864 tty_flip_buffer_push(tty_port);
865 }
866
__dma_rx_complete(void * param)867 static void __dma_rx_complete(void *param)
868 {
869 struct uart_8250_port *p = param;
870 struct omap8250_priv *priv = p->port.private_data;
871 struct uart_8250_dma *dma = p->dma;
872 struct dma_tx_state state;
873 unsigned long flags;
874
875 spin_lock_irqsave(&p->port.lock, flags);
876
877 /*
878 * If the tx status is not DMA_COMPLETE, then this is a delayed
879 * completion callback. A previous RX timeout flush would have
880 * already pushed the data, so exit.
881 */
882 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
883 DMA_COMPLETE) {
884 spin_unlock_irqrestore(&p->port.lock, flags);
885 return;
886 }
887 __dma_rx_do_complete(p);
888 if (!priv->throttled) {
889 p->ier |= UART_IER_RLSI | UART_IER_RDI;
890 serial_out(p, UART_IER, p->ier);
891 if (!(priv->habit & UART_HAS_EFR2))
892 omap_8250_rx_dma(p);
893 }
894
895 spin_unlock_irqrestore(&p->port.lock, flags);
896 }
897
omap_8250_rx_dma_flush(struct uart_8250_port * p)898 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
899 {
900 struct omap8250_priv *priv = p->port.private_data;
901 struct uart_8250_dma *dma = p->dma;
902 struct dma_tx_state state;
903 unsigned long flags;
904 int ret;
905
906 spin_lock_irqsave(&priv->rx_dma_lock, flags);
907
908 if (!dma->rx_running) {
909 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
910 return;
911 }
912
913 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
914 if (ret == DMA_IN_PROGRESS) {
915 ret = dmaengine_pause(dma->rxchan);
916 if (WARN_ON_ONCE(ret))
917 priv->rx_dma_broken = true;
918 }
919 __dma_rx_do_complete(p);
920 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
921 }
922
omap_8250_rx_dma(struct uart_8250_port * p)923 static int omap_8250_rx_dma(struct uart_8250_port *p)
924 {
925 struct omap8250_priv *priv = p->port.private_data;
926 struct uart_8250_dma *dma = p->dma;
927 int err = 0;
928 struct dma_async_tx_descriptor *desc;
929 unsigned long flags;
930 u32 reg;
931
932 if (priv->rx_dma_broken)
933 return -EINVAL;
934
935 spin_lock_irqsave(&priv->rx_dma_lock, flags);
936
937 if (dma->rx_running) {
938 enum dma_status state;
939
940 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
941 if (state == DMA_COMPLETE) {
942 /*
943 * Disable RX interrupts to allow RX DMA completion
944 * callback to run.
945 */
946 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
947 serial_out(p, UART_IER, p->ier);
948 }
949 goto out;
950 }
951
952 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
953 dma->rx_size, DMA_DEV_TO_MEM,
954 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
955 if (!desc) {
956 err = -EBUSY;
957 goto out;
958 }
959
960 dma->rx_running = 1;
961 desc->callback = __dma_rx_complete;
962 desc->callback_param = p;
963
964 dma->rx_cookie = dmaengine_submit(desc);
965
966 /*
967 * Disable RX FIFO interrupt while RX DMA is enabled, else
968 * spurious interrupt may be raised when data is in the RX FIFO
969 * but is yet to be drained by DMA.
970 */
971 if (priv->habit & UART_HAS_RHR_IT_DIS) {
972 reg = serial_in(p, UART_OMAP_IER2);
973 reg |= UART_OMAP_IER2_RHR_IT_DIS;
974 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
975 }
976
977 dma_async_issue_pending(dma->rxchan);
978 out:
979 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
980 return err;
981 }
982
983 static int omap_8250_tx_dma(struct uart_8250_port *p);
984
omap_8250_dma_tx_complete(void * param)985 static void omap_8250_dma_tx_complete(void *param)
986 {
987 struct uart_8250_port *p = param;
988 struct uart_8250_dma *dma = p->dma;
989 struct circ_buf *xmit = &p->port.state->xmit;
990 unsigned long flags;
991 bool en_thri = false;
992 struct omap8250_priv *priv = p->port.private_data;
993
994 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
995 UART_XMIT_SIZE, DMA_TO_DEVICE);
996
997 spin_lock_irqsave(&p->port.lock, flags);
998
999 dma->tx_running = 0;
1000
1001 xmit->tail += dma->tx_size;
1002 xmit->tail &= UART_XMIT_SIZE - 1;
1003 p->port.icount.tx += dma->tx_size;
1004
1005 if (priv->delayed_restore) {
1006 priv->delayed_restore = 0;
1007 omap8250_restore_regs(p);
1008 }
1009
1010 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1011 uart_write_wakeup(&p->port);
1012
1013 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
1014 int ret;
1015
1016 ret = omap_8250_tx_dma(p);
1017 if (ret)
1018 en_thri = true;
1019 } else if (p->capabilities & UART_CAP_RPM) {
1020 en_thri = true;
1021 }
1022
1023 if (en_thri) {
1024 dma->tx_err = 1;
1025 serial8250_set_THRI(p);
1026 }
1027
1028 spin_unlock_irqrestore(&p->port.lock, flags);
1029 }
1030
omap_8250_tx_dma(struct uart_8250_port * p)1031 static int omap_8250_tx_dma(struct uart_8250_port *p)
1032 {
1033 struct uart_8250_dma *dma = p->dma;
1034 struct omap8250_priv *priv = p->port.private_data;
1035 struct circ_buf *xmit = &p->port.state->xmit;
1036 struct dma_async_tx_descriptor *desc;
1037 unsigned int skip_byte = 0;
1038 int ret;
1039
1040 if (dma->tx_running)
1041 return 0;
1042 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
1043
1044 /*
1045 * Even if no data, we need to return an error for the two cases
1046 * below so serial8250_tx_chars() is invoked and properly clears
1047 * THRI and/or runtime suspend.
1048 */
1049 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1050 ret = -EBUSY;
1051 goto err;
1052 }
1053 serial8250_clear_THRI(p);
1054 return 0;
1055 }
1056
1057 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1058 if (priv->habit & OMAP_DMA_TX_KICK) {
1059 u8 tx_lvl;
1060
1061 /*
1062 * We need to put the first byte into the FIFO in order to start
1063 * the DMA transfer. For transfers smaller than four bytes we
1064 * don't bother doing DMA at all. It seem not matter if there
1065 * are still bytes in the FIFO from the last transfer (in case
1066 * we got here directly from omap_8250_dma_tx_complete()). Bytes
1067 * leaving the FIFO seem not to trigger the DMA transfer. It is
1068 * really the byte that we put into the FIFO.
1069 * If the FIFO is already full then we most likely got here from
1070 * omap_8250_dma_tx_complete(). And this means the DMA engine
1071 * just completed its work. We don't have to wait the complete
1072 * 86us at 115200,8n1 but around 60us (not to mention lower
1073 * baudrates). So in that case we take the interrupt and try
1074 * again with an empty FIFO.
1075 */
1076 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
1077 if (tx_lvl == p->tx_loadsz) {
1078 ret = -EBUSY;
1079 goto err;
1080 }
1081 if (dma->tx_size < 4) {
1082 ret = -EINVAL;
1083 goto err;
1084 }
1085 skip_byte = 1;
1086 }
1087
1088 desc = dmaengine_prep_slave_single(dma->txchan,
1089 dma->tx_addr + xmit->tail + skip_byte,
1090 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1091 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1092 if (!desc) {
1093 ret = -EBUSY;
1094 goto err;
1095 }
1096
1097 dma->tx_running = 1;
1098
1099 desc->callback = omap_8250_dma_tx_complete;
1100 desc->callback_param = p;
1101
1102 dma->tx_cookie = dmaengine_submit(desc);
1103
1104 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1105 UART_XMIT_SIZE, DMA_TO_DEVICE);
1106
1107 dma_async_issue_pending(dma->txchan);
1108 if (dma->tx_err)
1109 dma->tx_err = 0;
1110
1111 serial8250_clear_THRI(p);
1112 if (skip_byte)
1113 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1114 return 0;
1115 err:
1116 dma->tx_err = 1;
1117 return ret;
1118 }
1119
handle_rx_dma(struct uart_8250_port * up,unsigned int iir)1120 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1121 {
1122 switch (iir & 0x3f) {
1123 case UART_IIR_RLSI:
1124 case UART_IIR_RX_TIMEOUT:
1125 case UART_IIR_RDI:
1126 omap_8250_rx_dma_flush(up);
1127 return true;
1128 }
1129 return omap_8250_rx_dma(up);
1130 }
1131
omap_8250_handle_rx_dma(struct uart_8250_port * up,u8 iir,unsigned char status)1132 static unsigned char omap_8250_handle_rx_dma(struct uart_8250_port *up,
1133 u8 iir, unsigned char status)
1134 {
1135 if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1136 (iir & UART_IIR_RDI)) {
1137 if (handle_rx_dma(up, iir)) {
1138 status = serial8250_rx_chars(up, status);
1139 omap_8250_rx_dma(up);
1140 }
1141 }
1142
1143 return status;
1144 }
1145
am654_8250_handle_rx_dma(struct uart_8250_port * up,u8 iir,unsigned char status)1146 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
1147 unsigned char status)
1148 {
1149 /*
1150 * Queue a new transfer if FIFO has data.
1151 */
1152 if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1153 (up->ier & UART_IER_RDI)) {
1154 omap_8250_rx_dma(up);
1155 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1156 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
1157 /*
1158 * Disable RX timeout, read IIR to clear
1159 * current timeout condition, clear EFR2 to
1160 * periodic timeouts, re-enable interrupts.
1161 */
1162 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1163 serial_out(up, UART_IER, up->ier);
1164 omap_8250_rx_dma_flush(up);
1165 serial_in(up, UART_IIR);
1166 serial_out(up, UART_OMAP_EFR2, 0x0);
1167 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1168 serial_out(up, UART_IER, up->ier);
1169 }
1170 }
1171
1172 /*
1173 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1174 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1175 * use the default routine in the non-DMA case and this one for with DMA.
1176 */
omap_8250_dma_handle_irq(struct uart_port * port)1177 static int omap_8250_dma_handle_irq(struct uart_port *port)
1178 {
1179 struct uart_8250_port *up = up_to_u8250p(port);
1180 struct omap8250_priv *priv = up->port.private_data;
1181 unsigned char status;
1182 unsigned long flags;
1183 u8 iir;
1184
1185 serial8250_rpm_get(up);
1186
1187 iir = serial_port_in(port, UART_IIR);
1188 if (iir & UART_IIR_NO_INT) {
1189 serial8250_rpm_put(up);
1190 return IRQ_HANDLED;
1191 }
1192
1193 spin_lock_irqsave(&port->lock, flags);
1194
1195 status = serial_port_in(port, UART_LSR);
1196
1197 if (priv->habit & UART_HAS_EFR2)
1198 am654_8250_handle_rx_dma(up, iir, status);
1199 else
1200 status = omap_8250_handle_rx_dma(up, iir, status);
1201
1202 serial8250_modem_status(up);
1203 if (status & UART_LSR_THRE && up->dma->tx_err) {
1204 if (uart_tx_stopped(&up->port) ||
1205 uart_circ_empty(&up->port.state->xmit)) {
1206 up->dma->tx_err = 0;
1207 serial8250_tx_chars(up);
1208 } else {
1209 /*
1210 * try again due to an earlier failer which
1211 * might have been resolved by now.
1212 */
1213 if (omap_8250_tx_dma(up))
1214 serial8250_tx_chars(up);
1215 }
1216 }
1217
1218 uart_unlock_and_check_sysrq(port, flags);
1219 serial8250_rpm_put(up);
1220 return 1;
1221 }
1222
the_no_dma_filter_fn(struct dma_chan * chan,void * param)1223 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1224 {
1225 return false;
1226 }
1227
1228 #else
1229
omap_8250_rx_dma(struct uart_8250_port * p)1230 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1231 {
1232 return -EINVAL;
1233 }
1234 #endif
1235
omap8250_no_handle_irq(struct uart_port * port)1236 static int omap8250_no_handle_irq(struct uart_port *port)
1237 {
1238 /* IRQ has not been requested but handling irq? */
1239 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1240 return 0;
1241 }
1242
1243 static struct omap8250_dma_params am654_dma = {
1244 .rx_size = SZ_2K,
1245 .rx_trigger = 1,
1246 .tx_trigger = TX_TRIGGER,
1247 };
1248
1249 static struct omap8250_dma_params am33xx_dma = {
1250 .rx_size = RX_TRIGGER,
1251 .rx_trigger = RX_TRIGGER,
1252 .tx_trigger = TX_TRIGGER,
1253 };
1254
1255 static struct omap8250_platdata am654_platdata = {
1256 .dma_params = &am654_dma,
1257 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
1258 UART_RX_TIMEOUT_QUIRK,
1259 };
1260
1261 static struct omap8250_platdata am33xx_platdata = {
1262 .dma_params = &am33xx_dma,
1263 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
1264 };
1265
1266 static struct omap8250_platdata omap4_platdata = {
1267 .dma_params = &am33xx_dma,
1268 .habit = UART_ERRATA_CLOCK_DISABLE,
1269 };
1270
1271 static const struct of_device_id omap8250_dt_ids[] = {
1272 { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1273 { .compatible = "ti,omap2-uart" },
1274 { .compatible = "ti,omap3-uart" },
1275 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1276 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1277 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1278 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1279 {},
1280 };
1281 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1282
omap8250_probe(struct platform_device * pdev)1283 static int omap8250_probe(struct platform_device *pdev)
1284 {
1285 struct device_node *np = pdev->dev.of_node;
1286 struct omap8250_priv *priv;
1287 const struct omap8250_platdata *pdata;
1288 struct uart_8250_port up;
1289 struct resource *regs;
1290 void __iomem *membase;
1291 int irq, ret;
1292
1293 irq = platform_get_irq(pdev, 0);
1294 if (irq < 0)
1295 return irq;
1296
1297 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1298 if (!regs) {
1299 dev_err(&pdev->dev, "missing registers\n");
1300 return -EINVAL;
1301 }
1302
1303 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1304 if (!priv)
1305 return -ENOMEM;
1306
1307 membase = devm_ioremap(&pdev->dev, regs->start,
1308 resource_size(regs));
1309 if (!membase)
1310 return -ENODEV;
1311
1312 memset(&up, 0, sizeof(up));
1313 up.port.dev = &pdev->dev;
1314 up.port.mapbase = regs->start;
1315 up.port.membase = membase;
1316 up.port.irq = irq;
1317 /*
1318 * It claims to be 16C750 compatible however it is a little different.
1319 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1320 * have) is enabled via EFR instead of MCR. The type is set here 8250
1321 * just to get things going. UNKNOWN does not work for a few reasons and
1322 * we don't need our own type since we don't use 8250's set_termios()
1323 * or pm callback.
1324 */
1325 up.port.type = PORT_8250;
1326 up.port.iotype = UPIO_MEM;
1327 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1328 UPF_HARD_FLOW;
1329 up.port.private_data = priv;
1330
1331 up.port.regshift = 2;
1332 up.port.fifosize = 64;
1333 up.tx_loadsz = 64;
1334 up.capabilities = UART_CAP_FIFO;
1335 #ifdef CONFIG_PM
1336 /*
1337 * Runtime PM is mostly transparent. However to do it right we need to a
1338 * TX empty interrupt before we can put the device to auto idle. So if
1339 * PM is not enabled we don't add that flag and can spare that one extra
1340 * interrupt in the TX path.
1341 */
1342 up.capabilities |= UART_CAP_RPM;
1343 #endif
1344 up.port.set_termios = omap_8250_set_termios;
1345 up.port.set_mctrl = omap8250_set_mctrl;
1346 up.port.pm = omap_8250_pm;
1347 up.port.startup = omap_8250_startup;
1348 up.port.shutdown = omap_8250_shutdown;
1349 up.port.throttle = omap_8250_throttle;
1350 up.port.unthrottle = omap_8250_unthrottle;
1351 up.port.rs485_config = serial8250_em485_config;
1352 up.rs485_start_tx = serial8250_em485_start_tx;
1353 up.rs485_stop_tx = serial8250_em485_stop_tx;
1354 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1355
1356 ret = of_alias_get_id(np, "serial");
1357 if (ret < 0) {
1358 dev_err(&pdev->dev, "failed to get alias\n");
1359 return ret;
1360 }
1361 up.port.line = ret;
1362
1363 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1364 struct clk *clk;
1365
1366 clk = devm_clk_get(&pdev->dev, NULL);
1367 if (IS_ERR(clk)) {
1368 if (PTR_ERR(clk) == -EPROBE_DEFER)
1369 return -EPROBE_DEFER;
1370 } else {
1371 up.port.uartclk = clk_get_rate(clk);
1372 }
1373 }
1374
1375 if (of_property_read_u32(np, "overrun-throttle-ms",
1376 &up.overrun_backoff_time_ms) != 0)
1377 up.overrun_backoff_time_ms = 0;
1378
1379 priv->wakeirq = irq_of_parse_and_map(np, 1);
1380
1381 pdata = of_device_get_match_data(&pdev->dev);
1382 if (pdata)
1383 priv->habit |= pdata->habit;
1384
1385 if (!up.port.uartclk) {
1386 up.port.uartclk = DEFAULT_CLK_SPEED;
1387 dev_warn(&pdev->dev,
1388 "No clock speed specified: using default: %d\n",
1389 DEFAULT_CLK_SPEED);
1390 }
1391
1392 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1393 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1394 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1395 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1396
1397 spin_lock_init(&priv->rx_dma_lock);
1398
1399 device_init_wakeup(&pdev->dev, true);
1400 pm_runtime_enable(&pdev->dev);
1401 pm_runtime_use_autosuspend(&pdev->dev);
1402
1403 /*
1404 * Disable runtime PM until autosuspend delay unless specifically
1405 * enabled by the user via sysfs. This is the historic way to
1406 * prevent an unsafe default policy with lossy characters on wake-up.
1407 * For serdev devices this is not needed, the policy can be managed by
1408 * the serdev driver.
1409 */
1410 if (!of_get_available_child_count(pdev->dev.of_node))
1411 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1412
1413 pm_runtime_irq_safe(&pdev->dev);
1414
1415 pm_runtime_get_sync(&pdev->dev);
1416
1417 omap_serial_fill_features_erratas(&up, priv);
1418 up.port.handle_irq = omap8250_no_handle_irq;
1419 priv->rx_trigger = RX_TRIGGER;
1420 priv->tx_trigger = TX_TRIGGER;
1421 #ifdef CONFIG_SERIAL_8250_DMA
1422 /*
1423 * Oh DMA support. If there are no DMA properties in the DT then
1424 * we will fall back to a generic DMA channel which does not
1425 * really work here. To ensure that we do not get a generic DMA
1426 * channel assigned, we have the the_no_dma_filter_fn() here.
1427 * To avoid "failed to request DMA" messages we check for DMA
1428 * properties in DT.
1429 */
1430 ret = of_property_count_strings(np, "dma-names");
1431 if (ret == 2) {
1432 struct omap8250_dma_params *dma_params = NULL;
1433
1434 up.dma = &priv->omap8250_dma;
1435 up.dma->fn = the_no_dma_filter_fn;
1436 up.dma->tx_dma = omap_8250_tx_dma;
1437 up.dma->rx_dma = omap_8250_rx_dma;
1438 if (pdata)
1439 dma_params = pdata->dma_params;
1440
1441 if (dma_params) {
1442 up.dma->rx_size = dma_params->rx_size;
1443 up.dma->rxconf.src_maxburst = dma_params->rx_trigger;
1444 up.dma->txconf.dst_maxburst = dma_params->tx_trigger;
1445 priv->rx_trigger = dma_params->rx_trigger;
1446 priv->tx_trigger = dma_params->tx_trigger;
1447 } else {
1448 up.dma->rx_size = RX_TRIGGER;
1449 up.dma->rxconf.src_maxburst = RX_TRIGGER;
1450 up.dma->txconf.dst_maxburst = TX_TRIGGER;
1451 }
1452 }
1453 #endif
1454 ret = serial8250_register_8250_port(&up);
1455 if (ret < 0) {
1456 dev_err(&pdev->dev, "unable to register 8250 port\n");
1457 goto err;
1458 }
1459 priv->line = ret;
1460 platform_set_drvdata(pdev, priv);
1461 pm_runtime_mark_last_busy(&pdev->dev);
1462 pm_runtime_put_autosuspend(&pdev->dev);
1463 return 0;
1464 err:
1465 pm_runtime_dont_use_autosuspend(&pdev->dev);
1466 pm_runtime_put_sync(&pdev->dev);
1467 pm_runtime_disable(&pdev->dev);
1468 return ret;
1469 }
1470
omap8250_remove(struct platform_device * pdev)1471 static int omap8250_remove(struct platform_device *pdev)
1472 {
1473 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1474
1475 pm_runtime_dont_use_autosuspend(&pdev->dev);
1476 pm_runtime_put_sync(&pdev->dev);
1477 pm_runtime_disable(&pdev->dev);
1478 serial8250_unregister_port(priv->line);
1479 cpu_latency_qos_remove_request(&priv->pm_qos_request);
1480 device_init_wakeup(&pdev->dev, false);
1481 return 0;
1482 }
1483
1484 #ifdef CONFIG_PM_SLEEP
omap8250_prepare(struct device * dev)1485 static int omap8250_prepare(struct device *dev)
1486 {
1487 struct omap8250_priv *priv = dev_get_drvdata(dev);
1488
1489 if (!priv)
1490 return 0;
1491 priv->is_suspending = true;
1492 return 0;
1493 }
1494
omap8250_complete(struct device * dev)1495 static void omap8250_complete(struct device *dev)
1496 {
1497 struct omap8250_priv *priv = dev_get_drvdata(dev);
1498
1499 if (!priv)
1500 return;
1501 priv->is_suspending = false;
1502 }
1503
omap8250_suspend(struct device * dev)1504 static int omap8250_suspend(struct device *dev)
1505 {
1506 struct omap8250_priv *priv = dev_get_drvdata(dev);
1507 struct uart_8250_port *up = serial8250_get_port(priv->line);
1508
1509 serial8250_suspend_port(priv->line);
1510
1511 pm_runtime_get_sync(dev);
1512 if (!device_may_wakeup(dev))
1513 priv->wer = 0;
1514 serial_out(up, UART_OMAP_WER, priv->wer);
1515 pm_runtime_mark_last_busy(dev);
1516 pm_runtime_put_autosuspend(dev);
1517
1518 flush_work(&priv->qos_work);
1519 return 0;
1520 }
1521
omap8250_resume(struct device * dev)1522 static int omap8250_resume(struct device *dev)
1523 {
1524 struct omap8250_priv *priv = dev_get_drvdata(dev);
1525
1526 serial8250_resume_port(priv->line);
1527 return 0;
1528 }
1529 #else
1530 #define omap8250_prepare NULL
1531 #define omap8250_complete NULL
1532 #endif
1533
1534 #ifdef CONFIG_PM
omap8250_lost_context(struct uart_8250_port * up)1535 static int omap8250_lost_context(struct uart_8250_port *up)
1536 {
1537 u32 val;
1538
1539 val = serial_in(up, UART_OMAP_SCR);
1540 /*
1541 * If we lose context, then SCR is set to its reset value of zero.
1542 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1543 * among other bits, to never set the register back to zero again.
1544 */
1545 if (!val)
1546 return 1;
1547 return 0;
1548 }
1549
1550 /* TODO: in future, this should happen via API in drivers/reset/ */
omap8250_soft_reset(struct device * dev)1551 static int omap8250_soft_reset(struct device *dev)
1552 {
1553 struct omap8250_priv *priv = dev_get_drvdata(dev);
1554 struct uart_8250_port *up = serial8250_get_port(priv->line);
1555 int timeout = 100;
1556 int sysc;
1557 int syss;
1558
1559 /*
1560 * At least on omap4, unused uarts may not idle after reset without
1561 * a basic scr dma configuration even with no dma in use. The
1562 * module clkctrl status bits will be 1 instead of 3 blocking idle
1563 * for the whole clockdomain. The softreset below will clear scr,
1564 * and we restore it on resume so this is safe to do on all SoCs
1565 * needing omap8250_soft_reset() quirk. Do it in two writes as
1566 * recommended in the comment for omap8250_update_scr().
1567 */
1568 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1569 serial_out(up, UART_OMAP_SCR,
1570 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1571
1572 sysc = serial_in(up, UART_OMAP_SYSC);
1573
1574 /* softreset the UART */
1575 sysc |= OMAP_UART_SYSC_SOFTRESET;
1576 serial_out(up, UART_OMAP_SYSC, sysc);
1577
1578 /* By experiments, 1us enough for reset complete on AM335x */
1579 do {
1580 udelay(1);
1581 syss = serial_in(up, UART_OMAP_SYSS);
1582 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1583
1584 if (!timeout) {
1585 dev_err(dev, "timed out waiting for reset done\n");
1586 return -ETIMEDOUT;
1587 }
1588
1589 return 0;
1590 }
1591
omap8250_runtime_suspend(struct device * dev)1592 static int omap8250_runtime_suspend(struct device *dev)
1593 {
1594 struct omap8250_priv *priv = dev_get_drvdata(dev);
1595 struct uart_8250_port *up;
1596
1597 /* In case runtime-pm tries this before we are setup */
1598 if (!priv)
1599 return 0;
1600
1601 up = serial8250_get_port(priv->line);
1602 /*
1603 * When using 'no_console_suspend', the console UART must not be
1604 * suspended. Since driver suspend is managed by runtime suspend,
1605 * preventing runtime suspend (by returning error) will keep device
1606 * active during suspend.
1607 */
1608 if (priv->is_suspending && !console_suspend_enabled) {
1609 if (uart_console(&up->port))
1610 return -EBUSY;
1611 }
1612
1613 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1614 int ret;
1615
1616 ret = omap8250_soft_reset(dev);
1617 if (ret)
1618 return ret;
1619
1620 /* Restore to UART mode after reset (for wakeup) */
1621 omap8250_update_mdr1(up, priv);
1622 /* Restore wakeup enable register */
1623 serial_out(up, UART_OMAP_WER, priv->wer);
1624 }
1625
1626 if (up->dma && up->dma->rxchan)
1627 omap_8250_rx_dma_flush(up);
1628
1629 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1630 schedule_work(&priv->qos_work);
1631
1632 return 0;
1633 }
1634
omap8250_runtime_resume(struct device * dev)1635 static int omap8250_runtime_resume(struct device *dev)
1636 {
1637 struct omap8250_priv *priv = dev_get_drvdata(dev);
1638 struct uart_8250_port *up;
1639
1640 /* In case runtime-pm tries this before we are setup */
1641 if (!priv)
1642 return 0;
1643
1644 up = serial8250_get_port(priv->line);
1645
1646 if (omap8250_lost_context(up))
1647 omap8250_restore_regs(up);
1648
1649 if (up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2))
1650 omap_8250_rx_dma(up);
1651
1652 priv->latency = priv->calc_latency;
1653 schedule_work(&priv->qos_work);
1654 return 0;
1655 }
1656 #endif
1657
1658 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
omap8250_console_fixup(void)1659 static int __init omap8250_console_fixup(void)
1660 {
1661 char *omap_str;
1662 char *options;
1663 u8 idx;
1664
1665 if (strstr(boot_command_line, "console=ttyS"))
1666 /* user set a ttyS based name for the console */
1667 return 0;
1668
1669 omap_str = strstr(boot_command_line, "console=ttyO");
1670 if (!omap_str)
1671 /* user did not set ttyO based console, so we don't care */
1672 return 0;
1673
1674 omap_str += 12;
1675 if ('0' <= *omap_str && *omap_str <= '9')
1676 idx = *omap_str - '0';
1677 else
1678 return 0;
1679
1680 omap_str++;
1681 if (omap_str[0] == ',') {
1682 omap_str++;
1683 options = omap_str;
1684 } else {
1685 options = NULL;
1686 }
1687
1688 add_preferred_console("ttyS", idx, options);
1689 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1690 idx, idx);
1691 pr_err("This ensures that you still see kernel messages. Please\n");
1692 pr_err("update your kernel commandline.\n");
1693 return 0;
1694 }
1695 console_initcall(omap8250_console_fixup);
1696 #endif
1697
1698 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1699 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1700 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1701 omap8250_runtime_resume, NULL)
1702 .prepare = omap8250_prepare,
1703 .complete = omap8250_complete,
1704 };
1705
1706 static struct platform_driver omap8250_platform_driver = {
1707 .driver = {
1708 .name = "omap8250",
1709 .pm = &omap8250_dev_pm_ops,
1710 .of_match_table = omap8250_dt_ids,
1711 },
1712 .probe = omap8250_probe,
1713 .remove = omap8250_remove,
1714 };
1715 module_platform_driver(omap8250_platform_driver);
1716
1717 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1718 MODULE_DESCRIPTION("OMAP 8250 Driver");
1719 MODULE_LICENSE("GPL v2");
1720