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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
4  *
5  * Copyright (c) 2000-2004 by David Brownell
6  */
7 
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/usb.h>
12 #include <linux/usb/hcd.h>
13 
14 #include "ehci.h"
15 #include "pci-quirks.h"
16 
17 #define DRIVER_DESC "EHCI PCI platform driver"
18 
19 static const char hcd_name[] = "ehci-pci";
20 
21 /* defined here to avoid adding to pci_ids.h for single instance use */
22 #define PCI_DEVICE_ID_INTEL_CE4100_USB	0x2e70
23 
24 /*-------------------------------------------------------------------------*/
25 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC		0x0939
is_intel_quark_x1000(struct pci_dev * pdev)26 static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
27 {
28 	return pdev->vendor == PCI_VENDOR_ID_INTEL &&
29 		pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
30 }
31 
32 /*
33  * This is the list of PCI IDs for the devices that have EHCI USB class and
34  * specific drivers for that. One of the example is a ChipIdea device installed
35  * on some Intel MID platforms.
36  */
37 static const struct pci_device_id bypass_pci_id_table[] = {
38 	/* ChipIdea on Intel MID platform */
39 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), },
40 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), },
41 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), },
42 	{}
43 };
44 
is_bypassed_id(struct pci_dev * pdev)45 static inline bool is_bypassed_id(struct pci_dev *pdev)
46 {
47 	return !!pci_match_id(bypass_pci_id_table, pdev);
48 }
49 
50 /*
51  * 0x84 is the offset of in/out threshold register,
52  * and it is the same offset as the register of 'hostpc'.
53  */
54 #define	intel_quark_x1000_insnreg01	hostpc
55 
56 /* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
57 #define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD	0x007f007f
58 
59 /* called after powerup, by probe or system-pm "wakeup" */
ehci_pci_reinit(struct ehci_hcd * ehci,struct pci_dev * pdev)60 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
61 {
62 	int			retval;
63 
64 	/* we expect static quirk code to handle the "extended capabilities"
65 	 * (currently just BIOS handoff) allowed starting with EHCI 0.96
66 	 */
67 
68 	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
69 	retval = pci_set_mwi(pdev);
70 	if (!retval)
71 		ehci_dbg(ehci, "MWI active\n");
72 
73 	/* Reset the threshold limit */
74 	if (is_intel_quark_x1000(pdev)) {
75 		/*
76 		 * For the Intel QUARK X1000, raise the I/O threshold to the
77 		 * maximum usable value in order to improve performance.
78 		 */
79 		ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
80 			ehci->regs->intel_quark_x1000_insnreg01);
81 	}
82 
83 	return 0;
84 }
85 
86 /* called during probe() after chip reset completes */
ehci_pci_setup(struct usb_hcd * hcd)87 static int ehci_pci_setup(struct usb_hcd *hcd)
88 {
89 	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
90 	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
91 	u32			temp;
92 	int			retval;
93 
94 	ehci->caps = hcd->regs;
95 
96 	/*
97 	 * ehci_init() causes memory for DMA transfers to be
98 	 * allocated.  Thus, any vendor-specific workarounds based on
99 	 * limiting the type of memory used for DMA transfers must
100 	 * happen before ehci_setup() is called.
101 	 *
102 	 * Most other workarounds can be done either before or after
103 	 * init and reset; they are located here too.
104 	 */
105 	switch (pdev->vendor) {
106 	case PCI_VENDOR_ID_TOSHIBA_2:
107 		/* celleb's companion chip */
108 		if (pdev->device == 0x01b5) {
109 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
110 			ehci->big_endian_mmio = 1;
111 #else
112 			ehci_warn(ehci,
113 				  "unsupported big endian Toshiba quirk\n");
114 #endif
115 		}
116 		break;
117 	case PCI_VENDOR_ID_NVIDIA:
118 		/* NVidia reports that certain chips don't handle
119 		 * QH, ITD, or SITD addresses above 2GB.  (But TD,
120 		 * data buffer, and periodic schedule are normal.)
121 		 */
122 		switch (pdev->device) {
123 		case 0x003c:	/* MCP04 */
124 		case 0x005b:	/* CK804 */
125 		case 0x00d8:	/* CK8 */
126 		case 0x00e8:	/* CK8S */
127 			if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(31)) < 0)
128 				ehci_warn(ehci, "can't enable NVidia "
129 					"workaround for >2GB RAM\n");
130 			break;
131 
132 		/* Some NForce2 chips have problems with selective suspend;
133 		 * fixed in newer silicon.
134 		 */
135 		case 0x0068:
136 			if (pdev->revision < 0xa4)
137 				ehci->no_selective_suspend = 1;
138 			break;
139 		}
140 		break;
141 	case PCI_VENDOR_ID_INTEL:
142 		if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
143 			hcd->has_tt = 1;
144 		break;
145 	case PCI_VENDOR_ID_TDI:
146 		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
147 			hcd->has_tt = 1;
148 		break;
149 	case PCI_VENDOR_ID_AMD:
150 		/* AMD PLL quirk */
151 		if (usb_amd_quirk_pll_check())
152 			ehci->amd_pll_fix = 1;
153 		/* AMD8111 EHCI doesn't work, according to AMD errata */
154 		if (pdev->device == 0x7463) {
155 			ehci_info(ehci, "ignoring AMD8111 (errata)\n");
156 			retval = -EIO;
157 			goto done;
158 		}
159 
160 		/*
161 		 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
162 		 * read/write memory space which does not belong to it when
163 		 * there is NULL pointer with T-bit set to 1 in the frame list
164 		 * table. To avoid the issue, the frame list link pointer
165 		 * should always contain a valid pointer to a inactive qh.
166 		 */
167 		if (pdev->device == 0x7808) {
168 			ehci->use_dummy_qh = 1;
169 			ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
170 		}
171 		break;
172 	case PCI_VENDOR_ID_VIA:
173 		if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
174 			u8 tmp;
175 
176 			/* The VT6212 defaults to a 1 usec EHCI sleep time which
177 			 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
178 			 * that sleep time use the conventional 10 usec.
179 			 */
180 			pci_read_config_byte(pdev, 0x4b, &tmp);
181 			if (tmp & 0x20)
182 				break;
183 			pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
184 		}
185 		break;
186 	case PCI_VENDOR_ID_ATI:
187 		/* AMD PLL quirk */
188 		if (usb_amd_quirk_pll_check())
189 			ehci->amd_pll_fix = 1;
190 
191 		/*
192 		 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
193 		 * read/write memory space which does not belong to it when
194 		 * there is NULL pointer with T-bit set to 1 in the frame list
195 		 * table. To avoid the issue, the frame list link pointer
196 		 * should always contain a valid pointer to a inactive qh.
197 		 */
198 		if (pdev->device == 0x4396) {
199 			ehci->use_dummy_qh = 1;
200 			ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
201 		}
202 		/* SB600 and old version of SB700 have a bug in EHCI controller,
203 		 * which causes usb devices lose response in some cases.
204 		 */
205 		if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&
206 				usb_amd_hang_symptom_quirk()) {
207 			u8 tmp;
208 			ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
209 			pci_read_config_byte(pdev, 0x53, &tmp);
210 			pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
211 		}
212 		break;
213 	case PCI_VENDOR_ID_NETMOS:
214 		/* MosChip frame-index-register bug */
215 		ehci_info(ehci, "applying MosChip frame-index workaround\n");
216 		ehci->frame_index_bug = 1;
217 		break;
218 	case PCI_VENDOR_ID_HUAWEI:
219 		/* Synopsys HC bug */
220 		if (pdev->device == 0xa239) {
221 			ehci_info(ehci, "applying Synopsys HC workaround\n");
222 			ehci->has_synopsys_hc_bug = 1;
223 		}
224 		break;
225 	}
226 
227 	/* optional debug port, normally in the first BAR */
228 	temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
229 	if (temp) {
230 		pci_read_config_dword(pdev, temp, &temp);
231 		temp >>= 16;
232 		if (((temp >> 13) & 7) == 1) {
233 			u32 hcs_params = ehci_readl(ehci,
234 						    &ehci->caps->hcs_params);
235 
236 			temp &= 0x1fff;
237 			ehci->debug = hcd->regs + temp;
238 			temp = ehci_readl(ehci, &ehci->debug->control);
239 			ehci_info(ehci, "debug port %d%s\n",
240 				  HCS_DEBUG_PORT(hcs_params),
241 				  (temp & DBGP_ENABLED) ? " IN USE" : "");
242 			if (!(temp & DBGP_ENABLED))
243 				ehci->debug = NULL;
244 		}
245 	}
246 
247 	retval = ehci_setup(hcd);
248 	if (retval)
249 		return retval;
250 
251 	/* These workarounds need to be applied after ehci_setup() */
252 	switch (pdev->vendor) {
253 	case PCI_VENDOR_ID_NEC:
254 	case PCI_VENDOR_ID_INTEL:
255 	case PCI_VENDOR_ID_AMD:
256 		ehci->need_io_watchdog = 0;
257 		break;
258 	case PCI_VENDOR_ID_NVIDIA:
259 		switch (pdev->device) {
260 		/* MCP89 chips on the MacBookAir3,1 give EPROTO when
261 		 * fetching device descriptors unless LPM is disabled.
262 		 * There are also intermittent problems enumerating
263 		 * devices with PPCD enabled.
264 		 */
265 		case 0x0d9d:
266 			ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
267 			ehci->has_ppcd = 0;
268 			ehci->command &= ~CMD_PPCEE;
269 			break;
270 		}
271 		break;
272 	}
273 
274 	/* at least the Genesys GL880S needs fixup here */
275 	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
276 	temp &= 0x0f;
277 	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
278 		ehci_dbg(ehci, "bogus port configuration: "
279 			"cc=%d x pcc=%d < ports=%d\n",
280 			HCS_N_CC(ehci->hcs_params),
281 			HCS_N_PCC(ehci->hcs_params),
282 			HCS_N_PORTS(ehci->hcs_params));
283 
284 		switch (pdev->vendor) {
285 		case 0x17a0:		/* GENESYS */
286 			/* GL880S: should be PORTS=2 */
287 			temp |= (ehci->hcs_params & ~0xf);
288 			ehci->hcs_params = temp;
289 			break;
290 		case PCI_VENDOR_ID_NVIDIA:
291 			/* NF4: should be PCC=10 */
292 			break;
293 		}
294 	}
295 
296 	/* Serial Bus Release Number is at PCI 0x60 offset */
297 	if (pdev->vendor == PCI_VENDOR_ID_STMICRO
298 	    && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
299 		;	/* ConneXT has no sbrn register */
300 	else if (pdev->vendor == PCI_VENDOR_ID_HUAWEI
301 			 && pdev->device == 0xa239)
302 		;	/* HUAWEI Kunpeng920 USB EHCI has no sbrn register */
303 	else
304 		pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
305 
306 	/* Keep this around for a while just in case some EHCI
307 	 * implementation uses legacy PCI PM support.  This test
308 	 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
309 	 * been triggered by then.
310 	 */
311 	if (!device_can_wakeup(&pdev->dev)) {
312 		u16	port_wake;
313 
314 		pci_read_config_word(pdev, 0x62, &port_wake);
315 		if (port_wake & 0x0001) {
316 			dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
317 			device_set_wakeup_capable(&pdev->dev, 1);
318 		}
319 	}
320 
321 #ifdef	CONFIG_PM
322 	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
323 		ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
324 #endif
325 
326 	retval = ehci_pci_reinit(ehci, pdev);
327 done:
328 	return retval;
329 }
330 
331 /*-------------------------------------------------------------------------*/
332 
333 #ifdef	CONFIG_PM
334 
335 /* suspend/resume, section 4.3 */
336 
337 /* These routines rely on the PCI bus glue
338  * to handle powerdown and wakeup, and currently also on
339  * transceivers that don't need any software attention to set up
340  * the right sort of wakeup.
341  * Also they depend on separate root hub suspend/resume.
342  */
343 
ehci_pci_resume(struct usb_hcd * hcd,bool hibernated)344 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
345 {
346 	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
347 	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
348 
349 	if (ehci_resume(hcd, hibernated) != 0)
350 		(void) ehci_pci_reinit(ehci, pdev);
351 	return 0;
352 }
353 
354 #else
355 
356 #define ehci_suspend		NULL
357 #define ehci_pci_resume		NULL
358 #endif	/* CONFIG_PM */
359 
360 static struct hc_driver __read_mostly ehci_pci_hc_driver;
361 
362 static const struct ehci_driver_overrides pci_overrides __initconst = {
363 	.reset =		ehci_pci_setup,
364 };
365 
366 /*-------------------------------------------------------------------------*/
367 
ehci_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)368 static int ehci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
369 {
370 	if (is_bypassed_id(pdev))
371 		return -ENODEV;
372 	return usb_hcd_pci_probe(pdev, id, &ehci_pci_hc_driver);
373 }
374 
ehci_pci_remove(struct pci_dev * pdev)375 static void ehci_pci_remove(struct pci_dev *pdev)
376 {
377 	pci_clear_mwi(pdev);
378 	usb_hcd_pci_remove(pdev);
379 }
380 
381 /* PCI driver selection metadata; PCI hotplugging uses this */
382 static const struct pci_device_id pci_ids [] = { {
383 	/* handle any USB 2.0 EHCI controller */
384 	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
385 	}, {
386 	PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
387 	},
388 	{ /* end: all zeroes */ }
389 };
390 MODULE_DEVICE_TABLE(pci, pci_ids);
391 
392 /* pci driver glue; this is a "new style" PCI driver module */
393 static struct pci_driver ehci_pci_driver = {
394 	.name =		hcd_name,
395 	.id_table =	pci_ids,
396 
397 	.probe =	ehci_pci_probe,
398 	.remove =	ehci_pci_remove,
399 	.shutdown = 	usb_hcd_pci_shutdown,
400 
401 #ifdef CONFIG_PM
402 	.driver =	{
403 		.pm =	&usb_hcd_pci_pm_ops
404 	},
405 #endif
406 };
407 
ehci_pci_init(void)408 static int __init ehci_pci_init(void)
409 {
410 	if (usb_disabled())
411 		return -ENODEV;
412 
413 	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
414 
415 	ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
416 
417 	/* Entries for the PCI suspend/resume callbacks are special */
418 	ehci_pci_hc_driver.pci_suspend = ehci_suspend;
419 	ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
420 
421 	return pci_register_driver(&ehci_pci_driver);
422 }
423 module_init(ehci_pci_init);
424 
ehci_pci_cleanup(void)425 static void __exit ehci_pci_cleanup(void)
426 {
427 	pci_unregister_driver(&ehci_pci_driver);
428 }
429 module_exit(ehci_pci_cleanup);
430 
431 MODULE_DESCRIPTION(DRIVER_DESC);
432 MODULE_AUTHOR("David Brownell");
433 MODULE_AUTHOR("Alan Stern");
434 MODULE_LICENSE("GPL");
435