1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author:
5 * Zhigang.Wei <zhigang.wei@mediatek.com>
6 * Chunfeng.Yun <chunfeng.yun@mediatek.com>
7 */
8
9 #ifndef _XHCI_MTK_H_
10 #define _XHCI_MTK_H_
11
12 #include "xhci.h"
13
14 /**
15 * To simplify scheduler algorithm, set a upper limit for ESIT,
16 * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
17 * round down to the limit value, that means allocating more
18 * bandwidth to it.
19 */
20 #define XHCI_MTK_MAX_ESIT 64
21
22 /**
23 * @ss_bit_map: used to avoid start split microframes overlay
24 * @fs_bus_bw: array to keep track of bandwidth already used for FS
25 * @ep_list: Endpoints using this TT
26 * @usb_tt: usb TT related
27 * @tt_port: TT port number
28 */
29 struct mu3h_sch_tt {
30 DECLARE_BITMAP(ss_bit_map, XHCI_MTK_MAX_ESIT);
31 u32 fs_bus_bw[XHCI_MTK_MAX_ESIT];
32 struct list_head ep_list;
33 struct usb_tt *usb_tt;
34 int tt_port;
35 };
36
37 /**
38 * struct mu3h_sch_bw_info: schedule information for bandwidth domain
39 *
40 * @bus_bw: array to keep track of bandwidth already used at each uframes
41 * @bw_ep_list: eps in the bandwidth domain
42 *
43 * treat a HS root port as a bandwidth domain, but treat a SS root port as
44 * two bandwidth domains, one for IN eps and another for OUT eps.
45 */
46 struct mu3h_sch_bw_info {
47 u32 bus_bw[XHCI_MTK_MAX_ESIT];
48 struct list_head bw_ep_list;
49 };
50
51 /**
52 * struct mu3h_sch_ep_info: schedule information for endpoint
53 *
54 * @esit: unit is 125us, equal to 2 << Interval field in ep-context
55 * @num_budget_microframes: number of continuous uframes
56 * (@repeat==1) scheduled within the interval
57 * @bw_cost_per_microframe: bandwidth cost per microframe
58 * @endpoint: linked into bandwidth domain which it belongs to
59 * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
60 * @sch_tt: mu3h_sch_tt linked into
61 * @ep_type: endpoint type
62 * @maxpkt: max packet size of endpoint
63 * @ep: address of usb_host_endpoint struct
64 * @allocated: the bandwidth is aready allocated from bus_bw
65 * @offset: which uframe of the interval that transfer should be
66 * scheduled first time within the interval
67 * @repeat: the time gap between two uframes that transfers are
68 * scheduled within a interval. in the simple algorithm, only
69 * assign 0 or 1 to it; 0 means using only one uframe in a
70 * interval, and 1 means using @num_budget_microframes
71 * continuous uframes
72 * @pkts: number of packets to be transferred in the scheduled uframes
73 * @cs_count: number of CS that host will trigger
74 * @burst_mode: burst mode for scheduling. 0: normal burst mode,
75 * distribute the bMaxBurst+1 packets for a single burst
76 * according to @pkts and @repeat, repeate the burst multiple
77 * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
78 * according to @pkts and @repeat. normal mode is used by
79 * default
80 * @bw_budget_table: table to record bandwidth budget per microframe
81 */
82 struct mu3h_sch_ep_info {
83 u32 esit;
84 u32 num_budget_microframes;
85 u32 bw_cost_per_microframe;
86 struct list_head endpoint;
87 struct list_head tt_endpoint;
88 struct mu3h_sch_tt *sch_tt;
89 u32 ep_type;
90 u32 maxpkt;
91 void *ep;
92 bool allocated;
93 /*
94 * mtk xHCI scheduling information put into reserved DWs
95 * in ep context
96 */
97 u32 offset;
98 u32 repeat;
99 u32 pkts;
100 u32 cs_count;
101 u32 burst_mode;
102 u32 bw_budget_table[];
103 };
104
105 #define MU3C_U3_PORT_MAX 4
106 #define MU3C_U2_PORT_MAX 5
107
108 /**
109 * struct mu3c_ippc_regs: MTK ssusb ip port control registers
110 * @ip_pw_ctr0~3: ip power and clock control registers
111 * @ip_pw_sts1~2: ip power and clock status registers
112 * @ip_xhci_cap: ip xHCI capability register
113 * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
114 * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
115 * @u2_phy_pll: usb2 phy pll control register
116 */
117 struct mu3c_ippc_regs {
118 __le32 ip_pw_ctr0;
119 __le32 ip_pw_ctr1;
120 __le32 ip_pw_ctr2;
121 __le32 ip_pw_ctr3;
122 __le32 ip_pw_sts1;
123 __le32 ip_pw_sts2;
124 __le32 reserved0[3];
125 __le32 ip_xhci_cap;
126 __le32 reserved1[2];
127 __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
128 __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
129 __le32 reserved2;
130 __le32 u2_phy_pll;
131 __le32 reserved3[33]; /* 0x80 ~ 0xff */
132 };
133
134 struct xhci_hcd_mtk {
135 struct device *dev;
136 struct usb_hcd *hcd;
137 struct mu3h_sch_bw_info *sch_array;
138 struct list_head bw_ep_chk_list;
139 struct mu3c_ippc_regs __iomem *ippc_regs;
140 bool has_ippc;
141 int num_u2_ports;
142 int num_u3_ports;
143 int u3p_dis_msk;
144 struct regulator *vusb33;
145 struct regulator *vbus;
146 struct clk *sys_clk; /* sys and mac clock */
147 struct clk *xhci_clk;
148 struct clk *ref_clk;
149 struct clk *mcu_clk;
150 struct clk *dma_clk;
151 struct regmap *pericfg;
152 struct phy **phys;
153 int num_phys;
154 bool lpm_support;
155 bool u2_lpm_disable;
156 /* usb remote wakeup */
157 bool uwk_en;
158 struct regmap *uwk;
159 u32 uwk_reg_base;
160 u32 uwk_vers;
161 };
162
hcd_to_mtk(struct usb_hcd * hcd)163 static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
164 {
165 return dev_get_drvdata(hcd->self.controller);
166 }
167
168 #if IS_ENABLED(CONFIG_USB_XHCI_MTK)
169 int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
170 void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
171 int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
172 struct usb_host_endpoint *ep);
173 void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
174 struct usb_host_endpoint *ep);
175 int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
176 void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
177
178 #else
xhci_mtk_add_ep_quirk(struct usb_hcd * hcd,struct usb_device * udev,struct usb_host_endpoint * ep)179 static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
180 struct usb_device *udev, struct usb_host_endpoint *ep)
181 {
182 return 0;
183 }
184
xhci_mtk_drop_ep_quirk(struct usb_hcd * hcd,struct usb_device * udev,struct usb_host_endpoint * ep)185 static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
186 struct usb_device *udev, struct usb_host_endpoint *ep)
187 {
188 }
189
xhci_mtk_check_bandwidth(struct usb_hcd * hcd,struct usb_device * udev)190 static inline int xhci_mtk_check_bandwidth(struct usb_hcd *hcd,
191 struct usb_device *udev)
192 {
193 return 0;
194 }
195
xhci_mtk_reset_bandwidth(struct usb_hcd * hcd,struct usb_device * udev)196 static inline void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd,
197 struct usb_device *udev)
198 {
199 }
200 #endif
201
202 #endif /* _XHCI_MTK_H_ */
203