1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Ingenic SoCs USB PHY driver
4 * Copyright (c) Paul Cercueil <paul@crapouillou.net>
5 * Copyright (c) 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
6 * Copyright (c) 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/usb/otg.h>
15 #include <linux/usb/phy.h>
16
17 /* OTGPHY register offsets */
18 #define REG_USBPCR_OFFSET 0x00
19 #define REG_USBRDT_OFFSET 0x04
20 #define REG_USBVBFIL_OFFSET 0x08
21 #define REG_USBPCR1_OFFSET 0x0c
22
23 /* bits within the USBPCR register */
24 #define USBPCR_USB_MODE BIT(31)
25 #define USBPCR_AVLD_REG BIT(30)
26 #define USBPCR_COMMONONN BIT(25)
27 #define USBPCR_VBUSVLDEXT BIT(24)
28 #define USBPCR_VBUSVLDEXTSEL BIT(23)
29 #define USBPCR_POR BIT(22)
30 #define USBPCR_SIDDQ BIT(21)
31 #define USBPCR_OTG_DISABLE BIT(20)
32 #define USBPCR_TXPREEMPHTUNE BIT(6)
33
34 #define USBPCR_IDPULLUP_LSB 28
35 #define USBPCR_IDPULLUP_MASK GENMASK(29, USBPCR_IDPULLUP_LSB)
36 #define USBPCR_IDPULLUP_ALWAYS (0x2 << USBPCR_IDPULLUP_LSB)
37 #define USBPCR_IDPULLUP_SUSPEND (0x1 << USBPCR_IDPULLUP_LSB)
38 #define USBPCR_IDPULLUP_OTG (0x0 << USBPCR_IDPULLUP_LSB)
39
40 #define USBPCR_COMPDISTUNE_LSB 17
41 #define USBPCR_COMPDISTUNE_MASK GENMASK(19, USBPCR_COMPDISTUNE_LSB)
42 #define USBPCR_COMPDISTUNE_DFT (0x4 << USBPCR_COMPDISTUNE_LSB)
43
44 #define USBPCR_OTGTUNE_LSB 14
45 #define USBPCR_OTGTUNE_MASK GENMASK(16, USBPCR_OTGTUNE_LSB)
46 #define USBPCR_OTGTUNE_DFT (0x4 << USBPCR_OTGTUNE_LSB)
47
48 #define USBPCR_SQRXTUNE_LSB 11
49 #define USBPCR_SQRXTUNE_MASK GENMASK(13, USBPCR_SQRXTUNE_LSB)
50 #define USBPCR_SQRXTUNE_DCR_20PCT (0x7 << USBPCR_SQRXTUNE_LSB)
51 #define USBPCR_SQRXTUNE_DFT (0x3 << USBPCR_SQRXTUNE_LSB)
52
53 #define USBPCR_TXFSLSTUNE_LSB 7
54 #define USBPCR_TXFSLSTUNE_MASK GENMASK(10, USBPCR_TXFSLSTUNE_LSB)
55 #define USBPCR_TXFSLSTUNE_DCR_50PPT (0xf << USBPCR_TXFSLSTUNE_LSB)
56 #define USBPCR_TXFSLSTUNE_DCR_25PPT (0x7 << USBPCR_TXFSLSTUNE_LSB)
57 #define USBPCR_TXFSLSTUNE_DFT (0x3 << USBPCR_TXFSLSTUNE_LSB)
58 #define USBPCR_TXFSLSTUNE_INC_25PPT (0x1 << USBPCR_TXFSLSTUNE_LSB)
59 #define USBPCR_TXFSLSTUNE_INC_50PPT (0x0 << USBPCR_TXFSLSTUNE_LSB)
60
61 #define USBPCR_TXHSXVTUNE_LSB 4
62 #define USBPCR_TXHSXVTUNE_MASK GENMASK(5, USBPCR_TXHSXVTUNE_LSB)
63 #define USBPCR_TXHSXVTUNE_DFT (0x3 << USBPCR_TXHSXVTUNE_LSB)
64 #define USBPCR_TXHSXVTUNE_DCR_15MV (0x1 << USBPCR_TXHSXVTUNE_LSB)
65
66 #define USBPCR_TXRISETUNE_LSB 4
67 #define USBPCR_TXRISETUNE_MASK GENMASK(5, USBPCR_TXRISETUNE_LSB)
68 #define USBPCR_TXRISETUNE_DFT (0x3 << USBPCR_TXRISETUNE_LSB)
69
70 #define USBPCR_TXVREFTUNE_LSB 0
71 #define USBPCR_TXVREFTUNE_MASK GENMASK(3, USBPCR_TXVREFTUNE_LSB)
72 #define USBPCR_TXVREFTUNE_INC_25PPT (0x7 << USBPCR_TXVREFTUNE_LSB)
73 #define USBPCR_TXVREFTUNE_DFT (0x5 << USBPCR_TXVREFTUNE_LSB)
74
75 /* bits within the USBRDTR register */
76 #define USBRDT_UTMI_RST BIT(27)
77 #define USBRDT_HB_MASK BIT(26)
78 #define USBRDT_VBFIL_LD_EN BIT(25)
79 #define USBRDT_IDDIG_EN BIT(24)
80 #define USBRDT_IDDIG_REG BIT(23)
81 #define USBRDT_VBFIL_EN BIT(2)
82
83 /* bits within the USBPCR1 register */
84 #define USBPCR1_BVLD_REG BIT(31)
85 #define USBPCR1_DPPD BIT(29)
86 #define USBPCR1_DMPD BIT(28)
87 #define USBPCR1_USB_SEL BIT(28)
88 #define USBPCR1_WORD_IF_16BIT BIT(19)
89
90 enum ingenic_usb_phy_version {
91 ID_JZ4770,
92 ID_JZ4780,
93 ID_X1000,
94 ID_X1830,
95 };
96
97 struct ingenic_soc_info {
98 enum ingenic_usb_phy_version version;
99
100 void (*usb_phy_init)(struct usb_phy *phy);
101 };
102
103 struct jz4770_phy {
104 const struct ingenic_soc_info *soc_info;
105
106 struct usb_phy phy;
107 struct usb_otg otg;
108 struct device *dev;
109 void __iomem *base;
110 struct clk *clk;
111 struct regulator *vcc_supply;
112 };
113
otg_to_jz4770_phy(struct usb_otg * otg)114 static inline struct jz4770_phy *otg_to_jz4770_phy(struct usb_otg *otg)
115 {
116 return container_of(otg, struct jz4770_phy, otg);
117 }
118
phy_to_jz4770_phy(struct usb_phy * phy)119 static inline struct jz4770_phy *phy_to_jz4770_phy(struct usb_phy *phy)
120 {
121 return container_of(phy, struct jz4770_phy, phy);
122 }
123
ingenic_usb_phy_set_peripheral(struct usb_otg * otg,struct usb_gadget * gadget)124 static int ingenic_usb_phy_set_peripheral(struct usb_otg *otg,
125 struct usb_gadget *gadget)
126 {
127 struct jz4770_phy *priv = otg_to_jz4770_phy(otg);
128 u32 reg;
129
130 if (priv->soc_info->version >= ID_X1000) {
131 reg = readl(priv->base + REG_USBPCR1_OFFSET);
132 reg |= USBPCR1_BVLD_REG;
133 writel(reg, priv->base + REG_USBPCR1_OFFSET);
134 }
135
136 reg = readl(priv->base + REG_USBPCR_OFFSET);
137 reg &= ~USBPCR_USB_MODE;
138 reg |= USBPCR_VBUSVLDEXT | USBPCR_VBUSVLDEXTSEL | USBPCR_OTG_DISABLE;
139 writel(reg, priv->base + REG_USBPCR_OFFSET);
140
141 return 0;
142 }
143
ingenic_usb_phy_set_host(struct usb_otg * otg,struct usb_bus * host)144 static int ingenic_usb_phy_set_host(struct usb_otg *otg, struct usb_bus *host)
145 {
146 struct jz4770_phy *priv = otg_to_jz4770_phy(otg);
147 u32 reg;
148
149 reg = readl(priv->base + REG_USBPCR_OFFSET);
150 reg &= ~(USBPCR_VBUSVLDEXT | USBPCR_VBUSVLDEXTSEL | USBPCR_OTG_DISABLE);
151 reg |= USBPCR_USB_MODE;
152 writel(reg, priv->base + REG_USBPCR_OFFSET);
153
154 return 0;
155 }
156
ingenic_usb_phy_init(struct usb_phy * phy)157 static int ingenic_usb_phy_init(struct usb_phy *phy)
158 {
159 struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
160 int err;
161 u32 reg;
162
163 err = regulator_enable(priv->vcc_supply);
164 if (err) {
165 dev_err(priv->dev, "Unable to enable VCC: %d\n", err);
166 return err;
167 }
168
169 err = clk_prepare_enable(priv->clk);
170 if (err) {
171 dev_err(priv->dev, "Unable to start clock: %d\n", err);
172 return err;
173 }
174
175 priv->soc_info->usb_phy_init(phy);
176
177 /* Wait for PHY to reset */
178 usleep_range(30, 300);
179 reg = readl(priv->base + REG_USBPCR_OFFSET);
180 writel(reg & ~USBPCR_POR, priv->base + REG_USBPCR_OFFSET);
181 usleep_range(300, 1000);
182
183 return 0;
184 }
185
ingenic_usb_phy_shutdown(struct usb_phy * phy)186 static void ingenic_usb_phy_shutdown(struct usb_phy *phy)
187 {
188 struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
189
190 clk_disable_unprepare(priv->clk);
191 regulator_disable(priv->vcc_supply);
192 }
193
ingenic_usb_phy_remove(void * phy)194 static void ingenic_usb_phy_remove(void *phy)
195 {
196 usb_remove_phy(phy);
197 }
198
jz4770_usb_phy_init(struct usb_phy * phy)199 static void jz4770_usb_phy_init(struct usb_phy *phy)
200 {
201 struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
202 u32 reg;
203
204 reg = USBPCR_AVLD_REG | USBPCR_COMMONONN | USBPCR_IDPULLUP_ALWAYS |
205 USBPCR_COMPDISTUNE_DFT | USBPCR_OTGTUNE_DFT | USBPCR_SQRXTUNE_DFT |
206 USBPCR_TXFSLSTUNE_DFT | USBPCR_TXRISETUNE_DFT | USBPCR_TXVREFTUNE_DFT |
207 USBPCR_POR;
208 writel(reg, priv->base + REG_USBPCR_OFFSET);
209 }
210
jz4780_usb_phy_init(struct usb_phy * phy)211 static void jz4780_usb_phy_init(struct usb_phy *phy)
212 {
213 struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
214 u32 reg;
215
216 reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_USB_SEL |
217 USBPCR1_WORD_IF_16BIT;
218 writel(reg, priv->base + REG_USBPCR1_OFFSET);
219
220 reg = USBPCR_TXPREEMPHTUNE | USBPCR_COMMONONN | USBPCR_POR;
221 writel(reg, priv->base + REG_USBPCR_OFFSET);
222 }
223
x1000_usb_phy_init(struct usb_phy * phy)224 static void x1000_usb_phy_init(struct usb_phy *phy)
225 {
226 struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
227 u32 reg;
228
229 reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_WORD_IF_16BIT;
230 writel(reg, priv->base + REG_USBPCR1_OFFSET);
231
232 reg = USBPCR_SQRXTUNE_DCR_20PCT | USBPCR_TXPREEMPHTUNE |
233 USBPCR_TXHSXVTUNE_DCR_15MV | USBPCR_TXVREFTUNE_INC_25PPT |
234 USBPCR_COMMONONN | USBPCR_POR;
235 writel(reg, priv->base + REG_USBPCR_OFFSET);
236 }
237
x1830_usb_phy_init(struct usb_phy * phy)238 static void x1830_usb_phy_init(struct usb_phy *phy)
239 {
240 struct jz4770_phy *priv = phy_to_jz4770_phy(phy);
241 u32 reg;
242
243 /* rdt */
244 writel(USBRDT_VBFIL_EN | USBRDT_UTMI_RST, priv->base + REG_USBRDT_OFFSET);
245
246 reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_WORD_IF_16BIT |
247 USBPCR1_DMPD | USBPCR1_DPPD;
248 writel(reg, priv->base + REG_USBPCR1_OFFSET);
249
250 reg = USBPCR_IDPULLUP_OTG | USBPCR_VBUSVLDEXT | USBPCR_TXPREEMPHTUNE |
251 USBPCR_COMMONONN | USBPCR_POR;
252 writel(reg, priv->base + REG_USBPCR_OFFSET);
253 }
254
255 static const struct ingenic_soc_info jz4770_soc_info = {
256 .version = ID_JZ4770,
257
258 .usb_phy_init = jz4770_usb_phy_init,
259 };
260
261 static const struct ingenic_soc_info jz4780_soc_info = {
262 .version = ID_JZ4780,
263
264 .usb_phy_init = jz4780_usb_phy_init,
265 };
266
267 static const struct ingenic_soc_info x1000_soc_info = {
268 .version = ID_X1000,
269
270 .usb_phy_init = x1000_usb_phy_init,
271 };
272
273 static const struct ingenic_soc_info x1830_soc_info = {
274 .version = ID_X1830,
275
276 .usb_phy_init = x1830_usb_phy_init,
277 };
278
279 static const struct of_device_id ingenic_usb_phy_of_matches[] = {
280 { .compatible = "ingenic,jz4770-phy", .data = &jz4770_soc_info },
281 { .compatible = "ingenic,jz4780-phy", .data = &jz4780_soc_info },
282 { .compatible = "ingenic,x1000-phy", .data = &x1000_soc_info },
283 { .compatible = "ingenic,x1830-phy", .data = &x1830_soc_info },
284 { /* sentinel */ }
285 };
286 MODULE_DEVICE_TABLE(of, ingenic_usb_phy_of_matches);
287
jz4770_phy_probe(struct platform_device * pdev)288 static int jz4770_phy_probe(struct platform_device *pdev)
289 {
290 struct device *dev = &pdev->dev;
291 struct jz4770_phy *priv;
292 int err;
293
294 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
295 if (!priv)
296 return -ENOMEM;
297
298 priv->soc_info = device_get_match_data(&pdev->dev);
299 if (!priv->soc_info) {
300 dev_err(&pdev->dev, "Error: No device match found\n");
301 return -ENODEV;
302 }
303
304 platform_set_drvdata(pdev, priv);
305 priv->dev = dev;
306 priv->phy.dev = dev;
307 priv->phy.otg = &priv->otg;
308 priv->phy.label = "ingenic-usb-phy";
309 priv->phy.init = ingenic_usb_phy_init;
310 priv->phy.shutdown = ingenic_usb_phy_shutdown;
311
312 priv->otg.state = OTG_STATE_UNDEFINED;
313 priv->otg.usb_phy = &priv->phy;
314 priv->otg.set_host = ingenic_usb_phy_set_host;
315 priv->otg.set_peripheral = ingenic_usb_phy_set_peripheral;
316
317 priv->base = devm_platform_ioremap_resource(pdev, 0);
318 if (IS_ERR(priv->base)) {
319 dev_err(dev, "Failed to map registers\n");
320 return PTR_ERR(priv->base);
321 }
322
323 priv->clk = devm_clk_get(dev, NULL);
324 if (IS_ERR(priv->clk)) {
325 err = PTR_ERR(priv->clk);
326 if (err != -EPROBE_DEFER)
327 dev_err(dev, "Failed to get clock\n");
328 return err;
329 }
330
331 priv->vcc_supply = devm_regulator_get(dev, "vcc");
332 if (IS_ERR(priv->vcc_supply)) {
333 err = PTR_ERR(priv->vcc_supply);
334 if (err != -EPROBE_DEFER)
335 dev_err(dev, "Failed to get regulator\n");
336 return err;
337 }
338
339 err = usb_add_phy(&priv->phy, USB_PHY_TYPE_USB2);
340 if (err) {
341 if (err != -EPROBE_DEFER)
342 dev_err(dev, "Unable to register PHY\n");
343 return err;
344 }
345
346 return devm_add_action_or_reset(dev, ingenic_usb_phy_remove, &priv->phy);
347 }
348
349 static struct platform_driver ingenic_phy_driver = {
350 .probe = jz4770_phy_probe,
351 .driver = {
352 .name = "jz4770-phy",
353 .of_match_table = of_match_ptr(ingenic_usb_phy_of_matches),
354 },
355 };
356 module_platform_driver(ingenic_phy_driver);
357
358 MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>");
359 MODULE_AUTHOR("漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>");
360 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
361 MODULE_DESCRIPTION("Ingenic SoCs USB PHY driver");
362 MODULE_LICENSE("GPL");
363