1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
40
41 #ifdef CONFIG_X86
42 /* for snoop control */
43 #include <asm/set_memory.h>
44 #include <asm/cpufeature.h>
45 #endif
46 #include <sound/core.h>
47 #include <sound/initval.h>
48 #include <sound/hdaudio.h>
49 #include <sound/hda_i915.h>
50 #include <sound/intel-dsp-config.h>
51 #include <linux/vgaarb.h>
52 #include <linux/vga_switcheroo.h>
53 #include <linux/firmware.h>
54 #include <sound/hda_codec.h>
55 #include "hda_controller.h"
56 #include "hda_intel.h"
57
58 #define CREATE_TRACE_POINTS
59 #include "hda_intel_trace.h"
60
61 /* position fix mode */
62 enum {
63 POS_FIX_AUTO,
64 POS_FIX_LPIB,
65 POS_FIX_POSBUF,
66 POS_FIX_VIACOMBO,
67 POS_FIX_COMBO,
68 POS_FIX_SKL,
69 POS_FIX_FIFO,
70 };
71
72 /* Defines for ATI HD Audio support in SB450 south bridge */
73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
75
76 /* Defines for Nvidia HDA support */
77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
79 #define NVIDIA_HDA_ISTRM_COH 0x4d
80 #define NVIDIA_HDA_OSTRM_COH 0x4c
81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
82
83 /* Defines for Intel SCH HDA snoop control */
84 #define INTEL_HDA_CGCTL 0x48
85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
86 #define INTEL_SCH_HDA_DEVC 0x78
87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
88
89 /* Define VIA HD Audio Device ID*/
90 #define VIA_HDAC_DEVICE_ID 0x3288
91
92 /* max number of SDs */
93 /* ICH, ATI and VIA have 4 playback and 4 capture */
94 #define ICH6_NUM_CAPTURE 4
95 #define ICH6_NUM_PLAYBACK 4
96
97 /* ULI has 6 playback and 5 capture */
98 #define ULI_NUM_CAPTURE 5
99 #define ULI_NUM_PLAYBACK 6
100
101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
102 #define ATIHDMI_NUM_CAPTURE 0
103 #define ATIHDMI_NUM_PLAYBACK 8
104
105 /* TERA has 4 playback and 3 capture */
106 #define TERA_NUM_CAPTURE 3
107 #define TERA_NUM_PLAYBACK 4
108
109
110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
113 static char *model[SNDRV_CARDS];
114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
117 static int probe_only[SNDRV_CARDS];
118 static int jackpoll_ms[SNDRV_CARDS];
119 static int single_cmd = -1;
120 static int enable_msi = -1;
121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
122 static char *patch[SNDRV_CARDS];
123 #endif
124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
126 CONFIG_SND_HDA_INPUT_BEEP_MODE};
127 #endif
128 static bool dmic_detect = 1;
129
130 module_param_array(index, int, NULL, 0444);
131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
132 module_param_array(id, charp, NULL, 0444);
133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
134 module_param_array(enable, bool, NULL, 0444);
135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
136 module_param_array(model, charp, NULL, 0444);
137 MODULE_PARM_DESC(model, "Use the given board model.");
138 module_param_array(position_fix, int, NULL, 0444);
139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
141 module_param_array(bdl_pos_adj, int, NULL, 0644);
142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
143 module_param_array(probe_mask, int, NULL, 0444);
144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
145 module_param_array(probe_only, int, NULL, 0444);
146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
147 module_param_array(jackpoll_ms, int, NULL, 0444);
148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
149 module_param(single_cmd, bint, 0444);
150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
151 "(for debugging only).");
152 module_param(enable_msi, bint, 0444);
153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
155 module_param_array(patch, charp, NULL, 0444);
156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
157 #endif
158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
159 module_param_array(beep_mode, bool, NULL, 0444);
160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
161 "(0=off, 1=on) (default=1).");
162 #endif
163 module_param(dmic_detect, bool, 0444);
164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
165 "(0=off, 1=on) (default=1); "
166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
167
168 #ifdef CONFIG_PM
169 static int param_set_xint(const char *val, const struct kernel_param *kp);
170 static const struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173 };
174 #define param_check_xint param_check_int
175
176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
177 module_param(power_save, xint, 0644);
178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
179 "(in second, 0 = disable).");
180
181 static bool pm_blacklist = true;
182 module_param(pm_blacklist, bool, 0644);
183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
184
185 /* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
192 #else
193 #define power_save 0
194 #endif /* CONFIG_PM */
195
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop true
207 #endif
208
209
210 MODULE_LICENSE("GPL");
211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
213 "{Intel, ICH7},"
214 "{Intel, ESB2},"
215 "{Intel, ICH8},"
216 "{Intel, ICH9},"
217 "{Intel, ICH10},"
218 "{Intel, PCH},"
219 "{Intel, CPT},"
220 "{Intel, PPT},"
221 "{Intel, LPT},"
222 "{Intel, LPT_LP},"
223 "{Intel, WPT_LP},"
224 "{Intel, SPT},"
225 "{Intel, SPT_LP},"
226 "{Intel, HPT},"
227 "{Intel, PBG},"
228 "{Intel, SCH},"
229 "{ATI, SB450},"
230 "{ATI, SB600},"
231 "{ATI, RS600},"
232 "{ATI, RS690},"
233 "{ATI, RS780},"
234 "{ATI, R600},"
235 "{ATI, RV630},"
236 "{ATI, RV610},"
237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
241 "{VIA, VT8251},"
242 "{VIA, VT8237A},"
243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
245 MODULE_DESCRIPTION("Intel HDA driver");
246
247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
249 #define SUPPORT_VGA_SWITCHEROO
250 #endif
251 #endif
252
253
254 /*
255 */
256
257 /* driver types */
258 enum {
259 AZX_DRIVER_ICH,
260 AZX_DRIVER_PCH,
261 AZX_DRIVER_SCH,
262 AZX_DRIVER_SKL,
263 AZX_DRIVER_HDMI,
264 AZX_DRIVER_ATI,
265 AZX_DRIVER_ATIHDMI,
266 AZX_DRIVER_ATIHDMI_NS,
267 AZX_DRIVER_VIA,
268 AZX_DRIVER_SIS,
269 AZX_DRIVER_ULI,
270 AZX_DRIVER_NVIDIA,
271 AZX_DRIVER_TERA,
272 AZX_DRIVER_CTX,
273 AZX_DRIVER_CTHDA,
274 AZX_DRIVER_CMEDIA,
275 AZX_DRIVER_ZHAOXIN,
276 AZX_DRIVER_GENERIC,
277 AZX_NUM_DRIVERS, /* keep this as last entry */
278 };
279
280 #define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
283
284 /* quirks for old Intel chipsets */
285 #define AZX_DCAPS_INTEL_ICH \
286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
287
288 /* quirks for Intel PCH */
289 #define AZX_DCAPS_INTEL_PCH_BASE \
290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
291 AZX_DCAPS_SNOOP_TYPE(SCH))
292
293 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
294 #define AZX_DCAPS_INTEL_PCH_NOPM \
295 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
296
297 /* PCH for HSW/BDW; with runtime PM */
298 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
299 #define AZX_DCAPS_INTEL_PCH \
300 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
301
302 /* HSW HDMI */
303 #define AZX_DCAPS_INTEL_HASWELL \
304 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
305 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
306 AZX_DCAPS_SNOOP_TYPE(SCH))
307
308 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
309 #define AZX_DCAPS_INTEL_BROADWELL \
310 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
311 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
312 AZX_DCAPS_SNOOP_TYPE(SCH))
313
314 #define AZX_DCAPS_INTEL_BAYTRAIL \
315 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
316
317 #define AZX_DCAPS_INTEL_BRASWELL \
318 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
319 AZX_DCAPS_I915_COMPONENT)
320
321 #define AZX_DCAPS_INTEL_SKYLAKE \
322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
323 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
324
325 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
326
327 /* quirks for ATI SB / AMD Hudson */
328 #define AZX_DCAPS_PRESET_ATI_SB \
329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
330 AZX_DCAPS_SNOOP_TYPE(ATI))
331
332 /* quirks for ATI/AMD HDMI */
333 #define AZX_DCAPS_PRESET_ATI_HDMI \
334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
335 AZX_DCAPS_NO_MSI64)
336
337 /* quirks for ATI HDMI with snoop off */
338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
340
341 /* quirks for AMD SB */
342 #define AZX_DCAPS_PRESET_AMD_SB \
343 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
344 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
345 AZX_DCAPS_RETRY_PROBE)
346
347 /* quirks for Nvidia */
348 #define AZX_DCAPS_PRESET_NVIDIA \
349 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
350 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
351
352 #define AZX_DCAPS_PRESET_CTHDA \
353 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
354 AZX_DCAPS_NO_64BIT |\
355 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
356
357 /*
358 * vga_switcheroo support
359 */
360 #ifdef SUPPORT_VGA_SWITCHEROO
361 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
362 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
363 #else
364 #define use_vga_switcheroo(chip) 0
365 #define needs_eld_notify_link(chip) false
366 #endif
367
368 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
369 ((pci)->device == 0x0c0c) || \
370 ((pci)->device == 0x0d0c) || \
371 ((pci)->device == 0x160c) || \
372 ((pci)->device == 0x490d) || \
373 ((pci)->device == 0x4f90) || \
374 ((pci)->device == 0x4f91) || \
375 ((pci)->device == 0x4f92))
376
377 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
378
379 static const char * const driver_short_names[] = {
380 [AZX_DRIVER_ICH] = "HDA Intel",
381 [AZX_DRIVER_PCH] = "HDA Intel PCH",
382 [AZX_DRIVER_SCH] = "HDA Intel MID",
383 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
384 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
385 [AZX_DRIVER_ATI] = "HDA ATI SB",
386 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
387 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
388 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
389 [AZX_DRIVER_SIS] = "HDA SIS966",
390 [AZX_DRIVER_ULI] = "HDA ULI M5461",
391 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
392 [AZX_DRIVER_TERA] = "HDA Teradici",
393 [AZX_DRIVER_CTX] = "HDA Creative",
394 [AZX_DRIVER_CTHDA] = "HDA Creative",
395 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
396 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
397 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
398 };
399
400 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
401 static void set_default_power_save(struct azx *chip);
402
403 /*
404 * initialize the PCI registers
405 */
406 /* update bits in a PCI register byte */
update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)407 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
408 unsigned char mask, unsigned char val)
409 {
410 unsigned char data;
411
412 pci_read_config_byte(pci, reg, &data);
413 data &= ~mask;
414 data |= (val & mask);
415 pci_write_config_byte(pci, reg, data);
416 }
417
azx_init_pci(struct azx * chip)418 static void azx_init_pci(struct azx *chip)
419 {
420 int snoop_type = azx_get_snoop_type(chip);
421
422 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
423 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
424 * Ensuring these bits are 0 clears playback static on some HD Audio
425 * codecs.
426 * The PCI register TCSEL is defined in the Intel manuals.
427 */
428 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
429 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
430 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
431 }
432
433 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
434 * we need to enable snoop.
435 */
436 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
437 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
438 azx_snoop(chip));
439 update_pci_byte(chip->pci,
440 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
441 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
442 }
443
444 /* For NVIDIA HDA, enable snoop */
445 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
446 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
447 azx_snoop(chip));
448 update_pci_byte(chip->pci,
449 NVIDIA_HDA_TRANSREG_ADDR,
450 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
451 update_pci_byte(chip->pci,
452 NVIDIA_HDA_ISTRM_COH,
453 0x01, NVIDIA_HDA_ENABLE_COHBIT);
454 update_pci_byte(chip->pci,
455 NVIDIA_HDA_OSTRM_COH,
456 0x01, NVIDIA_HDA_ENABLE_COHBIT);
457 }
458
459 /* Enable SCH/PCH snoop if needed */
460 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
461 unsigned short snoop;
462 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
463 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
464 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
465 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
466 if (!azx_snoop(chip))
467 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
468 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
469 pci_read_config_word(chip->pci,
470 INTEL_SCH_HDA_DEVC, &snoop);
471 }
472 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
473 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
474 "Disabled" : "Enabled");
475 }
476 }
477
478 /*
479 * In BXT-P A0, HD-Audio DMA requests is later than expected,
480 * and makes an audio stream sensitive to system latencies when
481 * 24/32 bits are playing.
482 * Adjusting threshold of DMA fifo to force the DMA request
483 * sooner to improve latency tolerance at the expense of power.
484 */
bxt_reduce_dma_latency(struct azx * chip)485 static void bxt_reduce_dma_latency(struct azx *chip)
486 {
487 u32 val;
488
489 val = azx_readl(chip, VS_EM4L);
490 val &= (0x3 << 20);
491 azx_writel(chip, VS_EM4L, val);
492 }
493
494 /*
495 * ML_LCAP bits:
496 * bit 0: 6 MHz Supported
497 * bit 1: 12 MHz Supported
498 * bit 2: 24 MHz Supported
499 * bit 3: 48 MHz Supported
500 * bit 4: 96 MHz Supported
501 * bit 5: 192 MHz Supported
502 */
intel_get_lctl_scf(struct azx * chip)503 static int intel_get_lctl_scf(struct azx *chip)
504 {
505 struct hdac_bus *bus = azx_bus(chip);
506 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
507 u32 val, t;
508 int i;
509
510 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
511
512 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
513 t = preferred_bits[i];
514 if (val & (1 << t))
515 return t;
516 }
517
518 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
519 return 0;
520 }
521
intel_ml_lctl_set_power(struct azx * chip,int state)522 static int intel_ml_lctl_set_power(struct azx *chip, int state)
523 {
524 struct hdac_bus *bus = azx_bus(chip);
525 u32 val;
526 int timeout;
527
528 /*
529 * the codecs are sharing the first link setting by default
530 * If other links are enabled for stream, they need similar fix
531 */
532 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
533 val &= ~AZX_MLCTL_SPA;
534 val |= state << AZX_MLCTL_SPA_SHIFT;
535 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
536 /* wait for CPA */
537 timeout = 50;
538 while (timeout) {
539 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
540 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
541 return 0;
542 timeout--;
543 udelay(10);
544 }
545
546 return -1;
547 }
548
intel_init_lctl(struct azx * chip)549 static void intel_init_lctl(struct azx *chip)
550 {
551 struct hdac_bus *bus = azx_bus(chip);
552 u32 val;
553 int ret;
554
555 /* 0. check lctl register value is correct or not */
556 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
557 /* if SCF is already set, let's use it */
558 if ((val & ML_LCTL_SCF_MASK) != 0)
559 return;
560
561 /*
562 * Before operating on SPA, CPA must match SPA.
563 * Any deviation may result in undefined behavior.
564 */
565 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
566 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
567 return;
568
569 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
570 ret = intel_ml_lctl_set_power(chip, 0);
571 udelay(100);
572 if (ret)
573 goto set_spa;
574
575 /* 2. update SCF to select a properly audio clock*/
576 val &= ~ML_LCTL_SCF_MASK;
577 val |= intel_get_lctl_scf(chip);
578 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
579
580 set_spa:
581 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
582 intel_ml_lctl_set_power(chip, 1);
583 udelay(100);
584 }
585
hda_intel_init_chip(struct azx * chip,bool full_reset)586 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
587 {
588 struct hdac_bus *bus = azx_bus(chip);
589 struct pci_dev *pci = chip->pci;
590 u32 val;
591
592 snd_hdac_set_codec_wakeup(bus, true);
593 if (chip->driver_type == AZX_DRIVER_SKL) {
594 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
595 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
596 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
597 }
598 azx_init_chip(chip, full_reset);
599 if (chip->driver_type == AZX_DRIVER_SKL) {
600 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
601 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
602 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
603 }
604
605 snd_hdac_set_codec_wakeup(bus, false);
606
607 /* reduce dma latency to avoid noise */
608 if (IS_BXT(pci))
609 bxt_reduce_dma_latency(chip);
610
611 if (bus->mlcap != NULL)
612 intel_init_lctl(chip);
613 }
614
615 /* calculate runtime delay from LPIB */
azx_get_delay_from_lpib(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)616 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
617 unsigned int pos)
618 {
619 struct snd_pcm_substream *substream = azx_dev->core.substream;
620 int stream = substream->stream;
621 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
622 int delay;
623
624 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
625 delay = pos - lpib_pos;
626 else
627 delay = lpib_pos - pos;
628 if (delay < 0) {
629 if (delay >= azx_dev->core.delay_negative_threshold)
630 delay = 0;
631 else
632 delay += azx_dev->core.bufsize;
633 }
634
635 if (delay >= azx_dev->core.period_bytes) {
636 dev_info(chip->card->dev,
637 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
638 delay, azx_dev->core.period_bytes);
639 delay = 0;
640 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
641 chip->get_delay[stream] = NULL;
642 }
643
644 return bytes_to_frames(substream->runtime, delay);
645 }
646
647 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
648
649 /* called from IRQ */
azx_position_check(struct azx * chip,struct azx_dev * azx_dev)650 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
651 {
652 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
653 int ok;
654
655 ok = azx_position_ok(chip, azx_dev);
656 if (ok == 1) {
657 azx_dev->irq_pending = 0;
658 return ok;
659 } else if (ok == 0) {
660 /* bogus IRQ, process it later */
661 azx_dev->irq_pending = 1;
662 schedule_work(&hda->irq_pending_work);
663 }
664 return 0;
665 }
666
667 #define display_power(chip, enable) \
668 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
669
670 /*
671 * Check whether the current DMA position is acceptable for updating
672 * periods. Returns non-zero if it's OK.
673 *
674 * Many HD-audio controllers appear pretty inaccurate about
675 * the update-IRQ timing. The IRQ is issued before actually the
676 * data is processed. So, we need to process it afterwords in a
677 * workqueue.
678 *
679 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
680 */
azx_position_ok(struct azx * chip,struct azx_dev * azx_dev)681 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
682 {
683 struct snd_pcm_substream *substream = azx_dev->core.substream;
684 struct snd_pcm_runtime *runtime = substream->runtime;
685 int stream = substream->stream;
686 u32 wallclk;
687 unsigned int pos;
688 snd_pcm_uframes_t hwptr, target;
689
690 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
691 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
692 return -1; /* bogus (too early) interrupt */
693
694 if (chip->get_position[stream])
695 pos = chip->get_position[stream](chip, azx_dev);
696 else { /* use the position buffer as default */
697 pos = azx_get_pos_posbuf(chip, azx_dev);
698 if (!pos || pos == (u32)-1) {
699 dev_info(chip->card->dev,
700 "Invalid position buffer, using LPIB read method instead.\n");
701 chip->get_position[stream] = azx_get_pos_lpib;
702 if (chip->get_position[0] == azx_get_pos_lpib &&
703 chip->get_position[1] == azx_get_pos_lpib)
704 azx_bus(chip)->use_posbuf = false;
705 pos = azx_get_pos_lpib(chip, azx_dev);
706 chip->get_delay[stream] = NULL;
707 } else {
708 chip->get_position[stream] = azx_get_pos_posbuf;
709 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
710 chip->get_delay[stream] = azx_get_delay_from_lpib;
711 }
712 }
713
714 if (pos >= azx_dev->core.bufsize)
715 pos = 0;
716
717 if (WARN_ONCE(!azx_dev->core.period_bytes,
718 "hda-intel: zero azx_dev->period_bytes"))
719 return -1; /* this shouldn't happen! */
720 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
721 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
722 /* NG - it's below the first next period boundary */
723 return chip->bdl_pos_adj ? 0 : -1;
724 azx_dev->core.start_wallclk += wallclk;
725
726 if (azx_dev->core.no_period_wakeup)
727 return 1; /* OK, no need to check period boundary */
728
729 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
730 return 1; /* OK, already in hwptr updating process */
731
732 /* check whether the period gets really elapsed */
733 pos = bytes_to_frames(runtime, pos);
734 hwptr = runtime->hw_ptr_base + pos;
735 if (hwptr < runtime->status->hw_ptr)
736 hwptr += runtime->buffer_size;
737 target = runtime->hw_ptr_interrupt + runtime->period_size;
738 if (hwptr < target) {
739 /* too early wakeup, process it later */
740 return chip->bdl_pos_adj ? 0 : -1;
741 }
742
743 return 1; /* OK, it's fine */
744 }
745
746 /*
747 * The work for pending PCM period updates.
748 */
azx_irq_pending_work(struct work_struct * work)749 static void azx_irq_pending_work(struct work_struct *work)
750 {
751 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
752 struct azx *chip = &hda->chip;
753 struct hdac_bus *bus = azx_bus(chip);
754 struct hdac_stream *s;
755 int pending, ok;
756
757 if (!hda->irq_pending_warned) {
758 dev_info(chip->card->dev,
759 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
760 chip->card->number);
761 hda->irq_pending_warned = 1;
762 }
763
764 for (;;) {
765 pending = 0;
766 spin_lock_irq(&bus->reg_lock);
767 list_for_each_entry(s, &bus->stream_list, list) {
768 struct azx_dev *azx_dev = stream_to_azx_dev(s);
769 if (!azx_dev->irq_pending ||
770 !s->substream ||
771 !s->running)
772 continue;
773 ok = azx_position_ok(chip, azx_dev);
774 if (ok > 0) {
775 azx_dev->irq_pending = 0;
776 spin_unlock(&bus->reg_lock);
777 snd_pcm_period_elapsed(s->substream);
778 spin_lock(&bus->reg_lock);
779 } else if (ok < 0) {
780 pending = 0; /* too early */
781 } else
782 pending++;
783 }
784 spin_unlock_irq(&bus->reg_lock);
785 if (!pending)
786 return;
787 msleep(1);
788 }
789 }
790
791 /* clear irq_pending flags and assure no on-going workq */
azx_clear_irq_pending(struct azx * chip)792 static void azx_clear_irq_pending(struct azx *chip)
793 {
794 struct hdac_bus *bus = azx_bus(chip);
795 struct hdac_stream *s;
796
797 spin_lock_irq(&bus->reg_lock);
798 list_for_each_entry(s, &bus->stream_list, list) {
799 struct azx_dev *azx_dev = stream_to_azx_dev(s);
800 azx_dev->irq_pending = 0;
801 }
802 spin_unlock_irq(&bus->reg_lock);
803 }
804
azx_acquire_irq(struct azx * chip,int do_disconnect)805 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
806 {
807 struct hdac_bus *bus = azx_bus(chip);
808
809 if (request_irq(chip->pci->irq, azx_interrupt,
810 chip->msi ? 0 : IRQF_SHARED,
811 chip->card->irq_descr, chip)) {
812 dev_err(chip->card->dev,
813 "unable to grab IRQ %d, disabling device\n",
814 chip->pci->irq);
815 if (do_disconnect)
816 snd_card_disconnect(chip->card);
817 return -1;
818 }
819 bus->irq = chip->pci->irq;
820 chip->card->sync_irq = bus->irq;
821 pci_intx(chip->pci, !chip->msi);
822 return 0;
823 }
824
825 /* get the current DMA position with correction on VIA chips */
azx_via_get_position(struct azx * chip,struct azx_dev * azx_dev)826 static unsigned int azx_via_get_position(struct azx *chip,
827 struct azx_dev *azx_dev)
828 {
829 unsigned int link_pos, mini_pos, bound_pos;
830 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
831 unsigned int fifo_size;
832
833 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
834 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
835 /* Playback, no problem using link position */
836 return link_pos;
837 }
838
839 /* Capture */
840 /* For new chipset,
841 * use mod to get the DMA position just like old chipset
842 */
843 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
844 mod_dma_pos %= azx_dev->core.period_bytes;
845
846 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
847
848 if (azx_dev->insufficient) {
849 /* Link position never gather than FIFO size */
850 if (link_pos <= fifo_size)
851 return 0;
852
853 azx_dev->insufficient = 0;
854 }
855
856 if (link_pos <= fifo_size)
857 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
858 else
859 mini_pos = link_pos - fifo_size;
860
861 /* Find nearest previous boudary */
862 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
863 mod_link_pos = link_pos % azx_dev->core.period_bytes;
864 if (mod_link_pos >= fifo_size)
865 bound_pos = link_pos - mod_link_pos;
866 else if (mod_dma_pos >= mod_mini_pos)
867 bound_pos = mini_pos - mod_mini_pos;
868 else {
869 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
870 if (bound_pos >= azx_dev->core.bufsize)
871 bound_pos = 0;
872 }
873
874 /* Calculate real DMA position we want */
875 return bound_pos + mod_dma_pos;
876 }
877
878 #define AMD_FIFO_SIZE 32
879
880 /* get the current DMA position with FIFO size correction */
azx_get_pos_fifo(struct azx * chip,struct azx_dev * azx_dev)881 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
882 {
883 struct snd_pcm_substream *substream = azx_dev->core.substream;
884 struct snd_pcm_runtime *runtime = substream->runtime;
885 unsigned int pos, delay;
886
887 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
888 if (!runtime)
889 return pos;
890
891 runtime->delay = AMD_FIFO_SIZE;
892 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
893 if (azx_dev->insufficient) {
894 if (pos < delay) {
895 delay = pos;
896 runtime->delay = bytes_to_frames(runtime, pos);
897 } else {
898 azx_dev->insufficient = 0;
899 }
900 }
901
902 /* correct the DMA position for capture stream */
903 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
904 if (pos < delay)
905 pos += azx_dev->core.bufsize;
906 pos -= delay;
907 }
908
909 return pos;
910 }
911
azx_get_delay_from_fifo(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)912 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
913 unsigned int pos)
914 {
915 struct snd_pcm_substream *substream = azx_dev->core.substream;
916
917 /* just read back the calculated value in the above */
918 return substream->runtime->delay;
919 }
920
__azx_shutdown_chip(struct azx * chip,bool skip_link_reset)921 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
922 {
923 azx_stop_chip(chip);
924 if (!skip_link_reset)
925 azx_enter_link_reset(chip);
926 azx_clear_irq_pending(chip);
927 display_power(chip, false);
928 }
929
930 #ifdef CONFIG_PM
931 static DEFINE_MUTEX(card_list_lock);
932 static LIST_HEAD(card_list);
933
azx_shutdown_chip(struct azx * chip)934 static void azx_shutdown_chip(struct azx *chip)
935 {
936 __azx_shutdown_chip(chip, false);
937 }
938
azx_add_card_list(struct azx * chip)939 static void azx_add_card_list(struct azx *chip)
940 {
941 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
942 mutex_lock(&card_list_lock);
943 list_add(&hda->list, &card_list);
944 mutex_unlock(&card_list_lock);
945 }
946
azx_del_card_list(struct azx * chip)947 static void azx_del_card_list(struct azx *chip)
948 {
949 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
950 mutex_lock(&card_list_lock);
951 list_del_init(&hda->list);
952 mutex_unlock(&card_list_lock);
953 }
954
955 /* trigger power-save check at writing parameter */
param_set_xint(const char * val,const struct kernel_param * kp)956 static int param_set_xint(const char *val, const struct kernel_param *kp)
957 {
958 struct hda_intel *hda;
959 struct azx *chip;
960 int prev = power_save;
961 int ret = param_set_int(val, kp);
962
963 if (ret || prev == power_save)
964 return ret;
965
966 mutex_lock(&card_list_lock);
967 list_for_each_entry(hda, &card_list, list) {
968 chip = &hda->chip;
969 if (!hda->probe_continued || chip->disabled)
970 continue;
971 snd_hda_set_power_save(&chip->bus, power_save * 1000);
972 }
973 mutex_unlock(&card_list_lock);
974 return 0;
975 }
976
977 /*
978 * power management
979 */
azx_is_pm_ready(struct snd_card * card)980 static bool azx_is_pm_ready(struct snd_card *card)
981 {
982 struct azx *chip;
983 struct hda_intel *hda;
984
985 if (!card)
986 return false;
987 chip = card->private_data;
988 hda = container_of(chip, struct hda_intel, chip);
989 if (chip->disabled || hda->init_failed || !chip->running)
990 return false;
991 return true;
992 }
993
__azx_runtime_resume(struct azx * chip)994 static void __azx_runtime_resume(struct azx *chip)
995 {
996 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
997 struct hdac_bus *bus = azx_bus(chip);
998 struct hda_codec *codec;
999 int status;
1000
1001 display_power(chip, true);
1002 if (hda->need_i915_power)
1003 snd_hdac_i915_set_bclk(bus);
1004
1005 /* Read STATESTS before controller reset */
1006 status = azx_readw(chip, STATESTS);
1007
1008 azx_init_pci(chip);
1009 hda_intel_init_chip(chip, true);
1010
1011 /* Avoid codec resume if runtime resume is for system suspend */
1012 if (!chip->pm_prepared) {
1013 list_for_each_codec(codec, &chip->bus) {
1014 if (codec->relaxed_resume)
1015 continue;
1016
1017 if (codec->forced_resume || (status & (1 << codec->addr)))
1018 pm_request_resume(hda_codec_dev(codec));
1019 }
1020 }
1021
1022 /* power down again for link-controlled chips */
1023 if (!hda->need_i915_power)
1024 display_power(chip, false);
1025 }
1026
1027 #ifdef CONFIG_PM_SLEEP
azx_prepare(struct device * dev)1028 static int azx_prepare(struct device *dev)
1029 {
1030 struct snd_card *card = dev_get_drvdata(dev);
1031 struct azx *chip;
1032
1033 if (!azx_is_pm_ready(card))
1034 return 0;
1035
1036 chip = card->private_data;
1037 chip->pm_prepared = 1;
1038 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1039
1040 flush_work(&azx_bus(chip)->unsol_work);
1041
1042 /* HDA controller always requires different WAKEEN for runtime suspend
1043 * and system suspend, so don't use direct-complete here.
1044 */
1045 return 0;
1046 }
1047
azx_complete(struct device * dev)1048 static void azx_complete(struct device *dev)
1049 {
1050 struct snd_card *card = dev_get_drvdata(dev);
1051 struct azx *chip;
1052
1053 if (!azx_is_pm_ready(card))
1054 return;
1055
1056 chip = card->private_data;
1057 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1058 chip->pm_prepared = 0;
1059 }
1060
azx_suspend(struct device * dev)1061 static int azx_suspend(struct device *dev)
1062 {
1063 struct snd_card *card = dev_get_drvdata(dev);
1064 struct azx *chip;
1065 struct hdac_bus *bus;
1066
1067 if (!azx_is_pm_ready(card))
1068 return 0;
1069
1070 chip = card->private_data;
1071 bus = azx_bus(chip);
1072 azx_shutdown_chip(chip);
1073 if (bus->irq >= 0) {
1074 free_irq(bus->irq, chip);
1075 bus->irq = -1;
1076 chip->card->sync_irq = -1;
1077 }
1078
1079 if (chip->msi)
1080 pci_disable_msi(chip->pci);
1081
1082 trace_azx_suspend(chip);
1083 return 0;
1084 }
1085
azx_resume(struct device * dev)1086 static int azx_resume(struct device *dev)
1087 {
1088 struct snd_card *card = dev_get_drvdata(dev);
1089 struct azx *chip;
1090
1091 if (!azx_is_pm_ready(card))
1092 return 0;
1093
1094 chip = card->private_data;
1095 if (chip->msi)
1096 if (pci_enable_msi(chip->pci) < 0)
1097 chip->msi = 0;
1098 if (azx_acquire_irq(chip, 1) < 0)
1099 return -EIO;
1100
1101 __azx_runtime_resume(chip);
1102
1103 trace_azx_resume(chip);
1104 return 0;
1105 }
1106
1107 /* put codec down to D3 at hibernation for Intel SKL+;
1108 * otherwise BIOS may still access the codec and screw up the driver
1109 */
azx_freeze_noirq(struct device * dev)1110 static int azx_freeze_noirq(struct device *dev)
1111 {
1112 struct snd_card *card = dev_get_drvdata(dev);
1113 struct azx *chip = card->private_data;
1114 struct pci_dev *pci = to_pci_dev(dev);
1115
1116 if (!azx_is_pm_ready(card))
1117 return 0;
1118 if (chip->driver_type == AZX_DRIVER_SKL)
1119 pci_set_power_state(pci, PCI_D3hot);
1120
1121 return 0;
1122 }
1123
azx_thaw_noirq(struct device * dev)1124 static int azx_thaw_noirq(struct device *dev)
1125 {
1126 struct snd_card *card = dev_get_drvdata(dev);
1127 struct azx *chip = card->private_data;
1128 struct pci_dev *pci = to_pci_dev(dev);
1129
1130 if (!azx_is_pm_ready(card))
1131 return 0;
1132 if (chip->driver_type == AZX_DRIVER_SKL)
1133 pci_set_power_state(pci, PCI_D0);
1134
1135 return 0;
1136 }
1137 #endif /* CONFIG_PM_SLEEP */
1138
azx_runtime_suspend(struct device * dev)1139 static int azx_runtime_suspend(struct device *dev)
1140 {
1141 struct snd_card *card = dev_get_drvdata(dev);
1142 struct azx *chip;
1143
1144 if (!azx_is_pm_ready(card))
1145 return 0;
1146 chip = card->private_data;
1147
1148 /* enable controller wake up event */
1149 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1150
1151 azx_shutdown_chip(chip);
1152 trace_azx_runtime_suspend(chip);
1153 return 0;
1154 }
1155
azx_runtime_resume(struct device * dev)1156 static int azx_runtime_resume(struct device *dev)
1157 {
1158 struct snd_card *card = dev_get_drvdata(dev);
1159 struct azx *chip;
1160
1161 if (!azx_is_pm_ready(card))
1162 return 0;
1163 chip = card->private_data;
1164 __azx_runtime_resume(chip);
1165
1166 /* disable controller Wake Up event*/
1167 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1168
1169 trace_azx_runtime_resume(chip);
1170 return 0;
1171 }
1172
azx_runtime_idle(struct device * dev)1173 static int azx_runtime_idle(struct device *dev)
1174 {
1175 struct snd_card *card = dev_get_drvdata(dev);
1176 struct azx *chip;
1177 struct hda_intel *hda;
1178
1179 if (!card)
1180 return 0;
1181
1182 chip = card->private_data;
1183 hda = container_of(chip, struct hda_intel, chip);
1184 if (chip->disabled || hda->init_failed)
1185 return 0;
1186
1187 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1188 azx_bus(chip)->codec_powered || !chip->running)
1189 return -EBUSY;
1190
1191 /* ELD notification gets broken when HD-audio bus is off */
1192 if (needs_eld_notify_link(chip))
1193 return -EBUSY;
1194
1195 return 0;
1196 }
1197
1198 static const struct dev_pm_ops azx_pm = {
1199 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1200 #ifdef CONFIG_PM_SLEEP
1201 .prepare = azx_prepare,
1202 .complete = azx_complete,
1203 .freeze_noirq = azx_freeze_noirq,
1204 .thaw_noirq = azx_thaw_noirq,
1205 #endif
1206 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1207 };
1208
1209 #define AZX_PM_OPS &azx_pm
1210 #else
1211 #define azx_add_card_list(chip) /* NOP */
1212 #define azx_del_card_list(chip) /* NOP */
1213 #define AZX_PM_OPS NULL
1214 #endif /* CONFIG_PM */
1215
1216
1217 static int azx_probe_continue(struct azx *chip);
1218
1219 #ifdef SUPPORT_VGA_SWITCHEROO
1220 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1221
azx_vs_set_state(struct pci_dev * pci,enum vga_switcheroo_state state)1222 static void azx_vs_set_state(struct pci_dev *pci,
1223 enum vga_switcheroo_state state)
1224 {
1225 struct snd_card *card = pci_get_drvdata(pci);
1226 struct azx *chip = card->private_data;
1227 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1228 struct hda_codec *codec;
1229 bool disabled;
1230
1231 wait_for_completion(&hda->probe_wait);
1232 if (hda->init_failed)
1233 return;
1234
1235 disabled = (state == VGA_SWITCHEROO_OFF);
1236 if (chip->disabled == disabled)
1237 return;
1238
1239 if (!hda->probe_continued) {
1240 chip->disabled = disabled;
1241 if (!disabled) {
1242 dev_info(chip->card->dev,
1243 "Start delayed initialization\n");
1244 if (azx_probe_continue(chip) < 0)
1245 dev_err(chip->card->dev, "initialization error\n");
1246 }
1247 } else {
1248 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1249 disabled ? "Disabling" : "Enabling");
1250 if (disabled) {
1251 list_for_each_codec(codec, &chip->bus) {
1252 pm_runtime_suspend(hda_codec_dev(codec));
1253 pm_runtime_disable(hda_codec_dev(codec));
1254 }
1255 pm_runtime_suspend(card->dev);
1256 pm_runtime_disable(card->dev);
1257 /* when we get suspended by vga_switcheroo we end up in D3cold,
1258 * however we have no ACPI handle, so pci/acpi can't put us there,
1259 * put ourselves there */
1260 pci->current_state = PCI_D3cold;
1261 chip->disabled = true;
1262 if (snd_hda_lock_devices(&chip->bus))
1263 dev_warn(chip->card->dev,
1264 "Cannot lock devices!\n");
1265 } else {
1266 snd_hda_unlock_devices(&chip->bus);
1267 chip->disabled = false;
1268 pm_runtime_enable(card->dev);
1269 list_for_each_codec(codec, &chip->bus) {
1270 pm_runtime_enable(hda_codec_dev(codec));
1271 pm_runtime_resume(hda_codec_dev(codec));
1272 }
1273 }
1274 }
1275 }
1276
azx_vs_can_switch(struct pci_dev * pci)1277 static bool azx_vs_can_switch(struct pci_dev *pci)
1278 {
1279 struct snd_card *card = pci_get_drvdata(pci);
1280 struct azx *chip = card->private_data;
1281 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1282
1283 wait_for_completion(&hda->probe_wait);
1284 if (hda->init_failed)
1285 return false;
1286 if (chip->disabled || !hda->probe_continued)
1287 return true;
1288 if (snd_hda_lock_devices(&chip->bus))
1289 return false;
1290 snd_hda_unlock_devices(&chip->bus);
1291 return true;
1292 }
1293
1294 /*
1295 * The discrete GPU cannot power down unless the HDA controller runtime
1296 * suspends, so activate runtime PM on codecs even if power_save == 0.
1297 */
setup_vga_switcheroo_runtime_pm(struct azx * chip)1298 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1299 {
1300 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1301 struct hda_codec *codec;
1302
1303 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1304 list_for_each_codec(codec, &chip->bus)
1305 codec->auto_runtime_pm = 1;
1306 /* reset the power save setup */
1307 if (chip->running)
1308 set_default_power_save(chip);
1309 }
1310 }
1311
azx_vs_gpu_bound(struct pci_dev * pci,enum vga_switcheroo_client_id client_id)1312 static void azx_vs_gpu_bound(struct pci_dev *pci,
1313 enum vga_switcheroo_client_id client_id)
1314 {
1315 struct snd_card *card = pci_get_drvdata(pci);
1316 struct azx *chip = card->private_data;
1317
1318 if (client_id == VGA_SWITCHEROO_DIS)
1319 chip->bus.keep_power = 0;
1320 setup_vga_switcheroo_runtime_pm(chip);
1321 }
1322
init_vga_switcheroo(struct azx * chip)1323 static void init_vga_switcheroo(struct azx *chip)
1324 {
1325 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1326 struct pci_dev *p = get_bound_vga(chip->pci);
1327 struct pci_dev *parent;
1328 if (p) {
1329 dev_info(chip->card->dev,
1330 "Handle vga_switcheroo audio client\n");
1331 hda->use_vga_switcheroo = 1;
1332
1333 /* cleared in either gpu_bound op or codec probe, or when its
1334 * upstream port has _PR3 (i.e. dGPU).
1335 */
1336 parent = pci_upstream_bridge(p);
1337 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1338 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1339 pci_dev_put(p);
1340 }
1341 }
1342
1343 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1344 .set_gpu_state = azx_vs_set_state,
1345 .can_switch = azx_vs_can_switch,
1346 .gpu_bound = azx_vs_gpu_bound,
1347 };
1348
register_vga_switcheroo(struct azx * chip)1349 static int register_vga_switcheroo(struct azx *chip)
1350 {
1351 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1352 struct pci_dev *p;
1353 int err;
1354
1355 if (!hda->use_vga_switcheroo)
1356 return 0;
1357
1358 p = get_bound_vga(chip->pci);
1359 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1360 pci_dev_put(p);
1361
1362 if (err < 0)
1363 return err;
1364 hda->vga_switcheroo_registered = 1;
1365
1366 return 0;
1367 }
1368 #else
1369 #define init_vga_switcheroo(chip) /* NOP */
1370 #define register_vga_switcheroo(chip) 0
1371 #define check_hdmi_disabled(pci) false
1372 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1373 #endif /* SUPPORT_VGA_SWITCHER */
1374
1375 /*
1376 * destructor
1377 */
azx_free(struct azx * chip)1378 static void azx_free(struct azx *chip)
1379 {
1380 struct pci_dev *pci = chip->pci;
1381 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1382 struct hdac_bus *bus = azx_bus(chip);
1383
1384 if (hda->freed)
1385 return;
1386
1387 if (azx_has_pm_runtime(chip) && chip->running)
1388 pm_runtime_get_noresume(&pci->dev);
1389 chip->running = 0;
1390
1391 azx_del_card_list(chip);
1392
1393 hda->init_failed = 1; /* to be sure */
1394 complete_all(&hda->probe_wait);
1395
1396 if (use_vga_switcheroo(hda)) {
1397 if (chip->disabled && hda->probe_continued)
1398 snd_hda_unlock_devices(&chip->bus);
1399 if (hda->vga_switcheroo_registered)
1400 vga_switcheroo_unregister_client(chip->pci);
1401 }
1402
1403 if (bus->chip_init) {
1404 azx_clear_irq_pending(chip);
1405 azx_stop_all_streams(chip);
1406 azx_stop_chip(chip);
1407 }
1408
1409 if (bus->irq >= 0)
1410 free_irq(bus->irq, (void*)chip);
1411 if (chip->msi)
1412 pci_disable_msi(chip->pci);
1413 iounmap(bus->remap_addr);
1414
1415 azx_free_stream_pages(chip);
1416 azx_free_streams(chip);
1417 snd_hdac_bus_exit(bus);
1418
1419 if (chip->region_requested)
1420 pci_release_regions(chip->pci);
1421
1422 pci_disable_device(chip->pci);
1423 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1424 release_firmware(chip->fw);
1425 #endif
1426 display_power(chip, false);
1427
1428 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1429 snd_hdac_i915_exit(bus);
1430
1431 hda->freed = 1;
1432 }
1433
azx_dev_disconnect(struct snd_device * device)1434 static int azx_dev_disconnect(struct snd_device *device)
1435 {
1436 struct azx *chip = device->device_data;
1437 struct hdac_bus *bus = azx_bus(chip);
1438
1439 chip->bus.shutdown = 1;
1440 cancel_work_sync(&bus->unsol_work);
1441
1442 return 0;
1443 }
1444
azx_dev_free(struct snd_device * device)1445 static int azx_dev_free(struct snd_device *device)
1446 {
1447 azx_free(device->device_data);
1448 return 0;
1449 }
1450
1451 #ifdef SUPPORT_VGA_SWITCHEROO
1452 #ifdef CONFIG_ACPI
1453 /* ATPX is in the integrated GPU's namespace */
atpx_present(void)1454 static bool atpx_present(void)
1455 {
1456 struct pci_dev *pdev = NULL;
1457 acpi_handle dhandle, atpx_handle;
1458 acpi_status status;
1459
1460 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1461 dhandle = ACPI_HANDLE(&pdev->dev);
1462 if (dhandle) {
1463 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1464 if (!ACPI_FAILURE(status)) {
1465 pci_dev_put(pdev);
1466 return true;
1467 }
1468 }
1469 }
1470 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1471 dhandle = ACPI_HANDLE(&pdev->dev);
1472 if (dhandle) {
1473 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1474 if (!ACPI_FAILURE(status)) {
1475 pci_dev_put(pdev);
1476 return true;
1477 }
1478 }
1479 }
1480 return false;
1481 }
1482 #else
atpx_present(void)1483 static bool atpx_present(void)
1484 {
1485 return false;
1486 }
1487 #endif
1488
1489 /*
1490 * Check of disabled HDMI controller by vga_switcheroo
1491 */
get_bound_vga(struct pci_dev * pci)1492 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1493 {
1494 struct pci_dev *p;
1495
1496 /* check only discrete GPU */
1497 switch (pci->vendor) {
1498 case PCI_VENDOR_ID_ATI:
1499 case PCI_VENDOR_ID_AMD:
1500 if (pci->devfn == 1) {
1501 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1502 pci->bus->number, 0);
1503 if (p) {
1504 /* ATPX is in the integrated GPU's ACPI namespace
1505 * rather than the dGPU's namespace. However,
1506 * the dGPU is the one who is involved in
1507 * vgaswitcheroo.
1508 */
1509 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1510 atpx_present())
1511 return p;
1512 pci_dev_put(p);
1513 }
1514 }
1515 break;
1516 case PCI_VENDOR_ID_NVIDIA:
1517 if (pci->devfn == 1) {
1518 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1519 pci->bus->number, 0);
1520 if (p) {
1521 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1522 return p;
1523 pci_dev_put(p);
1524 }
1525 }
1526 break;
1527 }
1528 return NULL;
1529 }
1530
check_hdmi_disabled(struct pci_dev * pci)1531 static bool check_hdmi_disabled(struct pci_dev *pci)
1532 {
1533 bool vga_inactive = false;
1534 struct pci_dev *p = get_bound_vga(pci);
1535
1536 if (p) {
1537 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1538 vga_inactive = true;
1539 pci_dev_put(p);
1540 }
1541 return vga_inactive;
1542 }
1543 #endif /* SUPPORT_VGA_SWITCHEROO */
1544
1545 /*
1546 * allow/deny-listing for position_fix
1547 */
1548 static const struct snd_pci_quirk position_fix_list[] = {
1549 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1550 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1551 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1552 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1553 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1554 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1555 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1556 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1557 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1558 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1559 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1560 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1561 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1562 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1563 {}
1564 };
1565
check_position_fix(struct azx * chip,int fix)1566 static int check_position_fix(struct azx *chip, int fix)
1567 {
1568 const struct snd_pci_quirk *q;
1569
1570 switch (fix) {
1571 case POS_FIX_AUTO:
1572 case POS_FIX_LPIB:
1573 case POS_FIX_POSBUF:
1574 case POS_FIX_VIACOMBO:
1575 case POS_FIX_COMBO:
1576 case POS_FIX_SKL:
1577 case POS_FIX_FIFO:
1578 return fix;
1579 }
1580
1581 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1582 if (q) {
1583 dev_info(chip->card->dev,
1584 "position_fix set to %d for device %04x:%04x\n",
1585 q->value, q->subvendor, q->subdevice);
1586 return q->value;
1587 }
1588
1589 /* Check VIA/ATI HD Audio Controller exist */
1590 if (chip->driver_type == AZX_DRIVER_VIA) {
1591 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1592 return POS_FIX_VIACOMBO;
1593 }
1594 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1595 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1596 return POS_FIX_FIFO;
1597 }
1598 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1599 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1600 return POS_FIX_LPIB;
1601 }
1602 if (chip->driver_type == AZX_DRIVER_SKL) {
1603 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1604 return POS_FIX_SKL;
1605 }
1606 return POS_FIX_AUTO;
1607 }
1608
assign_position_fix(struct azx * chip,int fix)1609 static void assign_position_fix(struct azx *chip, int fix)
1610 {
1611 static const azx_get_pos_callback_t callbacks[] = {
1612 [POS_FIX_AUTO] = NULL,
1613 [POS_FIX_LPIB] = azx_get_pos_lpib,
1614 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1615 [POS_FIX_VIACOMBO] = azx_via_get_position,
1616 [POS_FIX_COMBO] = azx_get_pos_lpib,
1617 [POS_FIX_SKL] = azx_get_pos_posbuf,
1618 [POS_FIX_FIFO] = azx_get_pos_fifo,
1619 };
1620
1621 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1622
1623 /* combo mode uses LPIB only for playback */
1624 if (fix == POS_FIX_COMBO)
1625 chip->get_position[1] = NULL;
1626
1627 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1628 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1629 chip->get_delay[0] = chip->get_delay[1] =
1630 azx_get_delay_from_lpib;
1631 }
1632
1633 if (fix == POS_FIX_FIFO)
1634 chip->get_delay[0] = chip->get_delay[1] =
1635 azx_get_delay_from_fifo;
1636 }
1637
1638 /*
1639 * deny-lists for probe_mask
1640 */
1641 static const struct snd_pci_quirk probe_mask_list[] = {
1642 /* Thinkpad often breaks the controller communication when accessing
1643 * to the non-working (or non-existing) modem codec slot.
1644 */
1645 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1646 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1647 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1648 /* broken BIOS */
1649 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1650 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1651 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1652 /* forced codec slots */
1653 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1654 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1655 /* WinFast VP200 H (Teradici) user reported broken communication */
1656 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1657 {}
1658 };
1659
1660 #define AZX_FORCE_CODEC_MASK 0x100
1661
check_probe_mask(struct azx * chip,int dev)1662 static void check_probe_mask(struct azx *chip, int dev)
1663 {
1664 const struct snd_pci_quirk *q;
1665
1666 chip->codec_probe_mask = probe_mask[dev];
1667 if (chip->codec_probe_mask == -1) {
1668 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1669 if (q) {
1670 dev_info(chip->card->dev,
1671 "probe_mask set to 0x%x for device %04x:%04x\n",
1672 q->value, q->subvendor, q->subdevice);
1673 chip->codec_probe_mask = q->value;
1674 }
1675 }
1676
1677 /* check forced option */
1678 if (chip->codec_probe_mask != -1 &&
1679 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1680 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1681 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1682 (int)azx_bus(chip)->codec_mask);
1683 }
1684 }
1685
1686 /*
1687 * allow/deny-list for enable_msi
1688 */
1689 static const struct snd_pci_quirk msi_deny_list[] = {
1690 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1691 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1692 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1693 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1694 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1695 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1696 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1697 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1698 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1699 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1700 {}
1701 };
1702
check_msi(struct azx * chip)1703 static void check_msi(struct azx *chip)
1704 {
1705 const struct snd_pci_quirk *q;
1706
1707 if (enable_msi >= 0) {
1708 chip->msi = !!enable_msi;
1709 return;
1710 }
1711 chip->msi = 1; /* enable MSI as default */
1712 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1713 if (q) {
1714 dev_info(chip->card->dev,
1715 "msi for device %04x:%04x set to %d\n",
1716 q->subvendor, q->subdevice, q->value);
1717 chip->msi = q->value;
1718 return;
1719 }
1720
1721 /* NVidia chipsets seem to cause troubles with MSI */
1722 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1723 dev_info(chip->card->dev, "Disabling MSI\n");
1724 chip->msi = 0;
1725 }
1726 }
1727
1728 /* check the snoop mode availability */
azx_check_snoop_available(struct azx * chip)1729 static void azx_check_snoop_available(struct azx *chip)
1730 {
1731 int snoop = hda_snoop;
1732
1733 if (snoop >= 0) {
1734 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1735 snoop ? "snoop" : "non-snoop");
1736 chip->snoop = snoop;
1737 chip->uc_buffer = !snoop;
1738 return;
1739 }
1740
1741 snoop = true;
1742 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1743 chip->driver_type == AZX_DRIVER_VIA) {
1744 /* force to non-snoop mode for a new VIA controller
1745 * when BIOS is set
1746 */
1747 u8 val;
1748 pci_read_config_byte(chip->pci, 0x42, &val);
1749 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1750 chip->pci->revision == 0x20))
1751 snoop = false;
1752 }
1753
1754 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1755 snoop = false;
1756
1757 chip->snoop = snoop;
1758 if (!snoop) {
1759 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1760 /* C-Media requires non-cached pages only for CORB/RIRB */
1761 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1762 chip->uc_buffer = true;
1763 }
1764 }
1765
azx_probe_work(struct work_struct * work)1766 static void azx_probe_work(struct work_struct *work)
1767 {
1768 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1769 azx_probe_continue(&hda->chip);
1770 }
1771
default_bdl_pos_adj(struct azx * chip)1772 static int default_bdl_pos_adj(struct azx *chip)
1773 {
1774 /* some exceptions: Atoms seem problematic with value 1 */
1775 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1776 switch (chip->pci->device) {
1777 case 0x0f04: /* Baytrail */
1778 case 0x2284: /* Braswell */
1779 return 32;
1780 }
1781 }
1782
1783 switch (chip->driver_type) {
1784 case AZX_DRIVER_ICH:
1785 case AZX_DRIVER_PCH:
1786 return 1;
1787 default:
1788 return 32;
1789 }
1790 }
1791
1792 /*
1793 * constructor
1794 */
1795 static const struct hda_controller_ops pci_hda_ops;
1796
azx_create(struct snd_card * card,struct pci_dev * pci,int dev,unsigned int driver_caps,struct azx ** rchip)1797 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1798 int dev, unsigned int driver_caps,
1799 struct azx **rchip)
1800 {
1801 static const struct snd_device_ops ops = {
1802 .dev_disconnect = azx_dev_disconnect,
1803 .dev_free = azx_dev_free,
1804 };
1805 struct hda_intel *hda;
1806 struct azx *chip;
1807 int err;
1808
1809 *rchip = NULL;
1810
1811 err = pci_enable_device(pci);
1812 if (err < 0)
1813 return err;
1814
1815 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1816 if (!hda) {
1817 pci_disable_device(pci);
1818 return -ENOMEM;
1819 }
1820
1821 chip = &hda->chip;
1822 mutex_init(&chip->open_mutex);
1823 chip->card = card;
1824 chip->pci = pci;
1825 chip->ops = &pci_hda_ops;
1826 chip->driver_caps = driver_caps;
1827 chip->driver_type = driver_caps & 0xff;
1828 check_msi(chip);
1829 chip->dev_index = dev;
1830 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1831 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1832 INIT_LIST_HEAD(&chip->pcm_list);
1833 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1834 INIT_LIST_HEAD(&hda->list);
1835 init_vga_switcheroo(chip);
1836 init_completion(&hda->probe_wait);
1837
1838 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1839
1840 check_probe_mask(chip, dev);
1841
1842 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1843 chip->fallback_to_single_cmd = 1;
1844 else /* explicitly set to single_cmd or not */
1845 chip->single_cmd = single_cmd;
1846
1847 azx_check_snoop_available(chip);
1848
1849 if (bdl_pos_adj[dev] < 0)
1850 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1851 else
1852 chip->bdl_pos_adj = bdl_pos_adj[dev];
1853
1854 err = azx_bus_init(chip, model[dev]);
1855 if (err < 0) {
1856 pci_disable_device(pci);
1857 return err;
1858 }
1859
1860 /* use the non-cached pages in non-snoop mode */
1861 if (!azx_snoop(chip))
1862 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1863
1864 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1865 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1866 chip->bus.core.needs_damn_long_delay = 1;
1867 }
1868
1869 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1870 if (err < 0) {
1871 dev_err(card->dev, "Error creating device [card]!\n");
1872 azx_free(chip);
1873 return err;
1874 }
1875
1876 /* continue probing in work context as may trigger request module */
1877 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1878
1879 *rchip = chip;
1880
1881 return 0;
1882 }
1883
azx_first_init(struct azx * chip)1884 static int azx_first_init(struct azx *chip)
1885 {
1886 int dev = chip->dev_index;
1887 struct pci_dev *pci = chip->pci;
1888 struct snd_card *card = chip->card;
1889 struct hdac_bus *bus = azx_bus(chip);
1890 int err;
1891 unsigned short gcap;
1892 unsigned int dma_bits = 64;
1893
1894 #if BITS_PER_LONG != 64
1895 /* Fix up base address on ULI M5461 */
1896 if (chip->driver_type == AZX_DRIVER_ULI) {
1897 u16 tmp3;
1898 pci_read_config_word(pci, 0x40, &tmp3);
1899 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1900 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1901 }
1902 #endif
1903
1904 err = pci_request_regions(pci, "ICH HD audio");
1905 if (err < 0)
1906 return err;
1907 chip->region_requested = 1;
1908
1909 bus->addr = pci_resource_start(pci, 0);
1910 bus->remap_addr = pci_ioremap_bar(pci, 0);
1911 if (bus->remap_addr == NULL) {
1912 dev_err(card->dev, "ioremap error\n");
1913 return -ENXIO;
1914 }
1915
1916 if (chip->driver_type == AZX_DRIVER_SKL)
1917 snd_hdac_bus_parse_capabilities(bus);
1918
1919 /*
1920 * Some Intel CPUs has always running timer (ART) feature and
1921 * controller may have Global time sync reporting capability, so
1922 * check both of these before declaring synchronized time reporting
1923 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1924 */
1925 chip->gts_present = false;
1926
1927 #ifdef CONFIG_X86
1928 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1929 chip->gts_present = true;
1930 #endif
1931
1932 if (chip->msi) {
1933 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1934 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1935 pci->no_64bit_msi = true;
1936 }
1937 if (pci_enable_msi(pci) < 0)
1938 chip->msi = 0;
1939 }
1940
1941 pci_set_master(pci);
1942
1943 gcap = azx_readw(chip, GCAP);
1944 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1945
1946 /* AMD devices support 40 or 48bit DMA, take the safe one */
1947 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1948 dma_bits = 40;
1949
1950 /* disable SB600 64bit support for safety */
1951 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1952 struct pci_dev *p_smbus;
1953 dma_bits = 40;
1954 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1955 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1956 NULL);
1957 if (p_smbus) {
1958 if (p_smbus->revision < 0x30)
1959 gcap &= ~AZX_GCAP_64OK;
1960 pci_dev_put(p_smbus);
1961 }
1962 }
1963
1964 /* NVidia hardware normally only supports up to 40 bits of DMA */
1965 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1966 dma_bits = 40;
1967
1968 /* disable 64bit DMA address on some devices */
1969 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1970 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1971 gcap &= ~AZX_GCAP_64OK;
1972 }
1973
1974 /* disable buffer size rounding to 128-byte multiples if supported */
1975 if (align_buffer_size >= 0)
1976 chip->align_buffer_size = !!align_buffer_size;
1977 else {
1978 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1979 chip->align_buffer_size = 0;
1980 else
1981 chip->align_buffer_size = 1;
1982 }
1983
1984 /* allow 64bit DMA address if supported by H/W */
1985 if (!(gcap & AZX_GCAP_64OK))
1986 dma_bits = 32;
1987 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1988 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1989 } else {
1990 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1991 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1992 }
1993
1994 /* read number of streams from GCAP register instead of using
1995 * hardcoded value
1996 */
1997 chip->capture_streams = (gcap >> 8) & 0x0f;
1998 chip->playback_streams = (gcap >> 12) & 0x0f;
1999 if (!chip->playback_streams && !chip->capture_streams) {
2000 /* gcap didn't give any info, switching to old method */
2001
2002 switch (chip->driver_type) {
2003 case AZX_DRIVER_ULI:
2004 chip->playback_streams = ULI_NUM_PLAYBACK;
2005 chip->capture_streams = ULI_NUM_CAPTURE;
2006 break;
2007 case AZX_DRIVER_ATIHDMI:
2008 case AZX_DRIVER_ATIHDMI_NS:
2009 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2010 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2011 break;
2012 case AZX_DRIVER_GENERIC:
2013 default:
2014 chip->playback_streams = ICH6_NUM_PLAYBACK;
2015 chip->capture_streams = ICH6_NUM_CAPTURE;
2016 break;
2017 }
2018 }
2019 chip->capture_index_offset = 0;
2020 chip->playback_index_offset = chip->capture_streams;
2021 chip->num_streams = chip->playback_streams + chip->capture_streams;
2022
2023 /* sanity check for the SDxCTL.STRM field overflow */
2024 if (chip->num_streams > 15 &&
2025 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
2026 dev_warn(chip->card->dev, "number of I/O streams is %d, "
2027 "forcing separate stream tags", chip->num_streams);
2028 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2029 }
2030
2031 /* initialize streams */
2032 err = azx_init_streams(chip);
2033 if (err < 0)
2034 return err;
2035
2036 err = azx_alloc_stream_pages(chip);
2037 if (err < 0)
2038 return err;
2039
2040 /* initialize chip */
2041 azx_init_pci(chip);
2042
2043 snd_hdac_i915_set_bclk(bus);
2044
2045 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2046
2047 /* codec detection */
2048 if (!azx_bus(chip)->codec_mask) {
2049 dev_err(card->dev, "no codecs found!\n");
2050 /* keep running the rest for the runtime PM */
2051 }
2052
2053 if (azx_acquire_irq(chip, 0) < 0)
2054 return -EBUSY;
2055
2056 strcpy(card->driver, "HDA-Intel");
2057 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2058 sizeof(card->shortname));
2059 snprintf(card->longname, sizeof(card->longname),
2060 "%s at 0x%lx irq %i",
2061 card->shortname, bus->addr, bus->irq);
2062
2063 return 0;
2064 }
2065
2066 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2067 /* callback from request_firmware_nowait() */
azx_firmware_cb(const struct firmware * fw,void * context)2068 static void azx_firmware_cb(const struct firmware *fw, void *context)
2069 {
2070 struct snd_card *card = context;
2071 struct azx *chip = card->private_data;
2072
2073 if (fw)
2074 chip->fw = fw;
2075 else
2076 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2077 if (!chip->disabled) {
2078 /* continue probing */
2079 azx_probe_continue(chip);
2080 }
2081 }
2082 #endif
2083
disable_msi_reset_irq(struct azx * chip)2084 static int disable_msi_reset_irq(struct azx *chip)
2085 {
2086 struct hdac_bus *bus = azx_bus(chip);
2087 int err;
2088
2089 free_irq(bus->irq, chip);
2090 bus->irq = -1;
2091 chip->card->sync_irq = -1;
2092 pci_disable_msi(chip->pci);
2093 chip->msi = 0;
2094 err = azx_acquire_irq(chip, 1);
2095 if (err < 0)
2096 return err;
2097
2098 return 0;
2099 }
2100
pcm_mmap_prepare(struct snd_pcm_substream * substream,struct vm_area_struct * area)2101 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2102 struct vm_area_struct *area)
2103 {
2104 #ifdef CONFIG_X86
2105 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2106 struct azx *chip = apcm->chip;
2107 if (chip->uc_buffer)
2108 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2109 #endif
2110 }
2111
2112 /* Denylist for skipping the whole probe:
2113 * some HD-audio PCI entries are exposed without any codecs, and such devices
2114 * should be ignored from the beginning.
2115 */
2116 static const struct pci_device_id driver_denylist[] = {
2117 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2118 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2119 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2120 {}
2121 };
2122
2123 static const struct hda_controller_ops pci_hda_ops = {
2124 .disable_msi_reset_irq = disable_msi_reset_irq,
2125 .pcm_mmap_prepare = pcm_mmap_prepare,
2126 .position_check = azx_position_check,
2127 };
2128
azx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2129 static int azx_probe(struct pci_dev *pci,
2130 const struct pci_device_id *pci_id)
2131 {
2132 static int dev;
2133 struct snd_card *card;
2134 struct hda_intel *hda;
2135 struct azx *chip;
2136 bool schedule_probe;
2137 int err;
2138
2139 if (pci_match_id(driver_denylist, pci)) {
2140 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2141 return -ENODEV;
2142 }
2143
2144 if (dev >= SNDRV_CARDS)
2145 return -ENODEV;
2146 if (!enable[dev]) {
2147 dev++;
2148 return -ENOENT;
2149 }
2150
2151 /*
2152 * stop probe if another Intel's DSP driver should be activated
2153 */
2154 if (dmic_detect) {
2155 err = snd_intel_dsp_driver_probe(pci);
2156 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2157 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2158 return -ENODEV;
2159 }
2160 } else {
2161 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2162 }
2163
2164 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2165 0, &card);
2166 if (err < 0) {
2167 dev_err(&pci->dev, "Error creating card!\n");
2168 return err;
2169 }
2170
2171 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2172 if (err < 0)
2173 goto out_free;
2174 card->private_data = chip;
2175 hda = container_of(chip, struct hda_intel, chip);
2176
2177 pci_set_drvdata(pci, card);
2178
2179 err = register_vga_switcheroo(chip);
2180 if (err < 0) {
2181 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2182 goto out_free;
2183 }
2184
2185 if (check_hdmi_disabled(pci)) {
2186 dev_info(card->dev, "VGA controller is disabled\n");
2187 dev_info(card->dev, "Delaying initialization\n");
2188 chip->disabled = true;
2189 }
2190
2191 schedule_probe = !chip->disabled;
2192
2193 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2194 if (patch[dev] && *patch[dev]) {
2195 dev_info(card->dev, "Applying patch firmware '%s'\n",
2196 patch[dev]);
2197 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2198 &pci->dev, GFP_KERNEL, card,
2199 azx_firmware_cb);
2200 if (err < 0)
2201 goto out_free;
2202 schedule_probe = false; /* continued in azx_firmware_cb() */
2203 }
2204 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2205
2206 #ifndef CONFIG_SND_HDA_I915
2207 if (CONTROLLER_IN_GPU(pci))
2208 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2209 #endif
2210
2211 if (schedule_probe)
2212 schedule_delayed_work(&hda->probe_work, 0);
2213
2214 dev++;
2215 if (chip->disabled)
2216 complete_all(&hda->probe_wait);
2217 return 0;
2218
2219 out_free:
2220 snd_card_free(card);
2221 return err;
2222 }
2223
2224 #ifdef CONFIG_PM
2225 /* On some boards setting power_save to a non 0 value leads to clicking /
2226 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2227 * figure out how to avoid these sounds, but that is not always feasible.
2228 * So we keep a list of devices where we disable powersaving as its known
2229 * to causes problems on these devices.
2230 */
2231 static const struct snd_pci_quirk power_save_denylist[] = {
2232 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2233 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2234 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2235 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2236 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2237 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2238 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2239 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2240 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2241 SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
2242 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2243 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2244 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2245 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2246 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2247 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2248 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2249 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2250 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2251 /* https://bugs.launchpad.net/bugs/1821663 */
2252 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2253 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2254 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2255 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2256 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2257 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2258 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2259 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2260 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2261 /* https://bugs.launchpad.net/bugs/1821663 */
2262 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2263 {}
2264 };
2265 #endif /* CONFIG_PM */
2266
set_default_power_save(struct azx * chip)2267 static void set_default_power_save(struct azx *chip)
2268 {
2269 int val = power_save;
2270
2271 #ifdef CONFIG_PM
2272 if (pm_blacklist) {
2273 const struct snd_pci_quirk *q;
2274
2275 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2276 if (q && val) {
2277 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2278 q->subvendor, q->subdevice);
2279 val = 0;
2280 }
2281 }
2282 #endif /* CONFIG_PM */
2283 snd_hda_set_power_save(&chip->bus, val * 1000);
2284 }
2285
2286 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2287 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2288 [AZX_DRIVER_NVIDIA] = 8,
2289 [AZX_DRIVER_TERA] = 1,
2290 };
2291
azx_probe_continue(struct azx * chip)2292 static int azx_probe_continue(struct azx *chip)
2293 {
2294 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2295 struct hdac_bus *bus = azx_bus(chip);
2296 struct pci_dev *pci = chip->pci;
2297 int dev = chip->dev_index;
2298 int err;
2299
2300 if (chip->disabled || hda->init_failed)
2301 return -EIO;
2302 if (hda->probe_retry)
2303 goto probe_retry;
2304
2305 to_hda_bus(bus)->bus_probing = 1;
2306 hda->probe_continued = 1;
2307
2308 /* bind with i915 if needed */
2309 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2310 err = snd_hdac_i915_init(bus);
2311 if (err < 0) {
2312 /* if the controller is bound only with HDMI/DP
2313 * (for HSW and BDW), we need to abort the probe;
2314 * for other chips, still continue probing as other
2315 * codecs can be on the same link.
2316 */
2317 if (CONTROLLER_IN_GPU(pci)) {
2318 dev_err(chip->card->dev,
2319 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2320 goto out_free;
2321 } else {
2322 /* don't bother any longer */
2323 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2324 }
2325 }
2326
2327 /* HSW/BDW controllers need this power */
2328 if (CONTROLLER_IN_GPU(pci))
2329 hda->need_i915_power = 1;
2330 }
2331
2332 /* Request display power well for the HDA controller or codec. For
2333 * Haswell/Broadwell, both the display HDA controller and codec need
2334 * this power. For other platforms, like Baytrail/Braswell, only the
2335 * display codec needs the power and it can be released after probe.
2336 */
2337 display_power(chip, true);
2338
2339 err = azx_first_init(chip);
2340 if (err < 0)
2341 goto out_free;
2342
2343 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2344 chip->beep_mode = beep_mode[dev];
2345 #endif
2346
2347 /* create codec instances */
2348 if (bus->codec_mask) {
2349 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2350 if (err < 0)
2351 goto out_free;
2352 }
2353
2354 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2355 if (chip->fw) {
2356 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2357 chip->fw->data);
2358 if (err < 0)
2359 goto out_free;
2360 #ifndef CONFIG_PM
2361 release_firmware(chip->fw); /* no longer needed */
2362 chip->fw = NULL;
2363 #endif
2364 }
2365 #endif
2366
2367 probe_retry:
2368 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2369 err = azx_codec_configure(chip);
2370 if (err) {
2371 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2372 ++hda->probe_retry < 60) {
2373 schedule_delayed_work(&hda->probe_work,
2374 msecs_to_jiffies(1000));
2375 return 0; /* keep things up */
2376 }
2377 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2378 goto out_free;
2379 }
2380 }
2381
2382 err = snd_card_register(chip->card);
2383 if (err < 0)
2384 goto out_free;
2385
2386 setup_vga_switcheroo_runtime_pm(chip);
2387
2388 chip->running = 1;
2389 azx_add_card_list(chip);
2390
2391 set_default_power_save(chip);
2392
2393 if (azx_has_pm_runtime(chip)) {
2394 pm_runtime_use_autosuspend(&pci->dev);
2395 pm_runtime_allow(&pci->dev);
2396 pm_runtime_put_autosuspend(&pci->dev);
2397 }
2398
2399 out_free:
2400 if (err < 0) {
2401 pci_set_drvdata(pci, NULL);
2402 snd_card_free(chip->card);
2403 return err;
2404 }
2405
2406 if (!hda->need_i915_power)
2407 display_power(chip, false);
2408 complete_all(&hda->probe_wait);
2409 to_hda_bus(bus)->bus_probing = 0;
2410 hda->probe_retry = 0;
2411 return 0;
2412 }
2413
azx_remove(struct pci_dev * pci)2414 static void azx_remove(struct pci_dev *pci)
2415 {
2416 struct snd_card *card = pci_get_drvdata(pci);
2417 struct azx *chip;
2418 struct hda_intel *hda;
2419
2420 if (card) {
2421 /* cancel the pending probing work */
2422 chip = card->private_data;
2423 hda = container_of(chip, struct hda_intel, chip);
2424 /* FIXME: below is an ugly workaround.
2425 * Both device_release_driver() and driver_probe_device()
2426 * take *both* the device's and its parent's lock before
2427 * calling the remove() and probe() callbacks. The codec
2428 * probe takes the locks of both the codec itself and its
2429 * parent, i.e. the PCI controller dev. Meanwhile, when
2430 * the PCI controller is unbound, it takes its lock, too
2431 * ==> ouch, a deadlock!
2432 * As a workaround, we unlock temporarily here the controller
2433 * device during cancel_work_sync() call.
2434 */
2435 device_unlock(&pci->dev);
2436 cancel_delayed_work_sync(&hda->probe_work);
2437 device_lock(&pci->dev);
2438
2439 snd_card_free(card);
2440 }
2441 }
2442
azx_shutdown(struct pci_dev * pci)2443 static void azx_shutdown(struct pci_dev *pci)
2444 {
2445 struct snd_card *card = pci_get_drvdata(pci);
2446 struct azx *chip;
2447
2448 if (!card)
2449 return;
2450 chip = card->private_data;
2451 if (chip && chip->running)
2452 __azx_shutdown_chip(chip, true);
2453 }
2454
2455 /* PCI IDs */
2456 static const struct pci_device_id azx_ids[] = {
2457 /* CPT */
2458 { PCI_DEVICE(0x8086, 0x1c20),
2459 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2460 /* PBG */
2461 { PCI_DEVICE(0x8086, 0x1d20),
2462 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2463 /* Panther Point */
2464 { PCI_DEVICE(0x8086, 0x1e20),
2465 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2466 /* Lynx Point */
2467 { PCI_DEVICE(0x8086, 0x8c20),
2468 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2469 /* 9 Series */
2470 { PCI_DEVICE(0x8086, 0x8ca0),
2471 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2472 /* Wellsburg */
2473 { PCI_DEVICE(0x8086, 0x8d20),
2474 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2475 { PCI_DEVICE(0x8086, 0x8d21),
2476 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2477 /* Lewisburg */
2478 { PCI_DEVICE(0x8086, 0xa1f0),
2479 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2480 { PCI_DEVICE(0x8086, 0xa270),
2481 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2482 /* Lynx Point-LP */
2483 { PCI_DEVICE(0x8086, 0x9c20),
2484 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2485 /* Lynx Point-LP */
2486 { PCI_DEVICE(0x8086, 0x9c21),
2487 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2488 /* Wildcat Point-LP */
2489 { PCI_DEVICE(0x8086, 0x9ca0),
2490 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2491 /* Sunrise Point */
2492 { PCI_DEVICE(0x8086, 0xa170),
2493 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2494 /* Sunrise Point-LP */
2495 { PCI_DEVICE(0x8086, 0x9d70),
2496 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2497 /* Kabylake */
2498 { PCI_DEVICE(0x8086, 0xa171),
2499 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2500 /* Kabylake-LP */
2501 { PCI_DEVICE(0x8086, 0x9d71),
2502 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2503 /* Kabylake-H */
2504 { PCI_DEVICE(0x8086, 0xa2f0),
2505 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2506 /* Coffelake */
2507 { PCI_DEVICE(0x8086, 0xa348),
2508 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2509 /* Cannonlake */
2510 { PCI_DEVICE(0x8086, 0x9dc8),
2511 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2512 /* CometLake-LP */
2513 { PCI_DEVICE(0x8086, 0x02C8),
2514 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2515 /* CometLake-H */
2516 { PCI_DEVICE(0x8086, 0x06C8),
2517 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2518 { PCI_DEVICE(0x8086, 0xf1c8),
2519 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2520 /* CometLake-S */
2521 { PCI_DEVICE(0x8086, 0xa3f0),
2522 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2523 /* CometLake-R */
2524 { PCI_DEVICE(0x8086, 0xf0c8),
2525 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2526 /* Icelake */
2527 { PCI_DEVICE(0x8086, 0x34c8),
2528 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2529 /* Icelake-H */
2530 { PCI_DEVICE(0x8086, 0x3dc8),
2531 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2532 /* Jasperlake */
2533 { PCI_DEVICE(0x8086, 0x38c8),
2534 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2535 { PCI_DEVICE(0x8086, 0x4dc8),
2536 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2537 /* Tigerlake */
2538 { PCI_DEVICE(0x8086, 0xa0c8),
2539 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2540 /* Tigerlake-H */
2541 { PCI_DEVICE(0x8086, 0x43c8),
2542 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2543 /* DG1 */
2544 { PCI_DEVICE(0x8086, 0x490d),
2545 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2546 /* DG2 */
2547 { PCI_DEVICE(0x8086, 0x4f90),
2548 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2549 { PCI_DEVICE(0x8086, 0x4f91),
2550 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2551 { PCI_DEVICE(0x8086, 0x4f92),
2552 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2553 /* Alderlake-S */
2554 { PCI_DEVICE(0x8086, 0x7ad0),
2555 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2556 /* Alderlake-P */
2557 { PCI_DEVICE(0x8086, 0x51c8),
2558 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2559 /* Elkhart Lake */
2560 { PCI_DEVICE(0x8086, 0x4b55),
2561 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2562 { PCI_DEVICE(0x8086, 0x4b58),
2563 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2564 /* Broxton-P(Apollolake) */
2565 { PCI_DEVICE(0x8086, 0x5a98),
2566 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2567 /* Broxton-T */
2568 { PCI_DEVICE(0x8086, 0x1a98),
2569 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2570 /* Gemini-Lake */
2571 { PCI_DEVICE(0x8086, 0x3198),
2572 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2573 /* Haswell */
2574 { PCI_DEVICE(0x8086, 0x0a0c),
2575 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2576 { PCI_DEVICE(0x8086, 0x0c0c),
2577 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2578 { PCI_DEVICE(0x8086, 0x0d0c),
2579 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2580 /* Broadwell */
2581 { PCI_DEVICE(0x8086, 0x160c),
2582 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2583 /* 5 Series/3400 */
2584 { PCI_DEVICE(0x8086, 0x3b56),
2585 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2586 /* Poulsbo */
2587 { PCI_DEVICE(0x8086, 0x811b),
2588 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2589 /* Oaktrail */
2590 { PCI_DEVICE(0x8086, 0x080a),
2591 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2592 /* BayTrail */
2593 { PCI_DEVICE(0x8086, 0x0f04),
2594 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2595 /* Braswell */
2596 { PCI_DEVICE(0x8086, 0x2284),
2597 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2598 /* ICH6 */
2599 { PCI_DEVICE(0x8086, 0x2668),
2600 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2601 /* ICH7 */
2602 { PCI_DEVICE(0x8086, 0x27d8),
2603 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2604 /* ESB2 */
2605 { PCI_DEVICE(0x8086, 0x269a),
2606 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2607 /* ICH8 */
2608 { PCI_DEVICE(0x8086, 0x284b),
2609 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2610 /* ICH9 */
2611 { PCI_DEVICE(0x8086, 0x293e),
2612 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2613 /* ICH9 */
2614 { PCI_DEVICE(0x8086, 0x293f),
2615 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2616 /* ICH10 */
2617 { PCI_DEVICE(0x8086, 0x3a3e),
2618 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2619 /* ICH10 */
2620 { PCI_DEVICE(0x8086, 0x3a6e),
2621 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2622 /* Generic Intel */
2623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2624 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2625 .class_mask = 0xffffff,
2626 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2627 /* ATI SB 450/600/700/800/900 */
2628 { PCI_DEVICE(0x1002, 0x437b),
2629 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2630 { PCI_DEVICE(0x1002, 0x4383),
2631 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2632 /* AMD Hudson */
2633 { PCI_DEVICE(0x1022, 0x780d),
2634 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2635 /* AMD, X370 & co */
2636 { PCI_DEVICE(0x1022, 0x1457),
2637 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2638 /* AMD, X570 & co */
2639 { PCI_DEVICE(0x1022, 0x1487),
2640 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2641 /* AMD Stoney */
2642 { PCI_DEVICE(0x1022, 0x157a),
2643 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2644 AZX_DCAPS_PM_RUNTIME },
2645 /* AMD Raven */
2646 { PCI_DEVICE(0x1022, 0x15e3),
2647 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2648 /* ATI HDMI */
2649 { PCI_DEVICE(0x1002, 0x0002),
2650 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2651 { PCI_DEVICE(0x1002, 0x1308),
2652 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2653 { PCI_DEVICE(0x1002, 0x157a),
2654 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2655 { PCI_DEVICE(0x1002, 0x15b3),
2656 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2657 { PCI_DEVICE(0x1002, 0x793b),
2658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2659 { PCI_DEVICE(0x1002, 0x7919),
2660 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2661 { PCI_DEVICE(0x1002, 0x960f),
2662 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2663 { PCI_DEVICE(0x1002, 0x970f),
2664 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2665 { PCI_DEVICE(0x1002, 0x9840),
2666 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2667 { PCI_DEVICE(0x1002, 0xaa00),
2668 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2669 { PCI_DEVICE(0x1002, 0xaa08),
2670 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2671 { PCI_DEVICE(0x1002, 0xaa10),
2672 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2673 { PCI_DEVICE(0x1002, 0xaa18),
2674 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2675 { PCI_DEVICE(0x1002, 0xaa20),
2676 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2677 { PCI_DEVICE(0x1002, 0xaa28),
2678 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2679 { PCI_DEVICE(0x1002, 0xaa30),
2680 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2681 { PCI_DEVICE(0x1002, 0xaa38),
2682 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2683 { PCI_DEVICE(0x1002, 0xaa40),
2684 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2685 { PCI_DEVICE(0x1002, 0xaa48),
2686 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2687 { PCI_DEVICE(0x1002, 0xaa50),
2688 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2689 { PCI_DEVICE(0x1002, 0xaa58),
2690 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2691 { PCI_DEVICE(0x1002, 0xaa60),
2692 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2693 { PCI_DEVICE(0x1002, 0xaa68),
2694 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2695 { PCI_DEVICE(0x1002, 0xaa80),
2696 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2697 { PCI_DEVICE(0x1002, 0xaa88),
2698 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2699 { PCI_DEVICE(0x1002, 0xaa90),
2700 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2701 { PCI_DEVICE(0x1002, 0xaa98),
2702 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2703 { PCI_DEVICE(0x1002, 0x9902),
2704 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2705 { PCI_DEVICE(0x1002, 0xaaa0),
2706 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2707 { PCI_DEVICE(0x1002, 0xaaa8),
2708 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2709 { PCI_DEVICE(0x1002, 0xaab0),
2710 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2711 { PCI_DEVICE(0x1002, 0xaac0),
2712 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2713 { PCI_DEVICE(0x1002, 0xaac8),
2714 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2715 { PCI_DEVICE(0x1002, 0xaad8),
2716 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2717 AZX_DCAPS_PM_RUNTIME },
2718 { PCI_DEVICE(0x1002, 0xaae0),
2719 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2720 AZX_DCAPS_PM_RUNTIME },
2721 { PCI_DEVICE(0x1002, 0xaae8),
2722 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2723 AZX_DCAPS_PM_RUNTIME },
2724 { PCI_DEVICE(0x1002, 0xaaf0),
2725 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2726 AZX_DCAPS_PM_RUNTIME },
2727 { PCI_DEVICE(0x1002, 0xaaf8),
2728 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2729 AZX_DCAPS_PM_RUNTIME },
2730 { PCI_DEVICE(0x1002, 0xab00),
2731 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2732 AZX_DCAPS_PM_RUNTIME },
2733 { PCI_DEVICE(0x1002, 0xab08),
2734 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2735 AZX_DCAPS_PM_RUNTIME },
2736 { PCI_DEVICE(0x1002, 0xab10),
2737 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2738 AZX_DCAPS_PM_RUNTIME },
2739 { PCI_DEVICE(0x1002, 0xab18),
2740 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2741 AZX_DCAPS_PM_RUNTIME },
2742 { PCI_DEVICE(0x1002, 0xab20),
2743 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2744 AZX_DCAPS_PM_RUNTIME },
2745 { PCI_DEVICE(0x1002, 0xab28),
2746 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2747 AZX_DCAPS_PM_RUNTIME },
2748 { PCI_DEVICE(0x1002, 0xab38),
2749 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2750 AZX_DCAPS_PM_RUNTIME },
2751 /* VIA VT8251/VT8237A */
2752 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2753 /* VIA GFX VT7122/VX900 */
2754 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2755 /* VIA GFX VT6122/VX11 */
2756 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2757 /* SIS966 */
2758 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2759 /* ULI M5461 */
2760 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2761 /* NVIDIA MCP */
2762 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2763 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2764 .class_mask = 0xffffff,
2765 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2766 /* Teradici */
2767 { PCI_DEVICE(0x6549, 0x1200),
2768 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2769 { PCI_DEVICE(0x6549, 0x2200),
2770 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2771 /* Creative X-Fi (CA0110-IBG) */
2772 /* CTHDA chips */
2773 { PCI_DEVICE(0x1102, 0x0010),
2774 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2775 { PCI_DEVICE(0x1102, 0x0012),
2776 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2777 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2778 /* the following entry conflicts with snd-ctxfi driver,
2779 * as ctxfi driver mutates from HD-audio to native mode with
2780 * a special command sequence.
2781 */
2782 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2783 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2784 .class_mask = 0xffffff,
2785 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2786 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2787 #else
2788 /* this entry seems still valid -- i.e. without emu20kx chip */
2789 { PCI_DEVICE(0x1102, 0x0009),
2790 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2791 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2792 #endif
2793 /* CM8888 */
2794 { PCI_DEVICE(0x13f6, 0x5011),
2795 .driver_data = AZX_DRIVER_CMEDIA |
2796 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2797 /* Vortex86MX */
2798 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2799 /* VMware HDAudio */
2800 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2801 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2802 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2803 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2804 .class_mask = 0xffffff,
2805 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2806 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2807 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2808 .class_mask = 0xffffff,
2809 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2810 /* Zhaoxin */
2811 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2812 { 0, }
2813 };
2814 MODULE_DEVICE_TABLE(pci, azx_ids);
2815
2816 /* pci_driver definition */
2817 static struct pci_driver azx_driver = {
2818 .name = KBUILD_MODNAME,
2819 .id_table = azx_ids,
2820 .probe = azx_probe,
2821 .remove = azx_remove,
2822 .shutdown = azx_shutdown,
2823 .driver = {
2824 .pm = AZX_PM_OPS,
2825 },
2826 };
2827
2828 module_pci_driver(azx_driver);
2829