1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright 2018 NXP
3
4 #include <linux/clk.h>
5 #include <linux/device.h>
6 #include <linux/interrupt.h>
7 #include <linux/kobject.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_irq.h>
13 #include <linux/of_platform.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/sysfs.h>
17 #include <linux/types.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm.h>
20 #include <sound/soc.h>
21 #include <sound/tlv.h>
22 #include <sound/core.h>
23
24 #include "fsl_micfil.h"
25 #include "imx-pcm.h"
26
27 #define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
28 #define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
29
30 struct fsl_micfil {
31 struct platform_device *pdev;
32 struct regmap *regmap;
33 const struct fsl_micfil_soc_data *soc;
34 struct clk *mclk;
35 struct snd_dmaengine_dai_dma_data dma_params_rx;
36 unsigned int dataline;
37 char name[32];
38 int irq[MICFIL_IRQ_LINES];
39 unsigned int mclk_streams;
40 int quality; /*QUALITY 2-0 bits */
41 bool slave_mode;
42 int channel_gain[8];
43 };
44
45 struct fsl_micfil_soc_data {
46 unsigned int fifos;
47 unsigned int fifo_depth;
48 unsigned int dataline;
49 bool imx;
50 };
51
52 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
53 .imx = true,
54 .fifos = 8,
55 .fifo_depth = 8,
56 .dataline = 0xf,
57 };
58
59 static const struct of_device_id fsl_micfil_dt_ids[] = {
60 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
61 {}
62 };
63 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
64
65 /* Table 5. Quality Modes
66 * Medium 0 0 0
67 * High 0 0 1
68 * Very Low 2 1 0 0
69 * Very Low 1 1 0 1
70 * Very Low 0 1 1 0
71 * Low 1 1 1
72 */
73 static const char * const micfil_quality_select_texts[] = {
74 "Medium", "High",
75 "N/A", "N/A",
76 "VLow2", "VLow1",
77 "VLow0", "Low",
78 };
79
80 static const struct soc_enum fsl_micfil_quality_enum =
81 SOC_ENUM_SINGLE(REG_MICFIL_CTRL2,
82 MICFIL_CTRL2_QSEL_SHIFT,
83 ARRAY_SIZE(micfil_quality_select_texts),
84 micfil_quality_select_texts);
85
86 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
87
88 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
89 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
90 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv),
91 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
92 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0x7, gain_tlv),
93 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
94 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0x7, gain_tlv),
95 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
96 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0x7, gain_tlv),
97 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
98 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0x7, gain_tlv),
99 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
100 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0x7, gain_tlv),
101 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
102 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0x7, gain_tlv),
103 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
104 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv),
105 SOC_ENUM_EXT("MICFIL Quality Select",
106 fsl_micfil_quality_enum,
107 snd_soc_get_enum_double, snd_soc_put_enum_double),
108 };
109
get_pdm_clk(struct fsl_micfil * micfil,unsigned int rate)110 static inline int get_pdm_clk(struct fsl_micfil *micfil,
111 unsigned int rate)
112 {
113 u32 ctrl2_reg;
114 int qsel, osr;
115 int bclk;
116
117 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
118 osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
119 >> MICFIL_CTRL2_CICOSR_SHIFT);
120
121 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
122 qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
123
124 switch (qsel) {
125 case MICFIL_HIGH_QUALITY:
126 bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
127 break;
128 case MICFIL_MEDIUM_QUALITY:
129 case MICFIL_VLOW0_QUALITY:
130 bclk = rate * 4 * osr * 1; /* kfactor = 1 */
131 break;
132 case MICFIL_LOW_QUALITY:
133 case MICFIL_VLOW1_QUALITY:
134 bclk = rate * 2 * osr * 2; /* kfactor = 2 */
135 break;
136 case MICFIL_VLOW2_QUALITY:
137 bclk = rate * osr * 4; /* kfactor = 4 */
138 break;
139 default:
140 dev_err(&micfil->pdev->dev,
141 "Please make sure you select a valid quality.\n");
142 bclk = -1;
143 break;
144 }
145
146 return bclk;
147 }
148
get_clk_div(struct fsl_micfil * micfil,unsigned int rate)149 static inline int get_clk_div(struct fsl_micfil *micfil,
150 unsigned int rate)
151 {
152 u32 ctrl2_reg;
153 long mclk_rate;
154 int clk_div;
155
156 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
157
158 mclk_rate = clk_get_rate(micfil->mclk);
159
160 clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
161
162 return clk_div;
163 }
164
165 /* The SRES is a self-negated bit which provides the CPU with the
166 * capability to initialize the PDM Interface module through the
167 * slave-bus interface. This bit always reads as zero, and this
168 * bit is only effective when MDIS is cleared
169 */
fsl_micfil_reset(struct device * dev)170 static int fsl_micfil_reset(struct device *dev)
171 {
172 struct fsl_micfil *micfil = dev_get_drvdata(dev);
173 int ret;
174
175 ret = regmap_update_bits(micfil->regmap,
176 REG_MICFIL_CTRL1,
177 MICFIL_CTRL1_MDIS_MASK,
178 0);
179 if (ret) {
180 dev_err(dev, "failed to clear MDIS bit %d\n", ret);
181 return ret;
182 }
183
184 ret = regmap_update_bits(micfil->regmap,
185 REG_MICFIL_CTRL1,
186 MICFIL_CTRL1_SRES_MASK,
187 MICFIL_CTRL1_SRES);
188 if (ret) {
189 dev_err(dev, "failed to reset MICFIL: %d\n", ret);
190 return ret;
191 }
192
193 return 0;
194 }
195
fsl_micfil_set_mclk_rate(struct fsl_micfil * micfil,unsigned int freq)196 static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
197 unsigned int freq)
198 {
199 struct device *dev = &micfil->pdev->dev;
200 int ret;
201
202 clk_disable_unprepare(micfil->mclk);
203
204 ret = clk_set_rate(micfil->mclk, freq * 1024);
205 if (ret)
206 dev_warn(dev, "failed to set rate (%u): %d\n",
207 freq * 1024, ret);
208
209 clk_prepare_enable(micfil->mclk);
210
211 return ret;
212 }
213
fsl_micfil_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)214 static int fsl_micfil_startup(struct snd_pcm_substream *substream,
215 struct snd_soc_dai *dai)
216 {
217 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
218
219 if (!micfil) {
220 dev_err(dai->dev, "micfil dai priv_data not set\n");
221 return -EINVAL;
222 }
223
224 return 0;
225 }
226
fsl_micfil_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)227 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
228 struct snd_soc_dai *dai)
229 {
230 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
231 struct device *dev = &micfil->pdev->dev;
232 int ret;
233
234 switch (cmd) {
235 case SNDRV_PCM_TRIGGER_START:
236 case SNDRV_PCM_TRIGGER_RESUME:
237 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
238 ret = fsl_micfil_reset(dev);
239 if (ret) {
240 dev_err(dev, "failed to soft reset\n");
241 return ret;
242 }
243
244 /* DMA Interrupt Selection - DISEL bits
245 * 00 - DMA and IRQ disabled
246 * 01 - DMA req enabled
247 * 10 - IRQ enabled
248 * 11 - reserved
249 */
250 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
251 MICFIL_CTRL1_DISEL_MASK,
252 (1 << MICFIL_CTRL1_DISEL_SHIFT));
253 if (ret) {
254 dev_err(dev, "failed to update DISEL bits\n");
255 return ret;
256 }
257
258 /* Enable the module */
259 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
260 MICFIL_CTRL1_PDMIEN_MASK,
261 MICFIL_CTRL1_PDMIEN);
262 if (ret) {
263 dev_err(dev, "failed to enable the module\n");
264 return ret;
265 }
266
267 break;
268 case SNDRV_PCM_TRIGGER_STOP:
269 case SNDRV_PCM_TRIGGER_SUSPEND:
270 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
271 /* Disable the module */
272 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
273 MICFIL_CTRL1_PDMIEN_MASK,
274 0);
275 if (ret) {
276 dev_err(dev, "failed to enable the module\n");
277 return ret;
278 }
279
280 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
281 MICFIL_CTRL1_DISEL_MASK,
282 (0 << MICFIL_CTRL1_DISEL_SHIFT));
283 if (ret) {
284 dev_err(dev, "failed to update DISEL bits\n");
285 return ret;
286 }
287 break;
288 default:
289 return -EINVAL;
290 }
291 return 0;
292 }
293
fsl_set_clock_params(struct device * dev,unsigned int rate)294 static int fsl_set_clock_params(struct device *dev, unsigned int rate)
295 {
296 struct fsl_micfil *micfil = dev_get_drvdata(dev);
297 int clk_div;
298 int ret;
299
300 ret = fsl_micfil_set_mclk_rate(micfil, rate);
301 if (ret < 0)
302 dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
303 clk_get_rate(micfil->mclk), rate);
304
305 /* set CICOSR */
306 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
307 MICFIL_CTRL2_CICOSR_MASK,
308 MICFIL_CTRL2_OSR_DEFAULT);
309 if (ret)
310 dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
311 REG_MICFIL_CTRL2);
312
313 /* set CLK_DIV */
314 clk_div = get_clk_div(micfil, rate);
315 if (clk_div < 0)
316 ret = -EINVAL;
317
318 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
319 MICFIL_CTRL2_CLKDIV_MASK, clk_div);
320 if (ret)
321 dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
322 REG_MICFIL_CTRL2);
323
324 return ret;
325 }
326
fsl_micfil_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)327 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
328 struct snd_pcm_hw_params *params,
329 struct snd_soc_dai *dai)
330 {
331 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
332 unsigned int channels = params_channels(params);
333 unsigned int rate = params_rate(params);
334 struct device *dev = &micfil->pdev->dev;
335 int ret;
336
337 /* 1. Disable the module */
338 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
339 MICFIL_CTRL1_PDMIEN_MASK, 0);
340 if (ret) {
341 dev_err(dev, "failed to disable the module\n");
342 return ret;
343 }
344
345 /* enable channels */
346 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
347 0xFF, ((1 << channels) - 1));
348 if (ret) {
349 dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
350 REG_MICFIL_CTRL1);
351 return ret;
352 }
353
354 ret = fsl_set_clock_params(dev, rate);
355 if (ret < 0) {
356 dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
357 return ret;
358 }
359
360 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
361
362 return 0;
363 }
364
fsl_micfil_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)365 static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
366 unsigned int freq, int dir)
367 {
368 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
369 struct device *dev = &micfil->pdev->dev;
370
371 int ret;
372
373 if (!freq)
374 return 0;
375
376 ret = fsl_micfil_set_mclk_rate(micfil, freq);
377 if (ret < 0)
378 dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
379 clk_get_rate(micfil->mclk), freq);
380
381 return ret;
382 }
383
384 static struct snd_soc_dai_ops fsl_micfil_dai_ops = {
385 .startup = fsl_micfil_startup,
386 .trigger = fsl_micfil_trigger,
387 .hw_params = fsl_micfil_hw_params,
388 .set_sysclk = fsl_micfil_set_dai_sysclk,
389 };
390
fsl_micfil_dai_probe(struct snd_soc_dai * cpu_dai)391 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
392 {
393 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
394 struct device *dev = cpu_dai->dev;
395 unsigned int val;
396 int ret;
397 int i;
398
399 /* set qsel to medium */
400 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
401 MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
402 if (ret) {
403 dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
404 REG_MICFIL_CTRL2);
405 return ret;
406 }
407
408 /* set default gain to max_gain */
409 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
410 for (i = 0; i < 8; i++)
411 micfil->channel_gain[i] = 0xF;
412
413 snd_soc_dai_init_dma_data(cpu_dai, NULL,
414 &micfil->dma_params_rx);
415
416 /* FIFO Watermark Control - FIFOWMK*/
417 val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
418 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
419 MICFIL_FIFO_CTRL_FIFOWMK_MASK,
420 val);
421 if (ret) {
422 dev_err(dev, "failed to set FIFOWMK\n");
423 return ret;
424 }
425
426 snd_soc_dai_set_drvdata(cpu_dai, micfil);
427
428 return 0;
429 }
430
431 static struct snd_soc_dai_driver fsl_micfil_dai = {
432 .probe = fsl_micfil_dai_probe,
433 .capture = {
434 .stream_name = "CPU-Capture",
435 .channels_min = 1,
436 .channels_max = 8,
437 .rates = FSL_MICFIL_RATES,
438 .formats = FSL_MICFIL_FORMATS,
439 },
440 .ops = &fsl_micfil_dai_ops,
441 };
442
443 static const struct snd_soc_component_driver fsl_micfil_component = {
444 .name = "fsl-micfil-dai",
445 .controls = fsl_micfil_snd_controls,
446 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
447
448 };
449
450 /* REGMAP */
451 static const struct reg_default fsl_micfil_reg_defaults[] = {
452 {REG_MICFIL_CTRL1, 0x00000000},
453 {REG_MICFIL_CTRL2, 0x00000000},
454 {REG_MICFIL_STAT, 0x00000000},
455 {REG_MICFIL_FIFO_CTRL, 0x00000007},
456 {REG_MICFIL_FIFO_STAT, 0x00000000},
457 {REG_MICFIL_DATACH0, 0x00000000},
458 {REG_MICFIL_DATACH1, 0x00000000},
459 {REG_MICFIL_DATACH2, 0x00000000},
460 {REG_MICFIL_DATACH3, 0x00000000},
461 {REG_MICFIL_DATACH4, 0x00000000},
462 {REG_MICFIL_DATACH5, 0x00000000},
463 {REG_MICFIL_DATACH6, 0x00000000},
464 {REG_MICFIL_DATACH7, 0x00000000},
465 {REG_MICFIL_DC_CTRL, 0x00000000},
466 {REG_MICFIL_OUT_CTRL, 0x00000000},
467 {REG_MICFIL_OUT_STAT, 0x00000000},
468 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
469 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
470 {REG_MICFIL_VAD0_STAT, 0x00000000},
471 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
472 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
473 {REG_MICFIL_VAD0_NDATA, 0x00000000},
474 {REG_MICFIL_VAD0_ZCD, 0x00000004},
475 };
476
fsl_micfil_readable_reg(struct device * dev,unsigned int reg)477 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
478 {
479 switch (reg) {
480 case REG_MICFIL_CTRL1:
481 case REG_MICFIL_CTRL2:
482 case REG_MICFIL_STAT:
483 case REG_MICFIL_FIFO_CTRL:
484 case REG_MICFIL_FIFO_STAT:
485 case REG_MICFIL_DATACH0:
486 case REG_MICFIL_DATACH1:
487 case REG_MICFIL_DATACH2:
488 case REG_MICFIL_DATACH3:
489 case REG_MICFIL_DATACH4:
490 case REG_MICFIL_DATACH5:
491 case REG_MICFIL_DATACH6:
492 case REG_MICFIL_DATACH7:
493 case REG_MICFIL_DC_CTRL:
494 case REG_MICFIL_OUT_CTRL:
495 case REG_MICFIL_OUT_STAT:
496 case REG_MICFIL_VAD0_CTRL1:
497 case REG_MICFIL_VAD0_CTRL2:
498 case REG_MICFIL_VAD0_STAT:
499 case REG_MICFIL_VAD0_SCONFIG:
500 case REG_MICFIL_VAD0_NCONFIG:
501 case REG_MICFIL_VAD0_NDATA:
502 case REG_MICFIL_VAD0_ZCD:
503 return true;
504 default:
505 return false;
506 }
507 }
508
fsl_micfil_writeable_reg(struct device * dev,unsigned int reg)509 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
510 {
511 switch (reg) {
512 case REG_MICFIL_CTRL1:
513 case REG_MICFIL_CTRL2:
514 case REG_MICFIL_STAT: /* Write 1 to Clear */
515 case REG_MICFIL_FIFO_CTRL:
516 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
517 case REG_MICFIL_DC_CTRL:
518 case REG_MICFIL_OUT_CTRL:
519 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
520 case REG_MICFIL_VAD0_CTRL1:
521 case REG_MICFIL_VAD0_CTRL2:
522 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
523 case REG_MICFIL_VAD0_SCONFIG:
524 case REG_MICFIL_VAD0_NCONFIG:
525 case REG_MICFIL_VAD0_ZCD:
526 return true;
527 default:
528 return false;
529 }
530 }
531
fsl_micfil_volatile_reg(struct device * dev,unsigned int reg)532 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
533 {
534 switch (reg) {
535 case REG_MICFIL_STAT:
536 case REG_MICFIL_DATACH0:
537 case REG_MICFIL_DATACH1:
538 case REG_MICFIL_DATACH2:
539 case REG_MICFIL_DATACH3:
540 case REG_MICFIL_DATACH4:
541 case REG_MICFIL_DATACH5:
542 case REG_MICFIL_DATACH6:
543 case REG_MICFIL_DATACH7:
544 case REG_MICFIL_VAD0_STAT:
545 case REG_MICFIL_VAD0_NDATA:
546 return true;
547 default:
548 return false;
549 }
550 }
551
552 static const struct regmap_config fsl_micfil_regmap_config = {
553 .reg_bits = 32,
554 .reg_stride = 4,
555 .val_bits = 32,
556
557 .max_register = REG_MICFIL_VAD0_ZCD,
558 .reg_defaults = fsl_micfil_reg_defaults,
559 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
560 .readable_reg = fsl_micfil_readable_reg,
561 .volatile_reg = fsl_micfil_volatile_reg,
562 .writeable_reg = fsl_micfil_writeable_reg,
563 .cache_type = REGCACHE_RBTREE,
564 };
565
566 /* END OF REGMAP */
567
micfil_isr(int irq,void * devid)568 static irqreturn_t micfil_isr(int irq, void *devid)
569 {
570 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
571 struct platform_device *pdev = micfil->pdev;
572 u32 stat_reg;
573 u32 fifo_stat_reg;
574 u32 ctrl1_reg;
575 bool dma_enabled;
576 int i;
577
578 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
579 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
580 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
581
582 dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
583
584 /* Channel 0-7 Output Data Flags */
585 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
586 if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
587 dev_dbg(&pdev->dev,
588 "Data available in Data Channel %d\n", i);
589 /* if DMA is not enabled, field must be written with 1
590 * to clear
591 */
592 if (!dma_enabled)
593 regmap_write_bits(micfil->regmap,
594 REG_MICFIL_STAT,
595 MICFIL_STAT_CHXF_MASK(i),
596 1);
597 }
598
599 for (i = 0; i < MICFIL_FIFO_NUM; i++) {
600 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i))
601 dev_dbg(&pdev->dev,
602 "FIFO Overflow Exception flag for channel %d\n",
603 i);
604
605 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i))
606 dev_dbg(&pdev->dev,
607 "FIFO Underflow Exception flag for channel %d\n",
608 i);
609 }
610
611 return IRQ_HANDLED;
612 }
613
micfil_err_isr(int irq,void * devid)614 static irqreturn_t micfil_err_isr(int irq, void *devid)
615 {
616 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
617 struct platform_device *pdev = micfil->pdev;
618 u32 stat_reg;
619
620 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
621
622 if (stat_reg & MICFIL_STAT_BSY_FIL_MASK)
623 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
624
625 if (stat_reg & MICFIL_STAT_FIR_RDY_MASK)
626 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
627
628 if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) {
629 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
630 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
631 MICFIL_STAT_LOWFREQF_MASK, 1);
632 }
633
634 return IRQ_HANDLED;
635 }
636
fsl_micfil_probe(struct platform_device * pdev)637 static int fsl_micfil_probe(struct platform_device *pdev)
638 {
639 struct device_node *np = pdev->dev.of_node;
640 const struct of_device_id *of_id;
641 struct fsl_micfil *micfil;
642 struct resource *res;
643 void __iomem *regs;
644 int ret, i;
645 unsigned long irqflag = 0;
646
647 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
648 if (!micfil)
649 return -ENOMEM;
650
651 micfil->pdev = pdev;
652 strncpy(micfil->name, np->name, sizeof(micfil->name) - 1);
653
654 of_id = of_match_device(fsl_micfil_dt_ids, &pdev->dev);
655 if (!of_id || !of_id->data)
656 return -EINVAL;
657
658 micfil->soc = of_id->data;
659
660 /* ipg_clk is used to control the registers
661 * ipg_clk_app is used to operate the filter
662 */
663 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
664 if (IS_ERR(micfil->mclk)) {
665 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
666 PTR_ERR(micfil->mclk));
667 return PTR_ERR(micfil->mclk);
668 }
669
670 /* init regmap */
671 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
672 regs = devm_ioremap_resource(&pdev->dev, res);
673 if (IS_ERR(regs))
674 return PTR_ERR(regs);
675
676 micfil->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
677 "ipg_clk",
678 regs,
679 &fsl_micfil_regmap_config);
680 if (IS_ERR(micfil->regmap)) {
681 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
682 PTR_ERR(micfil->regmap));
683 return PTR_ERR(micfil->regmap);
684 }
685
686 /* dataline mask for RX */
687 ret = of_property_read_u32_index(np,
688 "fsl,dataline",
689 0,
690 &micfil->dataline);
691 if (ret)
692 micfil->dataline = 1;
693
694 if (micfil->dataline & ~micfil->soc->dataline) {
695 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
696 micfil->soc->dataline);
697 return -EINVAL;
698 }
699
700 /* get IRQs */
701 for (i = 0; i < MICFIL_IRQ_LINES; i++) {
702 micfil->irq[i] = platform_get_irq(pdev, i);
703 dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]);
704 if (micfil->irq[i] < 0)
705 return micfil->irq[i];
706 }
707
708 if (of_property_read_bool(np, "fsl,shared-interrupt"))
709 irqflag = IRQF_SHARED;
710
711 /* Digital Microphone interface interrupt */
712 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
713 micfil_isr, irqflag,
714 micfil->name, micfil);
715 if (ret) {
716 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
717 micfil->irq[0]);
718 return ret;
719 }
720
721 /* Digital Microphone interface error interrupt */
722 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
723 micfil_err_isr, irqflag,
724 micfil->name, micfil);
725 if (ret) {
726 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
727 micfil->irq[1]);
728 return ret;
729 }
730
731 micfil->dma_params_rx.chan_name = "rx";
732 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
733 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
734
735
736 platform_set_drvdata(pdev, micfil);
737
738 pm_runtime_enable(&pdev->dev);
739
740 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
741 &fsl_micfil_dai, 1);
742 if (ret) {
743 dev_err(&pdev->dev, "failed to register component %s\n",
744 fsl_micfil_component.name);
745 return ret;
746 }
747
748 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
749 if (ret)
750 dev_err(&pdev->dev, "failed to pcm register\n");
751
752 return ret;
753 }
754
fsl_micfil_runtime_suspend(struct device * dev)755 static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev)
756 {
757 struct fsl_micfil *micfil = dev_get_drvdata(dev);
758
759 regcache_cache_only(micfil->regmap, true);
760
761 clk_disable_unprepare(micfil->mclk);
762
763 return 0;
764 }
765
fsl_micfil_runtime_resume(struct device * dev)766 static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev)
767 {
768 struct fsl_micfil *micfil = dev_get_drvdata(dev);
769 int ret;
770
771 ret = clk_prepare_enable(micfil->mclk);
772 if (ret < 0)
773 return ret;
774
775 regcache_cache_only(micfil->regmap, false);
776 regcache_mark_dirty(micfil->regmap);
777 regcache_sync(micfil->regmap);
778
779 return 0;
780 }
781
fsl_micfil_suspend(struct device * dev)782 static int __maybe_unused fsl_micfil_suspend(struct device *dev)
783 {
784 pm_runtime_force_suspend(dev);
785
786 return 0;
787 }
788
fsl_micfil_resume(struct device * dev)789 static int __maybe_unused fsl_micfil_resume(struct device *dev)
790 {
791 pm_runtime_force_resume(dev);
792
793 return 0;
794 }
795
796 static const struct dev_pm_ops fsl_micfil_pm_ops = {
797 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
798 fsl_micfil_runtime_resume,
799 NULL)
800 SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend,
801 fsl_micfil_resume)
802 };
803
804 static struct platform_driver fsl_micfil_driver = {
805 .probe = fsl_micfil_probe,
806 .driver = {
807 .name = "fsl-micfil-dai",
808 .pm = &fsl_micfil_pm_ops,
809 .of_match_table = fsl_micfil_dt_ids,
810 },
811 };
812 module_platform_driver(fsl_micfil_driver);
813
814 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
815 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
816 MODULE_LICENSE("GPL v2");
817