1 // Copyright 2017 The Abseil Authors.
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // https://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "absl/base/internal/unscaledcycleclock.h"
16
17 #if ABSL_USE_UNSCALED_CYCLECLOCK
18
19 #if defined(_WIN32)
20 #include <intrin.h>
21 #endif
22
23 #if defined(__powerpc__) || defined(__ppc__)
24 #ifdef __GLIBC__
25 #include <sys/platform/ppc.h>
26 #elif defined(__FreeBSD__)
27 #include <sys/sysctl.h>
28 #include <sys/types.h>
29 #endif
30 #endif
31
32 #include "absl/base/internal/sysinfo.h"
33
34 namespace absl {
35 ABSL_NAMESPACE_BEGIN
36 namespace base_internal {
37
38 #if defined(__i386__)
39
Now()40 int64_t UnscaledCycleClock::Now() {
41 int64_t ret;
42 __asm__ volatile("rdtsc" : "=A"(ret));
43 return ret;
44 }
45
Frequency()46 double UnscaledCycleClock::Frequency() {
47 return base_internal::NominalCPUFrequency();
48 }
49
50 #elif defined(__x86_64__)
51
52 int64_t UnscaledCycleClock::Now() {
53 uint64_t low, high;
54 __asm__ volatile("rdtsc" : "=a"(low), "=d"(high));
55 return (high << 32) | low;
56 }
57
58 double UnscaledCycleClock::Frequency() {
59 return base_internal::NominalCPUFrequency();
60 }
61
62 #elif defined(__powerpc__) || defined(__ppc__)
63
64 int64_t UnscaledCycleClock::Now() {
65 #ifdef __GLIBC__
66 return __ppc_get_timebase();
67 #else
68 #ifdef __powerpc64__
69 int64_t tbr;
70 asm volatile("mfspr %0, 268" : "=r"(tbr));
71 return tbr;
72 #else
73 int32_t tbu, tbl, tmp;
74 asm volatile(
75 "0:\n"
76 "mftbu %[hi32]\n"
77 "mftb %[lo32]\n"
78 "mftbu %[tmp]\n"
79 "cmpw %[tmp],%[hi32]\n"
80 "bne 0b\n"
81 : [ hi32 ] "=r"(tbu), [ lo32 ] "=r"(tbl), [ tmp ] "=r"(tmp));
82 return (static_cast<int64_t>(tbu) << 32) | tbl;
83 #endif
84 #endif
85 }
86
87 double UnscaledCycleClock::Frequency() {
88 #ifdef __GLIBC__
89 return __ppc_get_timebase_freq();
90 #elif defined(__FreeBSD__)
91 static once_flag init_timebase_frequency_once;
92 static double timebase_frequency = 0.0;
93 base_internal::LowLevelCallOnce(&init_timebase_frequency_once, [&]() {
94 size_t length = sizeof(timebase_frequency);
95 sysctlbyname("kern.timecounter.tc.timebase.frequency", &timebase_frequency,
96 &length, nullptr, 0);
97 });
98 return timebase_frequency;
99 #else
100 #error Must implement UnscaledCycleClock::Frequency()
101 #endif
102 }
103
104 #elif defined(__aarch64__)
105
106 // System timer of ARMv8 runs at a different frequency than the CPU's.
107 // The frequency is fixed, typically in the range 1-50MHz. It can be
108 // read at CNTFRQ special register. We assume the OS has set up
109 // the virtual timer properly.
110 int64_t UnscaledCycleClock::Now() {
111 int64_t virtual_timer_value;
112 asm volatile("mrs %0, cntvct_el0" : "=r"(virtual_timer_value));
113 return virtual_timer_value;
114 }
115
116 double UnscaledCycleClock::Frequency() {
117 uint64_t aarch64_timer_frequency;
118 asm volatile("mrs %0, cntfrq_el0" : "=r"(aarch64_timer_frequency));
119 return aarch64_timer_frequency;
120 }
121
122 #elif defined(_M_IX86) || defined(_M_X64)
123
124 #pragma intrinsic(__rdtsc)
125
126 int64_t UnscaledCycleClock::Now() {
127 return __rdtsc();
128 }
129
130 double UnscaledCycleClock::Frequency() {
131 return base_internal::NominalCPUFrequency();
132 }
133
134 #endif
135
136 } // namespace base_internal
137 ABSL_NAMESPACE_END
138 } // namespace absl
139
140 #endif // ABSL_USE_UNSCALED_CYCLECLOCK
141